Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T179,T182,T310
0	1	Covered	T179,T182,T310
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T179,T182,T310
1	Covered	T179,T182,T310

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T179,T182,T310
1	Covered	T179,T182,T310

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T179,T182,T310
1	1	Covered	T179,T182,T310

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T179,T182,T310
1	0	Covered	T179,T182,T310
1	1	Covered	T179,T182,T310

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T179,T182,T310

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T179,T182,T310
0	Covered	T179,T182,T310

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T179,T182,T310
0	Covered	T179,T182,T310

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1044153304	1025628880	0	0
CheckNGreaterZero_A	2056	2056	0	0
GntImpliesReady_A	1044153304	8386	0	0
GntImpliesValid_A	1044153304	8386	0	0
GrantKnown_A	1044153304	1025628880	0	0
IdxKnown_A	1044153304	1025628880	0	0
IndexIsCorrect_A	1044153304	8386	0	0
NoReadyValidNoGrant_A	1044153304	0	0	0
Priority_A	1044153304	8386	0	0
ReadyAndValidImplyGrant_A	1044153304	8386	0	0
ReqAndReadyImplyGrant_A	1044153304	8386	0	0
ReqImpliesValid_A	1044153304	8386	0	0
ValidKnown_A	1044153304	1025628880	0	0
gen_data_port_assertion.DataFlow_A	1044153304	8386	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1044153304	1025628880	0	0
T1	845806	845690	0	0
T2	256474	256262	0	0
T3	557712	557472	0	0
T4	1514668	1514646	0	0
T5	1308314	1308204	0	0
T6	499470	499036	0	0
T7	111996	111762	0	0
T8	311022	310998	0	0
T80	416032	415800	0	0
T81	325248	325138	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2056	2056	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T5	2	2	0	0
T6	2	2	0	0
T7	2	2	0	0
T8	2	2	0	0
T80	2	2	0	0
T81	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1044153304	8386	0	0
T112	431116	0	0	0
T153	1041494	0	0	0
T179	157246	2798	0	0
T182	0	2795	0	0
T234	1988524	0	0	0
T310	0	2793	0	0
T312	174090	0	0	0
T313	154748	0	0	0
T314	268096	0	0	0
T315	373764	0	0	0
T316	511942	0	0	0
T317	381014	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1044153304	8386	0	0
T112	431116	0	0	0
T153	1041494	0	0	0
T179	157246	2798	0	0
T182	0	2795	0	0
T234	1988524	0	0	0
T310	0	2793	0	0
T312	174090	0	0	0
T313	154748	0	0	0
T314	268096	0	0	0
T315	373764	0	0	0
T316	511942	0	0	0
T317	381014	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1044153304	1025628880	0	0
T1	845806	845690	0	0
T2	256474	256262	0	0
T3	557712	557472	0	0
T4	1514668	1514646	0	0
T5	1308314	1308204	0	0
T6	499470	499036	0	0
T7	111996	111762	0	0
T8	311022	310998	0	0
T80	416032	415800	0	0
T81	325248	325138	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1044153304	1025628880	0	0
T1	845806	845690	0	0
T2	256474	256262	0	0
T3	557712	557472	0	0
T4	1514668	1514646	0	0
T5	1308314	1308204	0	0
T6	499470	499036	0	0
T7	111996	111762	0	0
T8	311022	310998	0	0
T80	416032	415800	0	0
T81	325248	325138	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1044153304	8386	0	0
T112	431116	0	0	0
T153	1041494	0	0	0
T179	157246	2798	0	0
T182	0	2795	0	0
T234	1988524	0	0	0
T310	0	2793	0	0
T312	174090	0	0	0
T313	154748	0	0	0
T314	268096	0	0	0
T315	373764	0	0	0
T316	511942	0	0	0
T317	381014	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1044153304	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1044153304	8386	0	0
T112	431116	0	0	0
T153	1041494	0	0	0
T179	157246	2798	0	0
T182	0	2795	0	0
T234	1988524	0	0	0
T310	0	2793	0	0
T312	174090	0	0	0
T313	154748	0	0	0
T314	268096	0	0	0
T315	373764	0	0	0
T316	511942	0	0	0
T317	381014	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1044153304	8386	0	0
T112	431116	0	0	0
T153	1041494	0	0	0
T179	157246	2798	0	0
T182	0	2795	0	0
T234	1988524	0	0	0
T310	0	2793	0	0
T312	174090	0	0	0
T313	154748	0	0	0
T314	268096	0	0	0
T315	373764	0	0	0
T316	511942	0	0	0
T317	381014	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1044153304	8386	0	0
T112	431116	0	0	0
T153	1041494	0	0	0
T179	157246	2798	0	0
T182	0	2795	0	0
T234	1988524	0	0	0
T310	0	2793	0	0
T312	174090	0	0	0
T313	154748	0	0	0
T314	268096	0	0	0
T315	373764	0	0	0
T316	511942	0	0	0
T317	381014	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1044153304	8386	0	0
T112	431116	0	0	0
T153	1041494	0	0	0
T179	157246	2798	0	0
T182	0	2795	0	0
T234	1988524	0	0	0
T310	0	2793	0	0
T312	174090	0	0	0
T313	154748	0	0	0
T314	268096	0	0	0
T315	373764	0	0	0
T316	511942	0	0	0
T317	381014	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1044153304	1025628880	0	0
T1	845806	845690	0	0
T2	256474	256262	0	0
T3	557712	557472	0	0
T4	1514668	1514646	0	0
T5	1308314	1308204	0	0
T6	499470	499036	0	0
T7	111996	111762	0	0
T8	311022	310998	0	0
T80	416032	415800	0	0
T81	325248	325138	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1044153304	8386	0	0
T112	431116	0	0	0
T153	1041494	0	0	0
T179	157246	2798	0	0
T182	0	2795	0	0
T234	1988524	0	0	0
T310	0	2793	0	0
T312	174090	0	0	0
T313	154748	0	0	0
T314	268096	0	0	0
T315	373764	0	0	0
T316	511942	0	0	0
T317	381014	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T179,T182,T310
0	1	Covered	T179,T182,T310
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T179,T182,T310
1	Covered	T179,T182,T310

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T179,T182,T310
1	Covered	T179,T182,T310

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T179,T182,T310
1	1	Covered	T179,T182,T310

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T179,T182,T310
1	0	Covered	T179,T182,T310
1	1	Covered	T179,T182,T310

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T179,T182,T310

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T179,T182,T310
0	Covered	T179,T182,T310

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T179,T182,T310
0	Covered	T179,T182,T310

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	522076652	512814440	0	0
CheckNGreaterZero_A	1028	1028	0	0
GntImpliesReady_A	522076652	5197	0	0
GntImpliesValid_A	522076652	5197	0	0
GrantKnown_A	522076652	512814440	0	0
IdxKnown_A	522076652	512814440	0	0
IndexIsCorrect_A	522076652	5197	0	0
NoReadyValidNoGrant_A	522076652	0	0	0
Priority_A	522076652	5197	0	0
ReadyAndValidImplyGrant_A	522076652	5197	0	0
ReqAndReadyImplyGrant_A	522076652	5197	0	0
ReqImpliesValid_A	522076652	5197	0	0
ValidKnown_A	522076652	512814440	0	0
gen_data_port_assertion.DataFlow_A	522076652	5197	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522076652	512814440	0	0
T1	422903	422845	0	0
T2	128237	128131	0	0
T3	278856	278736	0	0
T4	757334	757323	0	0
T5	654157	654102	0	0
T6	249735	249518	0	0
T7	55998	55881	0	0
T8	155511	155499	0	0
T80	208016	207900	0	0
T81	162624	162569	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522076652	5197	0	0
T112	215558	0	0	0
T153	520747	0	0	0
T179	78623	1734	0	0
T182	0	1733	0	0
T234	994262	0	0	0
T310	0	1730	0	0
T312	87045	0	0	0
T313	77374	0	0	0
T314	134048	0	0	0
T315	186882	0	0	0
T316	255971	0	0	0
T317	190507	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522076652	5197	0	0
T112	215558	0	0	0
T153	520747	0	0	0
T179	78623	1734	0	0
T182	0	1733	0	0
T234	994262	0	0	0
T310	0	1730	0	0
T312	87045	0	0	0
T313	77374	0	0	0
T314	134048	0	0	0
T315	186882	0	0	0
T316	255971	0	0	0
T317	190507	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522076652	512814440	0	0
T1	422903	422845	0	0
T2	128237	128131	0	0
T3	278856	278736	0	0
T4	757334	757323	0	0
T5	654157	654102	0	0
T6	249735	249518	0	0
T7	55998	55881	0	0
T8	155511	155499	0	0
T80	208016	207900	0	0
T81	162624	162569	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522076652	512814440	0	0
T1	422903	422845	0	0
T2	128237	128131	0	0
T3	278856	278736	0	0
T4	757334	757323	0	0
T5	654157	654102	0	0
T6	249735	249518	0	0
T7	55998	55881	0	0
T8	155511	155499	0	0
T80	208016	207900	0	0
T81	162624	162569	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522076652	5197	0	0
T112	215558	0	0	0
T153	520747	0	0	0
T179	78623	1734	0	0
T182	0	1733	0	0
T234	994262	0	0	0
T310	0	1730	0	0
T312	87045	0	0	0
T313	77374	0	0	0
T314	134048	0	0	0
T315	186882	0	0	0
T316	255971	0	0	0
T317	190507	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522076652	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522076652	5197	0	0
T112	215558	0	0	0
T153	520747	0	0	0
T179	78623	1734	0	0
T182	0	1733	0	0
T234	994262	0	0	0
T310	0	1730	0	0
T312	87045	0	0	0
T313	77374	0	0	0
T314	134048	0	0	0
T315	186882	0	0	0
T316	255971	0	0	0
T317	190507	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522076652	5197	0	0
T112	215558	0	0	0
T153	520747	0	0	0
T179	78623	1734	0	0
T182	0	1733	0	0
T234	994262	0	0	0
T310	0	1730	0	0
T312	87045	0	0	0
T313	77374	0	0	0
T314	134048	0	0	0
T315	186882	0	0	0
T316	255971	0	0	0
T317	190507	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522076652	5197	0	0
T112	215558	0	0	0
T153	520747	0	0	0
T179	78623	1734	0	0
T182	0	1733	0	0
T234	994262	0	0	0
T310	0	1730	0	0
T312	87045	0	0	0
T313	77374	0	0	0
T314	134048	0	0	0
T315	186882	0	0	0
T316	255971	0	0	0
T317	190507	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522076652	5197	0	0
T112	215558	0	0	0
T153	520747	0	0	0
T179	78623	1734	0	0
T182	0	1733	0	0
T234	994262	0	0	0
T310	0	1730	0	0
T312	87045	0	0	0
T313	77374	0	0	0
T314	134048	0	0	0
T315	186882	0	0	0
T316	255971	0	0	0
T317	190507	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522076652	512814440	0	0
T1	422903	422845	0	0
T2	128237	128131	0	0
T3	278856	278736	0	0
T4	757334	757323	0	0
T5	654157	654102	0	0
T6	249735	249518	0	0
T7	55998	55881	0	0
T8	155511	155499	0	0
T80	208016	207900	0	0
T81	162624	162569	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522076652	5197	0	0
T112	215558	0	0	0
T153	520747	0	0	0
T179	78623	1734	0	0
T182	0	1733	0	0
T234	994262	0	0	0
T310	0	1730	0	0
T312	87045	0	0	0
T313	77374	0	0	0
T314	134048	0	0	0
T315	186882	0	0	0
T316	255971	0	0	0
T317	190507	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T179,T182,T310
0	1	Covered	T179,T182,T310
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T179,T182,T310
1	Covered	T179,T182,T310

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T179,T182,T310
1	Covered	T179,T182,T310

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T179,T182,T310
1	1	Covered	T179,T182,T310

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T179,T182,T310
1	0	Covered	T179,T182,T310
1	1	Covered	T179,T182,T310

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T179,T182,T310

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T179,T182,T310
0	Covered	T179,T182,T310

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T179,T182,T310
0	Covered	T179,T182,T310

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	522076652	512814440	0	0
CheckNGreaterZero_A	1028	1028	0	0
GntImpliesReady_A	522076652	3189	0	0
GntImpliesValid_A	522076652	3189	0	0
GrantKnown_A	522076652	512814440	0	0
IdxKnown_A	522076652	512814440	0	0
IndexIsCorrect_A	522076652	3189	0	0
NoReadyValidNoGrant_A	522076652	0	0	0
Priority_A	522076652	3189	0	0
ReadyAndValidImplyGrant_A	522076652	3189	0	0
ReqAndReadyImplyGrant_A	522076652	3189	0	0
ReqImpliesValid_A	522076652	3189	0	0
ValidKnown_A	522076652	512814440	0	0
gen_data_port_assertion.DataFlow_A	522076652	3189	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522076652	512814440	0	0
T1	422903	422845	0	0
T2	128237	128131	0	0
T3	278856	278736	0	0
T4	757334	757323	0	0
T5	654157	654102	0	0
T6	249735	249518	0	0
T7	55998	55881	0	0
T8	155511	155499	0	0
T80	208016	207900	0	0
T81	162624	162569	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522076652	3189	0	0
T112	215558	0	0	0
T153	520747	0	0	0
T179	78623	1064	0	0
T182	0	1062	0	0
T234	994262	0	0	0
T310	0	1063	0	0
T312	87045	0	0	0
T313	77374	0	0	0
T314	134048	0	0	0
T315	186882	0	0	0
T316	255971	0	0	0
T317	190507	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522076652	3189	0	0
T112	215558	0	0	0
T153	520747	0	0	0
T179	78623	1064	0	0
T182	0	1062	0	0
T234	994262	0	0	0
T310	0	1063	0	0
T312	87045	0	0	0
T313	77374	0	0	0
T314	134048	0	0	0
T315	186882	0	0	0
T316	255971	0	0	0
T317	190507	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522076652	512814440	0	0
T1	422903	422845	0	0
T2	128237	128131	0	0
T3	278856	278736	0	0
T4	757334	757323	0	0
T5	654157	654102	0	0
T6	249735	249518	0	0
T7	55998	55881	0	0
T8	155511	155499	0	0
T80	208016	207900	0	0
T81	162624	162569	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522076652	512814440	0	0
T1	422903	422845	0	0
T2	128237	128131	0	0
T3	278856	278736	0	0
T4	757334	757323	0	0
T5	654157	654102	0	0
T6	249735	249518	0	0
T7	55998	55881	0	0
T8	155511	155499	0	0
T80	208016	207900	0	0
T81	162624	162569	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522076652	3189	0	0
T112	215558	0	0	0
T153	520747	0	0	0
T179	78623	1064	0	0
T182	0	1062	0	0
T234	994262	0	0	0
T310	0	1063	0	0
T312	87045	0	0	0
T313	77374	0	0	0
T314	134048	0	0	0
T315	186882	0	0	0
T316	255971	0	0	0
T317	190507	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522076652	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522076652	3189	0	0
T112	215558	0	0	0
T153	520747	0	0	0
T179	78623	1064	0	0
T182	0	1062	0	0
T234	994262	0	0	0
T310	0	1063	0	0
T312	87045	0	0	0
T313	77374	0	0	0
T314	134048	0	0	0
T315	186882	0	0	0
T316	255971	0	0	0
T317	190507	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522076652	3189	0	0
T112	215558	0	0	0
T153	520747	0	0	0
T179	78623	1064	0	0
T182	0	1062	0	0
T234	994262	0	0	0
T310	0	1063	0	0
T312	87045	0	0	0
T313	77374	0	0	0
T314	134048	0	0	0
T315	186882	0	0	0
T316	255971	0	0	0
T317	190507	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522076652	3189	0	0
T112	215558	0	0	0
T153	520747	0	0	0
T179	78623	1064	0	0
T182	0	1062	0	0
T234	994262	0	0	0
T310	0	1063	0	0
T312	87045	0	0	0
T313	77374	0	0	0
T314	134048	0	0	0
T315	186882	0	0	0
T316	255971	0	0	0
T317	190507	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522076652	3189	0	0
T112	215558	0	0	0
T153	520747	0	0	0
T179	78623	1064	0	0
T182	0	1062	0	0
T234	994262	0	0	0
T310	0	1063	0	0
T312	87045	0	0	0
T313	77374	0	0	0
T314	134048	0	0	0
T315	186882	0	0	0
T316	255971	0	0	0
T317	190507	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522076652	512814440	0	0
T1	422903	422845	0	0
T2	128237	128131	0	0
T3	278856	278736	0	0
T4	757334	757323	0	0
T5	654157	654102	0	0
T6	249735	249518	0	0
T7	55998	55881	0	0
T8	155511	155499	0	0
T80	208016	207900	0	0
T81	162624	162569	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	522076652	3189	0	0
T112	215558	0	0	0
T153	520747	0	0	0
T179	78623	1064	0	0
T182	0	1062	0	0
T234	994262	0	0	0
T310	0	1063	0	0
T312	87045	0	0	0
T313	77374	0	0	0
T314	134048	0	0	0
T315	186882	0	0	0
T316	255971	0	0	0
T317	190507	0	0	0