Unified Coverage Report :: Module :: prim_mubi4_sync

Module : prim_mubi4_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync	100.00						100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.41	99.34	100.00			98.31	100.00	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : prim_mubi4_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1028	1028	0	0
OutputsKnown_A	130234427	129536914	0	0
gen_no_flops.OutputDelay_A	130234427	129536914	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130234427	129536914	0	0
T1	102537	101870	0	0
T2	31956	31526	0	0
T3	67975	67664	0	0
T4	181995	181845	0	0
T5	157699	157375	0	0
T6	62754	62187	0	0
T7	16159	14620	0	0
T8	374253	373608	0	0
T80	51255	50673	0	0
T81	40400	39400	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130234427	129536914	0	0
T1	102537	101870	0	0
T2	31956	31526	0	0
T3	67975	67664	0	0
T4	181995	181845	0	0
T5	157699	157375	0	0
T6	62754	62187	0	0
T7	16159	14620	0	0
T8	374253	373608	0	0
T80	51255	50673	0	0
T81	40400	39400	0	0

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1028	1028	0	0
OutputsKnown_A	130234427	129536914	0	0
gen_no_flops.OutputDelay_A	130234427	129536914	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T80	1	1	0	0
T81	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130234427	129536914	0	0
T1	102537	101870	0	0
T2	31956	31526	0	0
T3	67975	67664	0	0
T4	181995	181845	0	0
T5	157699	157375	0	0
T6	62754	62187	0	0
T7	16159	14620	0	0
T8	374253	373608	0	0
T80	51255	50673	0	0
T81	40400	39400	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	130234427	129536914	0	0
T1	102537	101870	0	0
T2	31956	31526	0	0
T3	67975	67664	0	0
T4	181995	181845	0	0
T5	157699	157375	0	0
T6	62754	62187	0	0
T7	16159	14620	0	0
T8	374253	373608	0	0
T80	51255	50673	0	0
T81	40400	39400	0	0