| SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
| NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_max_outstanding_cg | 100.00 | 1 | 100 | 1 | 64 | 64 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 3 | 0 | 3 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_num_of_outstanding | 3 | 0 | 3 | 100.00 | 100 | 1 | 1 | 0 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 3 | 0 | 3 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| values[1] | 40061313 | 1 | T1 | 3703 | T2 | 10031 | T3 | 32265 | ||||
| values[2] | 1162428 | 1 | T380 | 5369 | T379 | 4385 | T531 | 2860 | ||||
| values[3] | 39445 | 1 | T380 | 19 | T531 | 3 | T160 | 279 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |