Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2079445	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

39018317

1

T1

3605

T2

9651

T3

30858

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	28567381	1			T1	897		T2	3683		T3	22025
values[0x0]	10975252	1			T1	2708		T2	5968		T3	8833
values[0x1]	1555129	1			T1	98		T2	380		T3	1407

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	656209	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

40441553

1

T1

3703

T2

10031

T3

32265

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	19353693	1			T1	1852		T2	5016		T3	16133
valid_sources[0x01]	19352072	1			T1	1851		T2	5015		T3	16132
valid_sources[0x02]	38730	1			T78	1		T380	238		T379	216
valid_sources[0x03]	38377	1			T380	265		T379	152		T531	28
valid_sources[0x04]	38678	1			T78	2		T380	239		T379	201
valid_sources[0x05]	38303	1			T380	256		T379	111		T531	21
valid_sources[0x06]	38896	1			T82	4		T380	266		T379	142
valid_sources[0x07]	38323	1			T82	3		T211	7		T380	246
valid_sources[0x08]	40270	1			T82	1		T380	236		T379	184
valid_sources[0x09]	38745	1			T380	269		T379	190		T531	21
valid_sources[0x0a]	38929	1			T78	1		T380	275		T379	143
valid_sources[0x0b]	37674	1			T78	1		T380	224		T379	148
valid_sources[0x0c]	40477	1			T82	1		T211	1		T380	226
valid_sources[0x0d]	38432	1			T380	237		T379	141		T531	22
valid_sources[0x0e]	39003	1			T78	5		T211	1		T380	251
valid_sources[0x0f]	38023	1			T82	3		T380	232		T379	112
valid_sources[0x10]	39451	1			T78	4		T380	246		T379	110
valid_sources[0x11]	38169	1			T380	272		T379	198		T531	21
valid_sources[0x12]	37965	1			T380	246		T379	159		T531	14
valid_sources[0x13]	38463	1			T82	4		T380	273		T379	117
valid_sources[0x14]	38046	1			T78	1		T380	249		T379	139
valid_sources[0x15]	38032	1			T380	249		T379	206		T531	18
valid_sources[0x16]	38802	1			T78	2		T211	1		T380	253
valid_sources[0x17]	38387	1			T380	231		T379	209		T531	18
valid_sources[0x18]	38712	1			T82	1		T380	279		T379	218
valid_sources[0x19]	39044	1			T211	4		T380	255		T379	185
valid_sources[0x1a]	38611	1			T380	223		T379	164		T531	19
valid_sources[0x1b]	38855	1			T380	244		T379	195		T531	26
valid_sources[0x1c]	37854	1			T78	1		T51	39		T380	256
valid_sources[0x1d]	37794	1			T82	3		T380	239		T379	109
valid_sources[0x1e]	38980	1			T78	2		T380	244		T379	178
valid_sources[0x1f]	38318	1			T82	5		T380	248		T379	182
valid_sources[0x20]	38693	1			T78	1		T380	242		T379	126

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27836392

1

T1

897

T2

3683

T3

22025

values[0x0]

all_enables

biggest_size

10918555

1

T1

2708

T2

5968

T3

8833

values[0x1]

all_enables

biggest_size

263370

1

T21

20

T82

19

T83

19

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2866143	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

452644

1

T79

662

T80

267

T81

166

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1123479	1			T79	1466		T80	652		T81	385
values[0x0]	1071394	1			T79	1560		T80	607		T81	370
values[0x1]	1123914	1			T79	1395		T80	635		T81	378

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2219919	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1098868

1

T79

1459

T80

614

T81

383

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51612	1			T79	68		T80	29		T81	13
valid_sources[0x01]	51262	1			T79	77		T80	29		T81	17
valid_sources[0x02]	51418	1			T79	72		T80	31		T81	10
valid_sources[0x03]	52426	1			T79	77		T80	20		T81	13
valid_sources[0x04]	52130	1			T79	60		T80	28		T81	15
valid_sources[0x05]	52277	1			T79	80		T80	38		T81	22
valid_sources[0x06]	52916	1			T79	56		T80	27		T81	14
valid_sources[0x07]	51676	1			T79	67		T80	30		T81	9
valid_sources[0x08]	51509	1			T79	68		T80	28		T81	21
valid_sources[0x09]	51782	1			T79	84		T80	22		T81	15
valid_sources[0x0a]	52266	1			T79	63		T80	34		T81	23
valid_sources[0x0b]	52710	1			T79	71		T80	27		T81	20
valid_sources[0x0c]	52084	1			T79	68		T80	27		T81	14
valid_sources[0x0d]	52408	1			T79	66		T80	30		T81	20
valid_sources[0x0e]	52193	1			T79	76		T80	30		T81	17
valid_sources[0x0f]	51951	1			T79	69		T80	31		T81	18
valid_sources[0x10]	51632	1			T79	69		T80	32		T81	20
valid_sources[0x11]	52747	1			T79	65		T80	30		T81	11
valid_sources[0x12]	51728	1			T79	60		T80	30		T81	17
valid_sources[0x13]	51948	1			T79	76		T80	33		T81	20
valid_sources[0x14]	52645	1			T79	80		T80	35		T81	17
valid_sources[0x15]	52183	1			T79	66		T80	23		T81	23
valid_sources[0x16]	51875	1			T79	63		T80	34		T81	10
valid_sources[0x17]	50858	1			T79	70		T80	20		T81	20
valid_sources[0x18]	51625	1			T79	74		T80	25		T81	15
valid_sources[0x19]	51392	1			T79	59		T80	33		T81	13
valid_sources[0x1a]	51466	1			T79	70		T80	35		T81	13
valid_sources[0x1b]	51560	1			T79	78		T80	38		T81	15
valid_sources[0x1c]	52024	1			T79	66		T80	31		T81	16
valid_sources[0x1d]	50427	1			T79	66		T80	27		T81	13
valid_sources[0x1e]	52340	1			T79	61		T80	26		T81	24
valid_sources[0x1f]	51117	1			T79	79		T80	32		T81	24
valid_sources[0x20]	52702	1			T79	73		T80	20		T81	25

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47387

1

T79

60

T80

28

T81

16

values[0x0]

all_enables

biggest_size

357748

1

T79

541

T80

209

T81

132

values[0x1]

all_enables

biggest_size

47509

1

T79

61

T80

30

T81

18

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3061104	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

498154

1

T79

571

T80

275

T81

192

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1218545	1			T79	1410		T80	623		T81	404
values[0x0]	1121803	1			T79	1334		T80	637		T81	434
values[0x1]	1218910	1			T79	1403		T80	627		T81	437

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2348694	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1210564

1

T79

1383

T80

651

T81

439

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	55268	1			T79	69		T80	32		T81	30
valid_sources[0x01]	54915	1			T79	51		T80	23		T81	21
valid_sources[0x02]	55897	1			T79	69		T80	26		T81	15
valid_sources[0x03]	56402	1			T79	72		T80	30		T81	27
valid_sources[0x04]	54858	1			T79	92		T80	35		T81	30
valid_sources[0x05]	56344	1			T79	56		T80	32		T81	27
valid_sources[0x06]	55658	1			T79	52		T80	26		T81	22
valid_sources[0x07]	56143	1			T79	83		T80	31		T81	22
valid_sources[0x08]	54488	1			T79	62		T80	25		T81	20
valid_sources[0x09]	55156	1			T79	70		T80	25		T81	16
valid_sources[0x0a]	55553	1			T79	73		T80	34		T81	16
valid_sources[0x0b]	55664	1			T79	38		T80	29		T81	20
valid_sources[0x0c]	55245	1			T79	76		T80	27		T81	22
valid_sources[0x0d]	55617	1			T79	71		T80	19		T81	17
valid_sources[0x0e]	56475	1			T79	64		T80	25		T81	17
valid_sources[0x0f]	56458	1			T79	54		T80	24		T81	11
valid_sources[0x10]	55395	1			T79	66		T80	35		T81	20
valid_sources[0x11]	56655	1			T79	56		T80	38		T81	28
valid_sources[0x12]	55113	1			T79	54		T80	27		T81	19
valid_sources[0x13]	56434	1			T79	70		T80	23		T81	18
valid_sources[0x14]	55575	1			T79	67		T80	30		T81	16
valid_sources[0x15]	56072	1			T79	55		T80	32		T81	14
valid_sources[0x16]	54997	1			T79	84		T80	31		T81	29
valid_sources[0x17]	56044	1			T79	86		T80	27		T81	16
valid_sources[0x18]	55911	1			T79	66		T80	36		T81	25
valid_sources[0x19]	55029	1			T79	84		T80	29		T81	14
valid_sources[0x1a]	55598	1			T79	52		T80	34		T81	18
valid_sources[0x1b]	56081	1			T79	73		T80	23		T81	28
valid_sources[0x1c]	56257	1			T79	55		T80	26		T81	18
valid_sources[0x1d]	55124	1			T79	44		T80	29		T81	22
valid_sources[0x1e]	55591	1			T79	68		T80	30		T81	19
valid_sources[0x1f]	55183	1			T79	70		T80	31		T81	22
valid_sources[0x20]	56533	1			T79	71		T80	31		T81	22

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

52395

1

T79

56

T80

26

T81

11

values[0x0]

all_enables

biggest_size

393537

1

T79

458

T80

211

T81

163

values[0x1]

all_enables

biggest_size

52222

1

T79

57

T80

38

T81

18

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2888925	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

455850

1

T79

591

T80

275

T81

162

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1131039	1			T79	1533		T80	663		T81	413
values[0x0]	1081105	1			T79	1433		T80	636		T81	391
values[0x1]	1132631	1			T79	1461		T80	659		T81	405

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2236861	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1107914

1

T79

1495

T80

674

T81

377

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51124	1			T79	67		T80	26		T81	15
valid_sources[0x01]	51655	1			T79	70		T80	33		T81	9
valid_sources[0x02]	52915	1			T79	73		T80	31		T81	29
valid_sources[0x03]	52272	1			T79	55		T80	26		T81	17
valid_sources[0x04]	51476	1			T79	71		T80	33		T81	28
valid_sources[0x05]	53147	1			T79	68		T80	34		T81	8
valid_sources[0x06]	53339	1			T79	77		T80	25		T81	15
valid_sources[0x07]	52610	1			T79	73		T80	22		T81	17
valid_sources[0x08]	52260	1			T79	81		T80	33		T81	10
valid_sources[0x09]	51768	1			T79	80		T80	33		T81	7
valid_sources[0x0a]	52709	1			T79	66		T80	29		T81	11
valid_sources[0x0b]	51884	1			T79	67		T80	31		T81	34
valid_sources[0x0c]	52814	1			T79	84		T80	29		T81	19
valid_sources[0x0d]	51805	1			T79	77		T80	36		T81	33
valid_sources[0x0e]	52180	1			T79	67		T80	30		T81	29
valid_sources[0x0f]	53056	1			T79	69		T80	26		T81	11
valid_sources[0x10]	51726	1			T79	68		T80	35		T81	6
valid_sources[0x11]	52042	1			T79	65		T80	35		T81	5
valid_sources[0x12]	51891	1			T79	63		T80	35		T81	12
valid_sources[0x13]	52768	1			T79	77		T80	33		T81	33
valid_sources[0x14]	53459	1			T79	71		T80	34		T81	20
valid_sources[0x15]	52469	1			T79	63		T80	25		T81	25
valid_sources[0x16]	52468	1			T79	56		T80	32		T81	25
valid_sources[0x17]	51924	1			T79	71		T80	28		T81	17
valid_sources[0x18]	52110	1			T79	71		T80	30		T81	28
valid_sources[0x19]	52048	1			T79	68		T80	32		T81	17
valid_sources[0x1a]	52156	1			T79	62		T80	22		T81	25
valid_sources[0x1b]	52199	1			T79	58		T80	33		T81	24
valid_sources[0x1c]	52836	1			T79	59		T80	32		T81	6
valid_sources[0x1d]	51442	1			T79	70		T80	27		T81	8
valid_sources[0x1e]	51851	1			T79	69		T80	33		T81	26
valid_sources[0x1f]	52137	1			T79	71		T80	27		T81	24
valid_sources[0x20]	52235	1			T79	81		T80	37		T81	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47663

1

T79

60

T80

18

T81

13

values[0x0]

all_enables

biggest_size

360475

1

T79

467

T80

235

T81

126

values[0x1]

all_enables

biggest_size

47712

1

T79

64

T80

22

T81

23