Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	535937332	63111787	0	0
DepthKnown_A	535937332	535829014	0	0
RvalidKnown_A	535937332	535829014	0	0
WreadyKnown_A	535937332	535829014	0	0
gen_passthru_fifo.paramCheckPass	1028	1028	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535937332	63111787	0	0
T1	93803	7919	0	0
T2	164664	19031	0	0
T3	330059	42741	0	0
T4	319574	31165	0	0
T5	202673	39195	0	0
T6	157451	23311	0	0
T47	148752	161388	0	0
T87	101573	7505	0	0
T93	59163	5453	0	0
T94	183189	24921	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535937332	535829014	0	0
T1	93803	93745	0	0
T2	164664	164562	0	0
T3	330059	330001	0	0
T4	319574	319364	0	0
T5	202673	202611	0	0
T6	157451	157331	0	0
T47	148752	148746	0	0
T87	101573	101515	0	0
T93	59163	59105	0	0
T94	183189	183134	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535937332	535829014	0	0
T1	93803	93745	0	0
T2	164664	164562	0	0
T3	330059	330001	0	0
T4	319574	319364	0	0
T5	202673	202611	0	0
T6	157451	157331	0	0
T47	148752	148746	0	0
T87	101573	101515	0	0
T93	59163	59105	0	0
T94	183189	183134	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535937332	535829014	0	0
T1	93803	93745	0	0
T2	164664	164562	0	0
T3	330059	330001	0	0
T4	319574	319364	0	0
T5	202673	202611	0	0
T6	157451	157331	0	0
T47	148752	148746	0	0
T87	101573	101515	0	0
T93	59163	59105	0	0
T94	183189	183134	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T47	1	1	0	0
T87	1	1	0	0
T93	1	1	0	0
T94	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	535937332	48644706	0	0
DepthKnown_A	535937332	535829014	0	0
RvalidKnown_A	535937332	535829014	0	0
WreadyKnown_A	535937332	535829014	0	0
gen_passthru_fifo.paramCheckPass	1028	1028	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535937332	48644706	0	0
T1	93803	5433	0	0
T2	164664	14046	0	0
T3	330059	37834	0	0
T4	319574	25182	0	0
T5	202673	28910	0	0
T6	157451	14921	0	0
T47	148752	141436	0	0
T87	101573	5344	0	0
T93	59163	3788	0	0
T94	183189	19304	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535937332	535829014	0	0
T1	93803	93745	0	0
T2	164664	164562	0	0
T3	330059	330001	0	0
T4	319574	319364	0	0
T5	202673	202611	0	0
T6	157451	157331	0	0
T47	148752	148746	0	0
T87	101573	101515	0	0
T93	59163	59105	0	0
T94	183189	183134	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535937332	535829014	0	0
T1	93803	93745	0	0
T2	164664	164562	0	0
T3	330059	330001	0	0
T4	319574	319364	0	0
T5	202673	202611	0	0
T6	157451	157331	0	0
T47	148752	148746	0	0
T87	101573	101515	0	0
T93	59163	59105	0	0
T94	183189	183134	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535937332	535829014	0	0
T1	93803	93745	0	0
T2	164664	164562	0	0
T3	330059	330001	0	0
T4	319574	319364	0	0
T5	202673	202611	0	0
T6	157451	157331	0	0
T47	148752	148746	0	0
T87	101573	101515	0	0
T93	59163	59105	0	0
T94	183189	183134	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T47	1	1	0	0
T87	1	1	0	0
T93	1	1	0	0
T94	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	535937332	45828827	0	0
DepthKnown_A	535937332	535829014	0	0
RvalidKnown_A	535937332	535829014	0	0
WreadyKnown_A	535937332	535829014	0	0
gen_passthru_fifo.paramCheckPass	1028	1028	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535937332	45828827	0	0
T1	93803	3855	0	0
T2	164664	10380	0	0
T3	330059	33015	0	0
T4	319574	14082	0	0
T5	202673	22901	0	0
T6	157451	11663	0	0
T47	148752	194925	0	0
T87	101573	4951	0	0
T93	59163	3121	0	0
T94	183189	13451	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535937332	535829014	0	0
T1	93803	93745	0	0
T2	164664	164562	0	0
T3	330059	330001	0	0
T4	319574	319364	0	0
T5	202673	202611	0	0
T6	157451	157331	0	0
T47	148752	148746	0	0
T87	101573	101515	0	0
T93	59163	59105	0	0
T94	183189	183134	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535937332	535829014	0	0
T1	93803	93745	0	0
T2	164664	164562	0	0
T3	330059	330001	0	0
T4	319574	319364	0	0
T5	202673	202611	0	0
T6	157451	157331	0	0
T47	148752	148746	0	0
T87	101573	101515	0	0
T93	59163	59105	0	0
T94	183189	183134	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535937332	535829014	0	0
T1	93803	93745	0	0
T2	164664	164562	0	0
T3	330059	330001	0	0
T4	319574	319364	0	0
T5	202673	202611	0	0
T6	157451	157331	0	0
T47	148752	148746	0	0
T87	101573	101515	0	0
T93	59163	59105	0	0
T94	183189	183134	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T47	1	1	0	0
T87	1	1	0	0
T93	1	1	0	0
T94	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	535937332	38692904	0	0
DepthKnown_A	535937332	535829014	0	0
RvalidKnown_A	535937332	535829014	0	0
WreadyKnown_A	535937332	535829014	0	0
gen_passthru_fifo.paramCheckPass	1028	1028	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535937332	38692904	0	0
T1	93803	3703	0	0
T2	164664	10031	0	0
T3	330059	32265	0	0
T4	319574	13703	0	0
T5	202673	22356	0	0
T6	157451	11148	0	0
T47	148752	147260	0	0
T87	101573	4755	0	0
T93	59163	3007	0	0
T94	183189	13197	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535937332	535829014	0	0
T1	93803	93745	0	0
T2	164664	164562	0	0
T3	330059	330001	0	0
T4	319574	319364	0	0
T5	202673	202611	0	0
T6	157451	157331	0	0
T47	148752	148746	0	0
T87	101573	101515	0	0
T93	59163	59105	0	0
T94	183189	183134	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535937332	535829014	0	0
T1	93803	93745	0	0
T2	164664	164562	0	0
T3	330059	330001	0	0
T4	319574	319364	0	0
T5	202673	202611	0	0
T6	157451	157331	0	0
T47	148752	148746	0	0
T87	101573	101515	0	0
T93	59163	59105	0	0
T94	183189	183134	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	535937332	535829014	0	0
T1	93803	93745	0	0
T2	164664	164562	0	0
T3	330059	330001	0	0
T4	319574	319364	0	0
T5	202673	202611	0	0
T6	157451	157331	0	0
T47	148752	148746	0	0
T87	101573	101515	0	0
T93	59163	59105	0	0
T94	183189	183134	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1028	1028	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T47	1	1	0	0
T87	1	1	0	0
T93	1	1	0	0
T94	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	618735938	93361	0	0
DepthKnown_A	618735938	618611893	0	0
RvalidKnown_A	618735938	618611893	0	0
WreadyKnown_A	618735938	618611893	0	0
gen_passthru_fifo.paramCheckPass	2936	2936	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618735938	93361	0	0
T1	93803	21	0	0
T2	164664	74	0	0
T3	330059	740	0	0
T4	319574	44	0	0
T5	202673	15	0	0
T6	157451	34	0	0
T47	148752	41	0	0
T87	101573	13	0	0
T93	59163	13	0	0
T94	183189	115	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618735938	618611893	0	0
T1	93803	93745	0	0
T2	164664	164562	0	0
T3	330059	330001	0	0
T4	319574	319364	0	0
T5	202673	202611	0	0
T6	157451	157331	0	0
T47	148752	148746	0	0
T87	101573	101515	0	0
T93	59163	59105	0	0
T94	183189	183134	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618735938	618611893	0	0
T1	93803	93745	0	0
T2	164664	164562	0	0
T3	330059	330001	0	0
T4	319574	319364	0	0
T5	202673	202611	0	0
T6	157451	157331	0	0
T47	148752	148746	0	0
T87	101573	101515	0	0
T93	59163	59105	0	0
T94	183189	183134	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618735938	618611893	0	0
T1	93803	93745	0	0
T2	164664	164562	0	0
T3	330059	330001	0	0
T4	319574	319364	0	0
T5	202673	202611	0	0
T6	157451	157331	0	0
T47	148752	148746	0	0
T87	101573	101515	0	0
T93	59163	59105	0	0
T94	183189	183134	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2936	2936	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T47	1	1	0	0
T87	1	1	0	0
T93	1	1	0	0
T94	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	618735938	96215	0	0
DepthKnown_A	618735938	618611893	0	0
RvalidKnown_A	618735938	618611893	0	0
WreadyKnown_A	618735938	618611893	0	0
gen_passthru_fifo.paramCheckPass	2936	2936	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618735938	96215	0	0
T1	93803	21	0	0
T2	164664	74	0	0
T3	330059	740	0	0
T4	319574	44	0	0
T5	202673	15	0	0
T6	157451	34	0	0
T47	148752	41	0	0
T87	101573	13	0	0
T93	59163	13	0	0
T94	183189	115	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618735938	618611893	0	0
T1	93803	93745	0	0
T2	164664	164562	0	0
T3	330059	330001	0	0
T4	319574	319364	0	0
T5	202673	202611	0	0
T6	157451	157331	0	0
T47	148752	148746	0	0
T87	101573	101515	0	0
T93	59163	59105	0	0
T94	183189	183134	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618735938	618611893	0	0
T1	93803	93745	0	0
T2	164664	164562	0	0
T3	330059	330001	0	0
T4	319574	319364	0	0
T5	202673	202611	0	0
T6	157451	157331	0	0
T47	148752	148746	0	0
T87	101573	101515	0	0
T93	59163	59105	0	0
T94	183189	183134	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618735938	618611893	0	0
T1	93803	93745	0	0
T2	164664	164562	0	0
T3	330059	330001	0	0
T4	319574	319364	0	0
T5	202673	202611	0	0
T6	157451	157331	0	0
T47	148752	148746	0	0
T87	101573	101515	0	0
T93	59163	59105	0	0
T94	183189	183134	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2936	2936	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T47	1	1	0	0
T87	1	1	0	0
T93	1	1	0	0
T94	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	618735938	52330	0	0
DepthKnown_A	618735938	618611893	0	0
RvalidKnown_A	618735938	618611893	0	0
WreadyKnown_A	618735938	618611893	0	0
gen_passthru_fifo.paramCheckPass	2936	2936	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618735938	52330	0	0
T1	93803	20	0	0
T2	164664	72	0	0
T3	330059	507	0	0
T4	319574	41	0	0
T5	202673	12	0	0
T6	157451	32	0	0
T47	148752	12	0	0
T87	101573	12	0	0
T93	59163	12	0	0
T94	183189	112	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618735938	618611893	0	0
T1	93803	93745	0	0
T2	164664	164562	0	0
T3	330059	330001	0	0
T4	319574	319364	0	0
T5	202673	202611	0	0
T6	157451	157331	0	0
T47	148752	148746	0	0
T87	101573	101515	0	0
T93	59163	59105	0	0
T94	183189	183134	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618735938	618611893	0	0
T1	93803	93745	0	0
T2	164664	164562	0	0
T3	330059	330001	0	0
T4	319574	319364	0	0
T5	202673	202611	0	0
T6	157451	157331	0	0
T47	148752	148746	0	0
T87	101573	101515	0	0
T93	59163	59105	0	0
T94	183189	183134	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618735938	618611893	0	0
T1	93803	93745	0	0
T2	164664	164562	0	0
T3	330059	330001	0	0
T4	319574	319364	0	0
T5	202673	202611	0	0
T6	157451	157331	0	0
T47	148752	148746	0	0
T87	101573	101515	0	0
T93	59163	59105	0	0
T94	183189	183134	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2936	2936	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T47	1	1	0	0
T87	1	1	0	0
T93	1	1	0	0
T94	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	618735938	52334	0	0
DepthKnown_A	618735938	618611893	0	0
RvalidKnown_A	618735938	618611893	0	0
WreadyKnown_A	618735938	618611893	0	0
gen_passthru_fifo.paramCheckPass	2936	2936	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618735938	52334	0	0
T1	93803	20	0	0
T2	164664	72	0	0
T3	330059	507	0	0
T4	319574	41	0	0
T5	202673	12	0	0
T6	157451	32	0	0
T47	148752	12	0	0
T87	101573	12	0	0
T93	59163	12	0	0
T94	183189	112	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618735938	618611893	0	0
T1	93803	93745	0	0
T2	164664	164562	0	0
T3	330059	330001	0	0
T4	319574	319364	0	0
T5	202673	202611	0	0
T6	157451	157331	0	0
T47	148752	148746	0	0
T87	101573	101515	0	0
T93	59163	59105	0	0
T94	183189	183134	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618735938	618611893	0	0
T1	93803	93745	0	0
T2	164664	164562	0	0
T3	330059	330001	0	0
T4	319574	319364	0	0
T5	202673	202611	0	0
T6	157451	157331	0	0
T47	148752	148746	0	0
T87	101573	101515	0	0
T93	59163	59105	0	0
T94	183189	183134	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618735938	618611893	0	0
T1	93803	93745	0	0
T2	164664	164562	0	0
T3	330059	330001	0	0
T4	319574	319364	0	0
T5	202673	202611	0	0
T6	157451	157331	0	0
T47	148752	148746	0	0
T87	101573	101515	0	0
T93	59163	59105	0	0
T94	183189	183134	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2936	2936	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T47	1	1	0	0
T87	1	1	0	0
T93	1	1	0	0
T94	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	618735938	41031	0	0
DepthKnown_A	618735938	618611893	0	0
RvalidKnown_A	618735938	618611893	0	0
WreadyKnown_A	618735938	618611893	0	0
gen_passthru_fifo.paramCheckPass	2936	2936	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618735938	41031	0	0
T1	93803	1	0	0
T2	164664	2	0	0
T3	330059	233	0	0
T4	319574	3	0	0
T5	202673	3	0	0
T6	157451	2	0	0
T47	148752	29	0	0
T87	101573	1	0	0
T93	59163	1	0	0
T94	183189	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618735938	618611893	0	0
T1	93803	93745	0	0
T2	164664	164562	0	0
T3	330059	330001	0	0
T4	319574	319364	0	0
T5	202673	202611	0	0
T6	157451	157331	0	0
T47	148752	148746	0	0
T87	101573	101515	0	0
T93	59163	59105	0	0
T94	183189	183134	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618735938	618611893	0	0
T1	93803	93745	0	0
T2	164664	164562	0	0
T3	330059	330001	0	0
T4	319574	319364	0	0
T5	202673	202611	0	0
T6	157451	157331	0	0
T47	148752	148746	0	0
T87	101573	101515	0	0
T93	59163	59105	0	0
T94	183189	183134	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618735938	618611893	0	0
T1	93803	93745	0	0
T2	164664	164562	0	0
T3	330059	330001	0	0
T4	319574	319364	0	0
T5	202673	202611	0	0
T6	157451	157331	0	0
T47	148752	148746	0	0
T87	101573	101515	0	0
T93	59163	59105	0	0
T94	183189	183134	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2936	2936	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T47	1	1	0	0
T87	1	1	0	0
T93	1	1	0	0
T94	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	618735938	43881	0	0
DepthKnown_A	618735938	618611893	0	0
RvalidKnown_A	618735938	618611893	0	0
WreadyKnown_A	618735938	618611893	0	0
gen_passthru_fifo.paramCheckPass	2936	2936	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618735938	43881	0	0
T1	93803	1	0	0
T2	164664	2	0	0
T3	330059	233	0	0
T4	319574	3	0	0
T5	202673	3	0	0
T6	157451	2	0	0
T47	148752	29	0	0
T87	101573	1	0	0
T93	59163	1	0	0
T94	183189	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618735938	618611893	0	0
T1	93803	93745	0	0
T2	164664	164562	0	0
T3	330059	330001	0	0
T4	319574	319364	0	0
T5	202673	202611	0	0
T6	157451	157331	0	0
T47	148752	148746	0	0
T87	101573	101515	0	0
T93	59163	59105	0	0
T94	183189	183134	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618735938	618611893	0	0
T1	93803	93745	0	0
T2	164664	164562	0	0
T3	330059	330001	0	0
T4	319574	319364	0	0
T5	202673	202611	0	0
T6	157451	157331	0	0
T47	148752	148746	0	0
T87	101573	101515	0	0
T93	59163	59105	0	0
T94	183189	183134	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	618735938	618611893	0	0
T1	93803	93745	0	0
T2	164664	164562	0	0
T3	330059	330001	0	0
T4	319574	319364	0	0
T5	202673	202611	0	0
T6	157451	157331	0	0
T47	148752	148746	0	0
T87	101573	101515	0	0
T93	59163	59105	0	0
T94	183189	183134	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2936	2936	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T47	1	1	0	0
T87	1	1	0	0
T93	1	1	0	0
T94	1	1	0	0