Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T6,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T47,T48,T49	Yes	T47,T48,T49	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T47,T48,T49	Yes	T47,T48,T49	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T21,*T71,*T72	Yes	T21,T71,T72	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T21,T82,T83	Yes	T21,T82,T83	INPUT
tl_i.a_valid	Yes	Yes	T47,T48,T49	Yes	T47,T48,T49	INPUT
tl_o.a_ready	Yes	Yes	T47,T48,T49	Yes	T47,T48,T49	OUTPUT
tl_o.d_error	Yes	Yes	T79,T80,T81	Yes	T79,T81,T86	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T47,T48,T49	Yes	T47,T48,T49	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T47,T48,T49	Yes	T47,T48,T49	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T47,T48,T49	Yes	T47,T48,T49	OUTPUT
tl_o.d_sink	Yes	Yes	T79,T81,T86	Yes	T79,T81,T86	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T71,*T72,*T78	Yes	T71,T72,T78	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T79,T81,T86	Yes	T79,T80,T81	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T47,*T48,*T49	Yes	T47,T48,T49	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T47,T48,T49	Yes	T47,T48,T49	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T87,T270,T88	Yes	T87,T270,T88	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T87,T270,T88	Yes	T87,T88,T170	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T87,T88,T170	Yes	T87,T270,T88	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T87,T270,T88	Yes	T87,T270,T88	OUTPUT
cio_rx_i	Yes	Yes	T6,T4,T7	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T47,T48,T49	Yes	T47,T48,T49	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T134,T222,T113	Yes	T134,T222,T113	OUTPUT
intr_tx_empty_o	Yes	Yes	T134,T222,T113	Yes	T134,T222,T113	OUTPUT
intr_rx_watermark_o	Yes	Yes	T134,T222,T113	Yes	T134,T222,T113	OUTPUT
intr_tx_done_o	Yes	Yes	T134,T342,T222	Yes	T134,T342,T222	OUTPUT
intr_rx_overflow_o	Yes	Yes	T134,T342,T222	Yes	T134,T342,T222	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T329,T341,T330	Yes	T329,T341,T330	OUTPUT
intr_rx_break_err_o	Yes	Yes	T329,T341,T330	Yes	T329,T341,T330	OUTPUT
intr_rx_timeout_o	Yes	Yes	T329,T341,T330	Yes	T329,T341,T330	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T329,T341,T330	Yes	T329,T341,T330	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T6,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T47,T48,T49	Yes	T47,T48,T49	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T47,T48,T49	Yes	T47,T48,T49	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T21,*T71,*T72	Yes	T21,T71,T72	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T21,T82,T83	Yes	T21,T82,T83	INPUT
tl_i.a_valid	Yes	Yes	T47,T48,T49	Yes	T47,T48,T49	INPUT
tl_o.a_ready	Yes	Yes	T47,T48,T49	Yes	T47,T48,T49	OUTPUT
tl_o.d_error	Yes	Yes	T79,T81,T86	Yes	T81,T86,T84	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T47,T48,T49	Yes	T47,T48,T49	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T47,T48,T49	Yes	T47,T48,T49	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T47,T48,T49	Yes	T47,T48,T49	OUTPUT
tl_o.d_sink	Yes	Yes	T81,T86,T84	Yes	T81,T86,T84	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T71,*T72,*T78	Yes	T71,T72,T78	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T79,T81,T86	Yes	T81,T86,T84	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T47,*T48,*T49	Yes	T47,T48,T49	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T47,T48,T49	Yes	T47,T48,T49	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T87,T88,T717	Yes	T87,T88,T717	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T87,T88,T169	Yes	T87,T88,T169	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T87,T88,T169	Yes	T87,T88,T169	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T87,T88,T717	Yes	T87,T88,T717	OUTPUT
cio_rx_i	Yes	Yes	T6,T4,T7	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T47,T48,T49	Yes	T47,T48,T49	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T226,T78,T311	Yes	T226,T78,T311	OUTPUT
intr_tx_empty_o	Yes	Yes	T226,T78,T338	Yes	T226,T78,T338	OUTPUT
intr_rx_watermark_o	Yes	Yes	T226,T338,T329	Yes	T226,T338,T329	OUTPUT
intr_tx_done_o	Yes	Yes	T342,T226,T338	Yes	T342,T226,T338	OUTPUT
intr_rx_overflow_o	Yes	Yes	T342,T226,T338	Yes	T342,T226,T338	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T329,T341,T330	Yes	T329,T341,T330	OUTPUT
intr_rx_break_err_o	Yes	Yes	T329,T341,T330	Yes	T329,T341,T330	OUTPUT
intr_rx_timeout_o	Yes	Yes	T329,T341,T330	Yes	T329,T341,T330	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T329,T341,T330	Yes	T329,T341,T330	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T6,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T222,T113,T223	Yes	T222,T113,T223	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T222,T113,T223	Yes	T222,T113,T223	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T21,*T71,*T72	Yes	T21,T71,T72	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T21,T82,T83	Yes	T21,T82,T83	INPUT
tl_i.a_valid	Yes	Yes	T222,T113,T223	Yes	T222,T113,T223	INPUT
tl_o.a_ready	Yes	Yes	T222,T113,T223	Yes	T222,T113,T223	OUTPUT
tl_o.d_error	Yes	Yes	T80,T81,T84	Yes	T79,T81,T84	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T222,T113,T223	Yes	T222,T113,T223	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T222,T113,T223	Yes	T222,T113,T223	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T222,T113,T223	Yes	T222,T113,T223	OUTPUT
tl_o.d_sink	Yes	Yes	T81,T84,T85	Yes	T79,T81,T84	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T78,*T79,*T81	Yes	T78,T81,T84	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T81,T84,T85	Yes	T80,T81,T84	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T222,*T113,*T223	Yes	T222,T113,T223	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T222,T113,T223	Yes	T222,T113,T223	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T87,T270,T88	Yes	T87,T270,T88	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T87,T270,T88	Yes	T87,T88,T169	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T87,T88,T169	Yes	T87,T270,T88	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T87,T270,T88	Yes	T87,T270,T88	OUTPUT
cio_rx_i	Yes	Yes	T222,T113,T223	Yes	T222,T113,T223	INPUT
cio_tx_o	Yes	Yes	T222,T113,T223	Yes	T222,T113,T223	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T222,T113,T223	Yes	T222,T113,T223	OUTPUT
intr_tx_empty_o	Yes	Yes	T222,T113,T223	Yes	T222,T113,T223	OUTPUT
intr_rx_watermark_o	Yes	Yes	T222,T113,T223	Yes	T222,T113,T223	OUTPUT
intr_tx_done_o	Yes	Yes	T222,T113,T223	Yes	T222,T113,T223	OUTPUT
intr_rx_overflow_o	Yes	Yes	T222,T113,T223	Yes	T222,T113,T223	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T329,T341,T330	Yes	T329,T341,T330	OUTPUT
intr_rx_break_err_o	Yes	Yes	T329,T341,T330	Yes	T329,T341,T330	OUTPUT
intr_rx_timeout_o	Yes	Yes	T329,T341,T330	Yes	T329,T341,T330	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T329,T341,T330	Yes	T329,T341,T330	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T6,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T134,T135,T78	Yes	T134,T135,T78	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T134,T135,T78	Yes	T134,T135,T78	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T21,*T71,*T72	Yes	T21,T71,T72	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T21,T82,T83	Yes	T21,T82,T83	INPUT
tl_i.a_valid	Yes	Yes	T134,T135,T78	Yes	T134,T135,T78	INPUT
tl_o.a_ready	Yes	Yes	T134,T135,T78	Yes	T134,T135,T78	OUTPUT
tl_o.d_error	Yes	Yes	T79,T81,T86	Yes	T81,T86,T84	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T134,T135,T78	Yes	T134,T135,T78	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T134,T135,T78	Yes	T134,T135,T78	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T134,T135,T78	Yes	T134,T135,T78	OUTPUT
tl_o.d_sink	Yes	Yes	T81,T86,T84	Yes	T81,T84,T85	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T78,*T81,*T84	Yes	T78,T81,T84	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T79,T81,T86	Yes	T81,T86,T84	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T134,*T135,*T78	Yes	T134,T135,T78	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T134,T135,T78	Yes	T134,T135,T78	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T87,T88,T78	Yes	T87,T88,T78	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T87,T88,T169	Yes	T88,T169,T172	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T88,T169,T172	Yes	T87,T88,T169	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T87,T88,T78	Yes	T87,T88,T78	OUTPUT
cio_rx_i	Yes	Yes	T134,T135,T340	Yes	T134,T135,T340	INPUT
cio_tx_o	Yes	Yes	T134,T135,T78	Yes	T134,T135,T78	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T134,T135,T78	Yes	T134,T135,T78	OUTPUT
intr_tx_empty_o	Yes	Yes	T134,T135,T340	Yes	T134,T135,T340	OUTPUT
intr_rx_watermark_o	Yes	Yes	T134,T135,T340	Yes	T134,T135,T340	OUTPUT
intr_tx_done_o	Yes	Yes	T134,T135,T340	Yes	T134,T135,T340	OUTPUT
intr_rx_overflow_o	Yes	Yes	T134,T135,T340	Yes	T134,T135,T340	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T329,T341,T330	Yes	T329,T341,T330	OUTPUT
intr_rx_break_err_o	Yes	Yes	T329,T341,T330	Yes	T329,T341,T330	OUTPUT
intr_rx_timeout_o	Yes	Yes	T329,T341,T330	Yes	T329,T341,T330	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T329,T341,T330	Yes	T329,T341,T330	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T6,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T16,T17,T328	Yes	T16,T17,T328	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T16,T17,T328	Yes	T16,T17,T328	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T79,*T80,*T81	Yes	T79,T80,T81	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T21,*T71,*T72	Yes	T21,T71,T72	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T79,T80,T81	Yes	T79,T80,T81	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T21,T82,T83	Yes	T21,T82,T83	INPUT
tl_i.a_valid	Yes	Yes	T16,T17,T328	Yes	T16,T17,T328	INPUT
tl_o.a_ready	Yes	Yes	T16,T17,T328	Yes	T16,T17,T328	OUTPUT
tl_o.d_error	Yes	Yes	T79,T81,T86	Yes	T79,T81,T84	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T16,T17,T328	Yes	T16,T17,T328	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T16,T17,T328	Yes	T16,T17,T328	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T16,T17,T328	Yes	T16,T17,T328	OUTPUT
tl_o.d_sink	Yes	Yes	T79,T81,T84	Yes	T79,T81,T84	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T78,*T79,*T81	Yes	T78,T79,T80	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T79,T81,T86	Yes	T79,T81,T86	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T16,*T17,*T328	Yes	T16,T17,T328	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T16,T17,T328	Yes	T16,T17,T328	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T87,T88,T170	Yes	T87,T88,T170	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T87,T88,T170	Yes	T87,T88,T170	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T87,T88,T170	Yes	T87,T88,T170	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T87,T88,T170	Yes	T87,T88,T170	OUTPUT
cio_rx_i	Yes	Yes	T16,T17,T328	Yes	T16,T17,T328	INPUT
cio_tx_o	Yes	Yes	T16,T17,T328	Yes	T16,T17,T328	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T16,T17,T328	Yes	T16,T17,T328	OUTPUT
intr_tx_empty_o	Yes	Yes	T16,T17,T328	Yes	T16,T17,T328	OUTPUT
intr_rx_watermark_o	Yes	Yes	T16,T17,T328	Yes	T16,T17,T328	OUTPUT
intr_tx_done_o	Yes	Yes	T16,T17,T328	Yes	T16,T17,T328	OUTPUT
intr_rx_overflow_o	Yes	Yes	T16,T17,T328	Yes	T16,T17,T328	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T329,T341,T330	Yes	T329,T341,T330	OUTPUT
intr_rx_break_err_o	Yes	Yes	T329,T341,T330	Yes	T329,T341,T330	OUTPUT
intr_rx_timeout_o	Yes	Yes	T329,T341,T330	Yes	T329,T341,T330	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T329,T341,T330	Yes	T329,T341,T330	OUTPUT

*Tests covering at least one bit in the range