SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
adc_ctrl_aon_fatal_fault | 100.00 | 1 | 100 | 1 | 64 | 64 |
aes_fatal_fault | 100.00 | 1 | 100 | 1 | 64 | 64 |
aes_recov_ctrl_update_err | 100.00 | 1 | 100 | 1 | 64 | 64 |
aon_timer_aon_fatal_fault | 100.00 | 1 | 100 | 1 | 64 | 64 |
clkmgr_aon_fatal_fault | 100.00 | 1 | 100 | 1 | 64 | 64 |
clkmgr_aon_recov_fault | 100.00 | 1 | 100 | 1 | 64 | 64 |
csrng_fatal_alert | 100.00 | 1 | 100 | 1 | 64 | 64 |
csrng_recov_alert | 100.00 | 1 | 100 | 1 | 64 | 64 |
edn0_fatal_alert | 100.00 | 1 | 100 | 1 | 64 | 64 |
edn0_recov_alert | 100.00 | 1 | 100 | 1 | 64 | 64 |
edn1_fatal_alert | 100.00 | 1 | 100 | 1 | 64 | 64 |
edn1_recov_alert | 100.00 | 1 | 100 | 1 | 64 | 64 |
entropy_src_fatal_alert | 100.00 | 1 | 100 | 1 | 64 | 64 |
entropy_src_recov_alert | 100.00 | 1 | 100 | 1 | 64 | 64 |
flash_ctrl_fatal_err | 100.00 | 1 | 100 | 1 | 64 | 64 |
flash_ctrl_fatal_prim_flash_alert | 100.00 | 1 | 100 | 1 | 64 | 64 |
flash_ctrl_fatal_std_err | 100.00 | 1 | 100 | 1 | 64 | 64 |
flash_ctrl_recov_err | 100.00 | 1 | 100 | 1 | 64 | 64 |
flash_ctrl_recov_prim_flash_alert | 100.00 | 1 | 100 | 1 | 64 | 64 |
gpio_fatal_fault | 100.00 | 1 | 100 | 1 | 64 | 64 |
hmac_fatal_fault | 100.00 | 1 | 100 | 1 | 64 | 64 |
i2c0_fatal_fault | 100.00 | 1 | 100 | 1 | 64 | 64 |
i2c1_fatal_fault | 100.00 | 1 | 100 | 1 | 64 | 64 |
i2c2_fatal_fault | 100.00 | 1 | 100 | 1 | 64 | 64 |
keymgr_fatal_fault_err | 100.00 | 1 | 100 | 1 | 64 | 64 |
keymgr_recov_operation_err | 100.00 | 1 | 100 | 1 | 64 | 64 |
kmac_fatal_fault_err | 100.00 | 1 | 100 | 1 | 64 | 64 |
kmac_recov_operation_err | 100.00 | 1 | 100 | 1 | 64 | 64 |
lc_ctrl_fatal_bus_integ_error | 100.00 | 1 | 100 | 1 | 64 | 64 |
lc_ctrl_fatal_prog_error | 100.00 | 1 | 100 | 1 | 64 | 64 |
lc_ctrl_fatal_state_error | 100.00 | 1 | 100 | 1 | 64 | 64 |
otbn_fatal | 100.00 | 1 | 100 | 1 | 64 | 64 |
otbn_recov | 100.00 | 1 | 100 | 1 | 64 | 64 |
otp_ctrl_fatal_bus_integ_error | 100.00 | 1 | 100 | 1 | 64 | 64 |
otp_ctrl_fatal_check_error | 100.00 | 1 | 100 | 1 | 64 | 64 |
otp_ctrl_fatal_macro_error | 100.00 | 1 | 100 | 1 | 64 | 64 |
otp_ctrl_fatal_prim_otp_alert | 100.00 | 1 | 100 | 1 | 64 | 64 |
otp_ctrl_recov_prim_otp_alert | 100.00 | 1 | 100 | 1 | 64 | 64 |
pattgen_fatal_fault | 100.00 | 1 | 100 | 1 | 64 | 64 |
pinmux_aon_fatal_fault | 100.00 | 1 | 100 | 1 | 64 | 64 |
pwm_aon_fatal_fault | 100.00 | 1 | 100 | 1 | 64 | 64 |
pwrmgr_aon_fatal_fault | 100.00 | 1 | 100 | 1 | 64 | 64 |
rom_ctrl_fatal | 100.00 | 1 | 100 | 1 | 64 | 64 |
rstmgr_aon_fatal_cnsty_fault | 100.00 | 1 | 100 | 1 | 64 | 64 |
rstmgr_aon_fatal_fault | 100.00 | 1 | 100 | 1 | 64 | 64 |
rv_core_ibex_fatal_hw_err | 100.00 | 1 | 100 | 1 | 64 | 64 |
rv_core_ibex_fatal_sw_err | 100.00 | 1 | 100 | 1 | 64 | 64 |
rv_core_ibex_recov_hw_err | 100.00 | 1 | 100 | 1 | 64 | 64 |
rv_core_ibex_recov_sw_err | 100.00 | 1 | 100 | 1 | 64 | 64 |
rv_dm_fatal_fault | 100.00 | 1 | 100 | 1 | 64 | 64 |
rv_plic_fatal_fault | 100.00 | 1 | 100 | 1 | 64 | 64 |
rv_timer_fatal_fault | 100.00 | 1 | 100 | 1 | 64 | 64 |
sensor_ctrl_aon_fatal_alert | 100.00 | 1 | 100 | 1 | 64 | 64 |
sensor_ctrl_aon_recov_alert | 100.00 | 1 | 100 | 1 | 64 | 64 |
spi_device_fatal_fault | 100.00 | 1 | 100 | 1 | 64 | 64 |
spi_host0_fatal_fault | 100.00 | 1 | 100 | 1 | 64 | 64 |
spi_host1_fatal_fault | 100.00 | 1 | 100 | 1 | 64 | 64 |
sram_ctrl_main_fatal_error | 100.00 | 1 | 100 | 1 | 64 | 64 |
sram_ctrl_ret_aon_fatal_error | 100.00 | 1 | 100 | 1 | 64 | 64 |
sysrst_ctrl_aon_fatal_fault | 100.00 | 1 | 100 | 1 | 64 | 64 |
uart0_fatal_fault | 100.00 | 1 | 100 | 1 | 64 | 64 |
uart1_fatal_fault | 100.00 | 1 | 100 | 1 | 64 | 64 |
uart2_fatal_fault | 100.00 | 1 | 100 | 1 | 64 | 64 |
uart3_fatal_fault | 100.00 | 1 | 100 | 1 | 64 | 64 |
usbdev_fatal_fault | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 1 | 0 | 1 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
triggered_cp | 1 | 0 | 1 | 100.00 | 100 | 1 | 1 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 3919 | 1 | T4 | 41 | T52 | 1 | T86 | 56 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 122720 | 1 | T4 | 40 | T35 | 599 | T36 | 605 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 177 | 1 | T4 | 36 | T52 | 1 | T86 | 37 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 3159 | 1 | T4 | 31 | T52 | 1 | T86 | 44 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 3413 | 1 | T4 | 44 | T52 | 1 | T86 | 41 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 826 | 1 | T4 | 41 | T697 | 106 | T52 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 1911 | 1 | T4 | 40 | T52 | 1 | T86 | 46 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 210 | 1 | T4 | 49 | T52 | 1 | T86 | 47 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 3582 | 1 | T4 | 35 | T52 | 1 | T86 | 43 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 200 | 1 | T4 | 35 | T52 | 1 | T86 | 45 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 5200 | 1 | T4 | 41 | T657 | 1080 | T52 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 190 | 1 | T4 | 44 | T52 | 1 | T86 | 40 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 7002 | 1 | T4 | 46 | T52 | 1 | T86 | 52 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 210 | 1 | T4 | 55 | T52 | 1 | T86 | 35 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 8579 | 1 | T4 | 40 | T52 | 1 | T86 | 48 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 7046 | 1 | T4 | 39 | T36 | 1737 | T52 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 3636 | 1 | T4 | 39 | T52 | 1 | T86 | 43 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 424 | 1 | T4 | 58 | T52 | 1 | T86 | 45 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 187 | 1 | T4 | 49 | T52 | 1 | T86 | 39 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 3396 | 1 | T4 | 29 | T693 | 525 | T52 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 206 | 1 | T4 | 47 | T52 | 1 | T86 | 54 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 2085 | 1 | T4 | 43 | T52 | 1 | T86 | 56 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 2360 | 1 | T4 | 39 | T52 | 1 | T86 | 44 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 2053 | 1 | T4 | 41 | T372 | 810 | T52 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 7056 | 1 | T4 | 36 | T227 | 1719 | T52 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 206 | 1 | T4 | 49 | T52 | 1 | T86 | 36 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 122700 | 1 | T4 | 42 | T35 | 599 | T36 | 605 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 216 | 1 | T4 | 44 | T52 | 1 | T86 | 50 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 4116 | 1 | T4 | 37 | T52 | 1 | T86 | 46 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 1911 | 1 | T4 | 38 | T52 | 1 | T86 | 39 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 7558 | 1 | T4 | 56 | T152 | 807 | T306 | 812 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 1396367 | 1 | T4 | 37 | T35 | 599 | T36 | 605 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 209 | 1 | T4 | 48 | T144 | 1 | T52 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 3176 | 1 | T4 | 38 | T154 | 815 | T52 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 55424 | 1 | T4 | 46 | T35 | 284 | T36 | 284 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 1013 | 1 | T4 | 46 | T152 | 807 | T52 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 2594 | 1 | T4 | 45 | T35 | 816 | T155 | 507 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 194 | 1 | T4 | 55 | T52 | 1 | T86 | 35 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 3385 | 1 | T4 | 44 | T324 | 511 | T52 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 3467 | 1 | T4 | 47 | T85 | 818 | T52 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 3416 | 1 | T4 | 56 | T108 | 518 | T52 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 8300 | 1 | T4 | 47 | T263 | 2 | T669 | 499 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 2430 | 1 | T4 | 48 | T407 | 1160 | T52 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 3106 | 1 | T4 | 38 | T52 | 1 | T86 | 34 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 3383 | 1 | T4 | 44 | T694 | 817 | T52 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 37344 | 1 | T4 | 24 | T177 | 264 | T248 | 799 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 6934 | 1 | T4 | 42 | T52 | 1 | T86 | 37 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 148 | 1 | T4 | 26 | T52 | 1 | T86 | 20 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 296 | 1 | T4 | 42 | T49 | 1 | T52 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 1313 | 1 | T4 | 34 | T86 | 51 | T706 | 1114 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 10563 | 1 | T4 | 47 | T5 | 1102 | T52 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 3876 | 1 | T4 | 40 | T52 | 1 | T86 | 42 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 5109 | 1 | T4 | 50 | T52 | 1 | T86 | 38 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 35912 | 1 | T4 | 35 | T6 | 7894 | T20 | 70 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 2050 | 1 | T4 | 41 | T98 | 511 | T52 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 6923 | 1 | T4 | 46 | T52 | 1 | T86 | 31 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 4957 | 1 | T4 | 41 | T52 | 1 | T86 | 43 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 3641 | 1 | T4 | 58 | T52 | 1 | T86 | 42 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 214 | 1 | T4 | 52 | T52 | 1 | T86 | 39 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 4014 | 1 | T4 | 42 | T52 | 1 | T86 | 48 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 4813 | 1 | T4 | 38 | T700 | 811 | T373 | 812 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 2888 | 1 | T4 | 44 | T368 | 816 | T52 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 3688 | 1 | T4 | 47 | T701 | 817 | T52 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 5312 | 1 | T4 | 53 | T52 | 1 | T374 | 808 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 1 | 0 | 1 | 100.00 |
NAME | COUNT | STATUS |
ignore | 0 | Excluded |
[auto[0]] | 0 | Excluded |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[1] | 4153 | 1 | T4 | 39 | T52 | 1 | T86 | 53 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |