Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3792827	1			T78	8966		T79	98		T80	125
values[2]	768874	1			T78	1781		T79	62		T80	38
values[3]	107486	1			T78	124		T80	31		T84	813
values[4]	55403	1			T78	4		T80	2		T84	474
values[5]	36755	1			T84	253		T214	104		T424	147
values[6]	26842	1			T84	219		T214	88		T424	95
values[7]	21539	1			T84	132		T214	66		T424	75
values[8]	18693	1			T84	108		T214	69		T424	34
values[9]	16272	1			T84	82		T214	64		T424	17
values[10]	14683	1			T84	74		T214	68		T424	24
values[11]	13668	1			T84	54		T214	65		T424	19
values[12]	12987	1			T84	48		T214	67		T424	17
values[13]	12325	1			T84	62		T214	72		T424	19
values[14]	11879	1			T84	48		T214	56		T424	20
values[15]	11113	1			T84	34		T214	62		T424	14
values[16]	10631	1			T84	43		T214	71		T424	18
values[17]	10126	1			T84	24		T214	67		T424	15
values[18]	9823	1			T84	27		T214	46		T424	8
values[19]	9870	1			T84	20		T214	63		T424	16
values[20]	9453	1			T84	17		T214	65		T424	9
values[21]	9060	1			T84	19		T214	52		T424	11
values[22]	8705	1			T84	16		T214	50		T424	16
values[23]	8359	1			T84	23		T214	42		T424	13
values[24]	8086	1			T84	21		T214	39		T424	14
values[25]	7719	1			T84	13		T214	43		T424	12
values[26]	7434	1			T84	17		T214	33		T424	15
values[27]	7140	1			T84	22		T214	26		T424	18
values[28]	6820	1			T84	17		T214	48		T424	13
values[29]	6437	1			T84	14		T214	42		T424	14
values[30]	6219	1			T84	23		T214	41		T424	9
values[31]	5689	1			T84	24		T214	29		T424	11
values[32]	5297	1			T84	21		T214	23		T424	11
values[33]	4841	1			T84	15		T214	9		T424	11
values[34]	4532	1			T84	20		T214	5		T424	15
values[35]	4293	1			T84	11		T214	8		T424	10
values[36]	4100	1			T84	16		T214	9		T424	8
values[37]	3913	1			T84	24		T214	12		T424	9
values[38]	3701	1			T84	25		T214	5		T424	13
values[39]	3601	1			T84	24		T214	5		T424	10
values[40]	3493	1			T84	18		T214	6		T424	15
values[41]	3450	1			T84	24		T214	12		T424	9
values[42]	3289	1			T84	18		T214	8		T424	7
values[43]	3272	1			T84	28		T214	7		T424	11
values[44]	3184	1			T84	25		T214	7		T424	11
values[45]	3123	1			T84	16		T214	4		T424	7
values[46]	3168	1			T84	13		T214	8		T424	10
values[47]	3059	1			T84	15		T214	6		T424	13
values[48]	3039	1			T84	14		T214	1		T424	13
values[49]	2873	1			T84	18		T214	2		T424	7
values[50]	2844	1			T84	19		T214	4		T424	11
values[51]	2827	1			T84	18		T214	2		T424	7
values[52]	2819	1			T84	15		T214	1		T424	13
values[53]	2739	1			T84	17		T424	15		T435	16
values[54]	2726	1			T84	24		T424	10		T435	16
values[55]	2655	1			T84	15		T424	6		T435	16
values[56]	2572	1			T84	17		T424	11		T435	16
values[57]	2555	1			T84	20		T424	10		T435	16
values[58]	2492	1			T84	16		T424	8		T435	16
values[59]	2532	1			T84	19		T424	11		T435	16
values[60]	2488	1			T84	16		T424	21		T435	16
values[61]	2663	1			T84	9		T424	24		T435	16
values[62]	4023	1			T84	30		T424	28		T435	16
values[63]	11186	1			T84	168		T424	89		T435	18
values[64]	238850	1			T84	507		T424	314		T435	2799

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4844382	1			T78	9457		T79	103		T80	68
values[2]	816196	1			T78	1563		T79	40		T80	23
values[3]	88213	1			T78	249		T80	10		T84	301
values[4]	15406	1			T78	56		T80	1		T84	71
values[5]	5913	1			T78	6		T80	1		T84	44
values[6]	3532	1			T78	3		T84	64		T539	3
values[7]	2808	1			T78	1		T84	55		T539	1
values[8]	2396	1			T84	67		T424	1		T435	2
values[9]	2153	1			T84	42		T424	1		T435	2
values[10]	1997	1			T84	37		T424	3		T435	2
values[11]	1764	1			T84	21		T424	3		T435	1
values[12]	1557	1			T84	22		T424	1		T435	1
values[13]	1460	1			T84	17		T424	1		T435	1
values[14]	1305	1			T84	12		T424	2		T435	1
values[15]	1146	1			T84	13		T424	6		T435	1
values[16]	1108	1			T84	14		T424	8		T435	1
values[17]	1077	1			T84	12		T424	7		T435	1
values[18]	1008	1			T84	12		T424	3		T435	1
values[19]	893	1			T84	13		T424	2		T435	1
values[20]	878	1			T84	13		T424	3		T435	1
values[21]	953	1			T84	20		T424	1		T435	1
values[22]	867	1			T84	13		T424	2		T435	1
values[23]	845	1			T84	10		T424	1		T435	1
values[24]	829	1			T84	4		T424	1		T435	1
values[25]	809	1			T84	3		T424	1		T435	1
values[26]	785	1			T84	7		T424	2		T435	1
values[27]	674	1			T84	7		T424	1		T435	1
values[28]	681	1			T84	7		T424	1		T435	1
values[29]	597	1			T84	7		T424	4		T435	1
values[30]	593	1			T84	6		T424	2		T435	1
values[31]	533	1			T84	5		T424	2		T435	1
values[32]	514	1			T84	3		T424	2		T435	1
values[33]	563	1			T84	10		T424	4		T435	1
values[34]	580	1			T84	8		T424	4		T435	1
values[35]	544	1			T84	7		T424	1		T435	1
values[36]	493	1			T84	5		T424	1		T435	1
values[37]	476	1			T84	4		T424	1		T435	1
values[38]	509	1			T84	5		T424	1		T435	1
values[39]	430	1			T84	6		T424	1		T435	1
values[40]	465	1			T84	5		T424	2		T435	1
values[41]	450	1			T84	5		T424	1		T435	1
values[42]	485	1			T84	7		T424	1		T435	1
values[43]	475	1			T84	5		T424	1		T435	1
values[44]	482	1			T84	8		T424	1		T435	1
values[45]	459	1			T84	7		T424	1		T435	2
values[46]	421	1			T84	8		T424	1		T435	1
values[47]	413	1			T84	7		T424	1		T435	1
values[48]	409	1			T84	6		T424	2		T435	1
values[49]	394	1			T84	7		T424	1		T435	1
values[50]	363	1			T84	6		T424	1		T435	1
values[51]	413	1			T84	9		T424	2		T435	1
values[52]	374	1			T84	5		T424	2		T435	1
values[53]	331	1			T84	4		T424	1		T435	1
values[54]	315	1			T84	8		T424	1		T435	1
values[55]	339	1			T84	7		T424	1		T435	1
values[56]	343	1			T84	3		T424	3		T435	1
values[57]	339	1			T84	7		T424	1		T435	1
values[58]	337	1			T84	7		T424	1		T435	1
values[59]	344	1			T84	7		T424	2		T435	1
values[60]	341	1			T84	9		T424	2		T435	1
values[61]	379	1			T84	11		T424	3		T435	1
values[62]	653	1			T84	25		T424	5		T435	1
values[63]	2431	1			T84	113		T424	36		T435	1
values[64]	23337	1			T84	254		T424	105		T435	142

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	604912	1			T78	2289		T79	1		T80	1
values[2]	2625275	1			T78	4691		T79	94		T80	1
values[3]	1245463	1			T78	2682		T79	35		T80	120
values[4]	155107	1			T78	475		T80	41		T84	1239
values[5]	77356	1			T78	213		T80	3		T84	818
values[6]	49893	1			T78	108		T84	501		T214	54
values[7]	35603	1			T78	68		T84	396		T214	28
values[8]	27747	1			T78	57		T84	290		T214	58
values[9]	23548	1			T78	29		T84	238		T214	72
values[10]	20563	1			T78	12		T84	171		T214	75
values[11]	18269	1			T78	8		T84	147		T214	57
values[12]	17160	1			T78	10		T84	138		T214	58
values[13]	15918	1			T84	90		T214	59		T424	15
values[14]	14771	1			T84	69		T214	79		T424	12
values[15]	14029	1			T84	54		T214	86		T424	13
values[16]	13605	1			T84	66		T214	64		T424	15
values[17]	13033	1			T84	70		T214	64		T424	12
values[18]	12346	1			T84	60		T214	78		T424	15
values[19]	11856	1			T84	41		T214	54		T424	15
values[20]	11357	1			T84	23		T214	35		T424	13
values[21]	10524	1			T84	25		T214	43		T424	15
values[22]	10121	1			T84	26		T214	58		T424	16
values[23]	9615	1			T84	25		T214	59		T424	16
values[24]	9224	1			T84	16		T214	37		T424	13
values[25]	8938	1			T84	24		T214	55		T424	12
values[26]	8554	1			T84	20		T214	63		T424	17
values[27]	8181	1			T84	17		T214	39		T424	30
values[28]	7753	1			T84	19		T214	49		T424	20
values[29]	7157	1			T84	21		T214	36		T424	12
values[30]	6873	1			T84	13		T214	21		T424	14
values[31]	6468	1			T84	20		T214	17		T424	11
values[32]	5765	1			T84	17		T214	21		T424	20
values[33]	5388	1			T84	19		T214	24		T424	17
values[34]	5166	1			T84	13		T214	21		T424	23
values[35]	4855	1			T84	20		T214	17		T424	18
values[36]	4606	1			T84	23		T214	17		T424	20
values[37]	4443	1			T84	16		T214	24		T424	14
values[38]	4136	1			T84	18		T214	10		T424	20
values[39]	4002	1			T84	18		T214	14		T424	8
values[40]	3716	1			T84	17		T214	11		T424	9
values[41]	3746	1			T84	35		T214	5		T424	13
values[42]	3620	1			T84	31		T214	2		T424	19
values[43]	3605	1			T84	24		T214	7		T424	24
values[44]	3577	1			T84	20		T214	2		T424	30
values[45]	3376	1			T84	25		T214	13		T424	20
values[46]	3297	1			T84	15		T214	5		T424	15
values[47]	3372	1			T84	19		T214	5		T424	17
values[48]	3282	1			T84	15		T214	6		T424	12
values[49]	3319	1			T84	16		T214	15		T424	11
values[50]	3236	1			T84	20		T214	8		T424	23
values[51]	3250	1			T84	25		T214	1		T424	19
values[52]	3268	1			T84	35		T424	20		T435	16
values[53]	3181	1			T84	28		T424	13		T435	16
values[54]	3082	1			T84	25		T424	5		T435	16
values[55]	3003	1			T84	18		T424	10		T435	18
values[56]	2956	1			T84	21		T424	9		T435	16
values[57]	2845	1			T84	24		T424	7		T435	16
values[58]	2864	1			T84	18		T424	8		T435	16
values[59]	2803	1			T84	14		T424	19		T435	17
values[60]	2755	1			T84	15		T424	19		T435	16
values[61]	2843	1			T84	15		T424	21		T435	18
values[62]	3917	1			T84	55		T424	45		T435	17
values[63]	9530	1			T84	178		T424	77		T435	17
values[64]	233062	1			T84	432		T424	203		T435	2952