Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1982546	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

38383003

1

T1

6027

T2

116763

T3

12847

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	28236168	1			T1	2547		T2	102451		T3	4249
values[0x0]	10667603	1			T1	3480		T2	14312		T3	8598
values[0x1]	1461778	1			T1	302		T2	11		T3	226

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	643598	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

39721951

1

T1

6329

T2

116774

T3

13073

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	19047762	1			T1	3165		T2	58387		T3	6537
valid_sources[0x01]	19046639	1			T1	3164		T2	58387		T3	6536
valid_sources[0x02]	36483	1			T404	28		T392	151		T393	86
valid_sources[0x03]	39494	1			T404	19		T392	161		T393	127
valid_sources[0x04]	35798	1			T83	1		T404	25		T392	171
valid_sources[0x05]	37812	1			T404	28		T392	173		T393	125
valid_sources[0x06]	36437	1			T404	27		T392	170		T393	88
valid_sources[0x07]	36481	1			T82	4		T404	28		T392	187
valid_sources[0x08]	36010	1			T82	3		T83	3		T404	29
valid_sources[0x09]	37214	1			T82	2		T83	3		T404	29
valid_sources[0x0a]	36265	1			T404	30		T392	204		T393	95
valid_sources[0x0b]	37092	1			T82	3		T83	2		T51	1
valid_sources[0x0c]	36857	1			T51	8		T404	21		T392	151
valid_sources[0x0d]	36294	1			T83	4		T404	28		T392	157
valid_sources[0x0e]	36426	1			T404	56		T392	170		T393	133
valid_sources[0x0f]	36596	1			T82	3		T83	1		T404	26
valid_sources[0x10]	36331	1			T404	30		T392	169		T393	183
valid_sources[0x11]	36018	1			T204	39		T404	24		T392	156
valid_sources[0x12]	35892	1			T57	5		T404	21		T392	166
valid_sources[0x13]	36304	1			T83	1		T404	17		T392	182
valid_sources[0x14]	36505	1			T83	1		T404	34		T392	145
valid_sources[0x15]	36702	1			T57	3		T83	2		T404	31
valid_sources[0x16]	36277	1			T82	2		T404	44		T392	179
valid_sources[0x17]	36747	1			T404	32		T392	153		T393	145
valid_sources[0x18]	37188	1			T404	24		T392	163		T393	101
valid_sources[0x19]	36198	1			T83	2		T404	21		T392	196
valid_sources[0x1a]	35929	1			T82	6		T83	2		T404	24
valid_sources[0x1b]	36283	1			T83	1		T404	45		T392	172
valid_sources[0x1c]	36594	1			T82	2		T404	39		T392	182
valid_sources[0x1d]	36882	1			T82	1		T404	41		T392	147
valid_sources[0x1e]	39428	1			T404	19		T392	175		T393	125
valid_sources[0x1f]	35697	1			T404	28		T392	154		T393	108
valid_sources[0x20]	36454	1			T82	1		T404	23		T392	166

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27525065

1

T1

2547

T2

102451

T3

4249

values[0x0]

all_enables

biggest_size

10615475

1

T1

3480

T2

14312

T3

8598

values[0x1]

all_enables

biggest_size

242463

1

T57

27

T82

18

T83

18

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2869032	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

453748

1

T78

56

T79

20

T80

21

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1124700	1			T78	236		T79	55		T80	60
values[0x0]	1072328	1			T78	28		T79	52		T80	66
values[0x1]	1125752	1			T78	231		T79	53		T80	70

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2221291	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1101489

1

T78

197

T79

53

T80

57

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52369	1			T78	6		T79	3		T80	3
valid_sources[0x01]	52935	1			T78	9		T79	1		T80	1
valid_sources[0x02]	52561	1			T78	14		T79	4		T80	2
valid_sources[0x03]	52540	1			T78	6		T80	2		T84	10
valid_sources[0x04]	52578	1			T78	10		T80	7		T84	8
valid_sources[0x05]	50122	1			T78	8		T79	8		T80	6
valid_sources[0x06]	51845	1			T78	7		T79	2		T80	4
valid_sources[0x07]	51639	1			T78	6		T79	6		T80	2
valid_sources[0x08]	52795	1			T78	9		T80	3		T84	9
valid_sources[0x09]	51506	1			T78	7		T79	3		T80	4
valid_sources[0x0a]	52177	1			T78	9		T79	5		T80	2
valid_sources[0x0b]	52963	1			T78	6		T80	1		T84	15
valid_sources[0x0c]	52523	1			T78	7		T80	5		T84	12
valid_sources[0x0d]	51677	1			T78	10		T79	2		T80	1
valid_sources[0x0e]	53365	1			T78	12		T79	3		T80	2
valid_sources[0x0f]	52152	1			T78	21		T79	1		T80	4
valid_sources[0x10]	52061	1			T78	5		T79	4		T80	7
valid_sources[0x11]	52107	1			T78	8		T79	2		T80	3
valid_sources[0x12]	51229	1			T78	4		T79	3		T80	5
valid_sources[0x13]	51987	1			T78	6		T79	3		T80	2
valid_sources[0x14]	51095	1			T78	8		T79	1		T80	6
valid_sources[0x15]	51900	1			T78	3		T79	2		T80	2
valid_sources[0x16]	51969	1			T78	5		T79	5		T80	1
valid_sources[0x17]	51217	1			T78	8		T79	1		T80	5
valid_sources[0x18]	51107	1			T78	7		T84	7		T214	284
valid_sources[0x19]	52990	1			T78	3		T79	3		T80	1
valid_sources[0x1a]	52040	1			T78	2		T79	4		T80	3
valid_sources[0x1b]	52651	1			T78	7		T79	2		T80	2
valid_sources[0x1c]	52332	1			T78	12		T79	4		T80	4
valid_sources[0x1d]	51322	1			T78	7		T79	1		T80	2
valid_sources[0x1e]	52034	1			T78	8		T79	4		T80	2
valid_sources[0x1f]	51191	1			T78	9		T79	2		T80	5
valid_sources[0x20]	50920	1			T78	3		T79	1		T80	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47417

1

T78

24

T79

3

T80

2

values[0x0]

all_enables

biggest_size

358863

1

T78

16

T79

16

T80

16

values[0x1]

all_enables

biggest_size

47468

1

T78

16

T79

1

T80

3

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3057594	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

497816

1

T78

54

T79

19

T80

18

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1218239	1			T78	216		T79	44		T80	28
values[0x0]	1120012	1			T78	47		T79	52		T80	33
values[0x1]	1217159	1			T78	227		T79	47		T80	42

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2345306	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1210104

1

T78

182

T79

50

T80

39

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	55424	1			T78	6		T79	1		T80	1
valid_sources[0x01]	55627	1			T78	8		T80	1		T84	4
valid_sources[0x02]	55446	1			T78	8		T79	3		T80	2
valid_sources[0x03]	55168	1			T78	14		T79	1		T84	12
valid_sources[0x04]	55558	1			T78	4		T80	4		T84	10
valid_sources[0x05]	54731	1			T78	8		T79	2		T80	1
valid_sources[0x06]	56140	1			T78	7		T79	5		T84	9
valid_sources[0x07]	55000	1			T78	6		T79	3		T80	1
valid_sources[0x08]	55333	1			T78	10		T79	2		T80	1
valid_sources[0x09]	55997	1			T78	11		T79	5		T84	8
valid_sources[0x0a]	55912	1			T78	5		T79	1		T84	10
valid_sources[0x0b]	55736	1			T78	8		T79	1		T84	6
valid_sources[0x0c]	55629	1			T78	7		T79	2		T80	1
valid_sources[0x0d]	55297	1			T78	8		T79	4		T80	6
valid_sources[0x0e]	55552	1			T78	9		T79	2		T80	3
valid_sources[0x0f]	54793	1			T78	13		T79	2		T80	1
valid_sources[0x10]	56047	1			T78	5		T79	2		T80	6
valid_sources[0x11]	55332	1			T78	7		T79	1		T80	2
valid_sources[0x12]	54767	1			T78	5		T79	4		T80	3
valid_sources[0x13]	56103	1			T78	8		T79	4		T80	2
valid_sources[0x14]	55549	1			T78	10		T79	1		T84	13
valid_sources[0x15]	55332	1			T78	5		T79	2		T80	2
valid_sources[0x16]	56322	1			T78	7		T79	2		T80	1
valid_sources[0x17]	55844	1			T78	5		T80	1		T84	13
valid_sources[0x18]	54462	1			T78	16		T79	2		T84	5
valid_sources[0x19]	55154	1			T78	4		T79	3		T80	3
valid_sources[0x1a]	56298	1			T78	8		T79	5		T84	14
valid_sources[0x1b]	56543	1			T78	9		T79	6		T84	9
valid_sources[0x1c]	55094	1			T78	6		T79	1		T80	2
valid_sources[0x1d]	55402	1			T78	6		T79	5		T84	8
valid_sources[0x1e]	55924	1			T78	9		T79	1		T80	3
valid_sources[0x1f]	55599	1			T78	6		T79	1		T84	12
valid_sources[0x20]	55578	1			T78	6		T79	2		T80	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

52554

1

T78

25

T79

2

T80

2

values[0x0]

all_enables

biggest_size

392932

1

T78

19

T79

15

T80

13

values[0x1]

all_enables

biggest_size

52330

1

T78

10

T79

2

T80

3

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2894533	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

457593

1

T78

51

T79

17

T80

26

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1135287	1			T78	220		T79	58		T80	56
values[0x0]	1080378	1			T78	40		T79	36		T80	64
values[0x1]	1136461	1			T78	231		T79	36		T80	46

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2240901	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1111225

1

T78

187

T79

36

T80

53

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52906	1			T78	6		T79	3		T84	14
valid_sources[0x01]	52019	1			T78	5		T79	1		T84	6
valid_sources[0x02]	51653	1			T78	9		T79	6		T80	1
valid_sources[0x03]	52863	1			T78	9		T79	2		T84	6
valid_sources[0x04]	52693	1			T78	7		T79	1		T84	9
valid_sources[0x05]	51807	1			T78	6		T79	5		T80	12
valid_sources[0x06]	53943	1			T78	7		T79	4		T80	5
valid_sources[0x07]	50882	1			T78	13		T79	6		T84	6
valid_sources[0x08]	52347	1			T78	8		T79	2		T80	7
valid_sources[0x09]	52681	1			T78	11		T79	2		T84	12
valid_sources[0x0a]	51689	1			T78	3		T79	1		T84	13
valid_sources[0x0b]	53077	1			T78	5		T79	2		T80	13
valid_sources[0x0c]	52544	1			T78	5		T79	1		T84	10
valid_sources[0x0d]	53194	1			T78	13		T79	1		T80	7
valid_sources[0x0e]	53494	1			T78	13		T79	3		T80	9
valid_sources[0x0f]	52379	1			T78	9		T79	1		T84	10
valid_sources[0x10]	51681	1			T78	4		T79	2		T80	9
valid_sources[0x11]	52968	1			T78	10		T79	3		T84	10
valid_sources[0x12]	52815	1			T78	6		T79	1		T80	4
valid_sources[0x13]	52409	1			T78	7		T84	7		T214	319
valid_sources[0x14]	52409	1			T78	11		T79	1		T80	5
valid_sources[0x15]	52438	1			T78	4		T79	1		T84	11
valid_sources[0x16]	52365	1			T78	8		T80	5		T84	4
valid_sources[0x17]	52685	1			T78	8		T79	2		T84	14
valid_sources[0x18]	52708	1			T78	3		T79	1		T84	6
valid_sources[0x19]	51708	1			T78	7		T79	4		T80	3
valid_sources[0x1a]	52397	1			T78	4		T80	4		T84	11
valid_sources[0x1b]	51479	1			T78	8		T79	1		T80	3
valid_sources[0x1c]	52743	1			T78	12		T84	8		T214	248
valid_sources[0x1d]	52354	1			T78	10		T79	2		T84	11
valid_sources[0x1e]	52011	1			T78	8		T80	7		T84	10
valid_sources[0x1f]	51962	1			T78	5		T79	1		T84	5
valid_sources[0x20]	52989	1			T78	4		T84	9		T214	288

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47990

1

T78

19

T79

2

T80

2

values[0x0]

all_enables

biggest_size

361539

1

T78

16

T79

13

T80

20

values[0x1]

all_enables

biggest_size

48064

1

T78

16

T79

2

T80

4