Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	531504997	61577348	0	0
DepthKnown_A	531504997	531397429	0	0
RvalidKnown_A	531504997	531397429	0	0
WreadyKnown_A	531504997	531397429	0	0
gen_passthru_fifo.paramCheckPass	1025	1025	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	531504997	61577348	0	0
T1	97825	11742	0	0
T2	128374	143772	0	0
T3	170024	22050	0	0
T4	579948	84733	0	0
T5	131161	18150	0	0
T6	107827	156792	0	0
T19	294484	392629	0	0
T35	293402	38453	0	0
T47	135245	146843	0	0
T88	90883	11260	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	531504997	531397429	0	0
T1	97825	97767	0	0
T2	128374	128368	0	0
T3	170024	169915	0	0
T4	579948	579843	0	0
T5	131161	131110	0	0
T6	107827	107816	0	0
T19	294484	294479	0	0
T35	293402	293278	0	0
T47	135245	135239	0	0
T88	90883	90825	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	531504997	531397429	0	0
T1	97825	97767	0	0
T2	128374	128368	0	0
T3	170024	169915	0	0
T4	579948	579843	0	0
T5	131161	131110	0	0
T6	107827	107816	0	0
T19	294484	294479	0	0
T35	293402	293278	0	0
T47	135245	135239	0	0
T88	90883	90825	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	531504997	531397429	0	0
T1	97825	97767	0	0
T2	128374	128368	0	0
T3	170024	169915	0	0
T4	579948	579843	0	0
T5	131161	131110	0	0
T6	107827	107816	0	0
T19	294484	294479	0	0
T35	293402	293278	0	0
T47	135245	135239	0	0
T88	90883	90825	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1025	1025	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T19	1	1	0	0
T35	1	1	0	0
T47	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	531504997	47506697	0	0
DepthKnown_A	531504997	531397429	0	0
RvalidKnown_A	531504997	531397429	0	0
WreadyKnown_A	531504997	531397429	0	0
gen_passthru_fifo.paramCheckPass	1025	1025	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	531504997	47506697	0	0
T1	97825	9015	0	0
T2	128374	124339	0	0
T3	170024	15125	0	0
T4	579948	60984	0	0
T5	131161	12967	0	0
T6	107827	145405	0	0
T19	294484	375467	0	0
T35	293402	28871	0	0
T47	135245	127929	0	0
T88	90883	8404	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	531504997	531397429	0	0
T1	97825	97767	0	0
T2	128374	128368	0	0
T3	170024	169915	0	0
T4	579948	579843	0	0
T5	131161	131110	0	0
T6	107827	107816	0	0
T19	294484	294479	0	0
T35	293402	293278	0	0
T47	135245	135239	0	0
T88	90883	90825	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	531504997	531397429	0	0
T1	97825	97767	0	0
T2	128374	128368	0	0
T3	170024	169915	0	0
T4	579948	579843	0	0
T5	131161	131110	0	0
T6	107827	107816	0	0
T19	294484	294479	0	0
T35	293402	293278	0	0
T47	135245	135239	0	0
T88	90883	90825	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	531504997	531397429	0	0
T1	97825	97767	0	0
T2	128374	128368	0	0
T3	170024	169915	0	0
T4	579948	579843	0	0
T5	131161	131110	0	0
T6	107827	107816	0	0
T19	294484	294479	0	0
T35	293402	293278	0	0
T47	135245	135239	0	0
T88	90883	90825	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1025	1025	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T19	1	1	0	0
T35	1	1	0	0
T47	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	531504997	44932456	0	0
DepthKnown_A	531504997	531397429	0	0
RvalidKnown_A	531504997	531397429	0	0
WreadyKnown_A	531504997	531397429	0	0
gen_passthru_fifo.paramCheckPass	1025	1025	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	531504997	44932456	0	0
T1	97825	6499	0	0
T2	128374	171355	0	0
T3	170024	13555	0	0
T4	579948	35043	0	0
T5	131161	7195	0	0
T6	107827	134463	0	0
T19	294484	525105	0	0
T35	293402	20672	0	0
T47	135245	194799	0	0
T88	90883	7741	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	531504997	531397429	0	0
T1	97825	97767	0	0
T2	128374	128368	0	0
T3	170024	169915	0	0
T4	579948	579843	0	0
T5	131161	131110	0	0
T6	107827	107816	0	0
T19	294484	294479	0	0
T35	293402	293278	0	0
T47	135245	135239	0	0
T88	90883	90825	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	531504997	531397429	0	0
T1	97825	97767	0	0
T2	128374	128368	0	0
T3	170024	169915	0	0
T4	579948	579843	0	0
T5	131161	131110	0	0
T6	107827	107816	0	0
T19	294484	294479	0	0
T35	293402	293278	0	0
T47	135245	135239	0	0
T88	90883	90825	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	531504997	531397429	0	0
T1	97825	97767	0	0
T2	128374	128368	0	0
T3	170024	169915	0	0
T4	579948	579843	0	0
T5	131161	131110	0	0
T6	107827	107816	0	0
T19	294484	294479	0	0
T35	293402	293278	0	0
T47	135245	135239	0	0
T88	90883	90825	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1025	1025	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T19	1	1	0	0
T35	1	1	0	0
T47	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	531504997	38125677	0	0
DepthKnown_A	531504997	531397429	0	0
RvalidKnown_A	531504997	531397429	0	0
WreadyKnown_A	531504997	531397429	0	0
gen_passthru_fifo.paramCheckPass	1025	1025	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	531504997	38125677	0	0
T1	97825	6329	0	0
T2	128374	116774	0	0
T3	170024	13073	0	0
T4	579948	34185	0	0
T5	131161	6917	0	0
T6	107827	133935	0	0
T19	294484	524776	0	0
T35	293402	20285	0	0
T47	135245	119792	0	0
T88	90883	7153	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	531504997	531397429	0	0
T1	97825	97767	0	0
T2	128374	128368	0	0
T3	170024	169915	0	0
T4	579948	579843	0	0
T5	131161	131110	0	0
T6	107827	107816	0	0
T19	294484	294479	0	0
T35	293402	293278	0	0
T47	135245	135239	0	0
T88	90883	90825	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	531504997	531397429	0	0
T1	97825	97767	0	0
T2	128374	128368	0	0
T3	170024	169915	0	0
T4	579948	579843	0	0
T5	131161	131110	0	0
T6	107827	107816	0	0
T19	294484	294479	0	0
T35	293402	293278	0	0
T47	135245	135239	0	0
T88	90883	90825	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	531504997	531397429	0	0
T1	97825	97767	0	0
T2	128374	128368	0	0
T3	170024	169915	0	0
T4	579948	579843	0	0
T5	131161	131110	0	0
T6	107827	107816	0	0
T19	294484	294479	0	0
T35	293402	293278	0	0
T47	135245	135239	0	0
T88	90883	90825	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1025	1025	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T19	1	1	0	0
T35	1	1	0	0
T47	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	601409256	87026	0	0
DepthKnown_A	601409256	601285211	0	0
RvalidKnown_A	601409256	601285211	0	0
WreadyKnown_A	601409256	601285211	0	0
gen_passthru_fifo.paramCheckPass	2935	2935	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601409256	87026	0	0
T1	97825	18	0	0
T2	128374	34	0	0
T3	170024	43	0	0
T4	579948	81	0	0
T5	131161	26	0	0
T6	107827	38	0	0
T19	294484	14	0	0
T35	293402	151	0	0
T47	135245	34	0	0
T88	90883	34	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601409256	601285211	0	0
T1	97825	97767	0	0
T2	128374	128368	0	0
T3	170024	169915	0	0
T4	579948	579843	0	0
T5	131161	131110	0	0
T6	107827	107816	0	0
T19	294484	294479	0	0
T35	293402	293278	0	0
T47	135245	135239	0	0
T88	90883	90825	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601409256	601285211	0	0
T1	97825	97767	0	0
T2	128374	128368	0	0
T3	170024	169915	0	0
T4	579948	579843	0	0
T5	131161	131110	0	0
T6	107827	107816	0	0
T19	294484	294479	0	0
T35	293402	293278	0	0
T47	135245	135239	0	0
T88	90883	90825	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601409256	601285211	0	0
T1	97825	97767	0	0
T2	128374	128368	0	0
T3	170024	169915	0	0
T4	579948	579843	0	0
T5	131161	131110	0	0
T6	107827	107816	0	0
T19	294484	294479	0	0
T35	293402	293278	0	0
T47	135245	135239	0	0
T88	90883	90825	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2935	2935	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T19	1	1	0	0
T35	1	1	0	0
T47	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	601409256	88986	0	0
DepthKnown_A	601409256	601285211	0	0
RvalidKnown_A	601409256	601285211	0	0
WreadyKnown_A	601409256	601285211	0	0
gen_passthru_fifo.paramCheckPass	2935	2935	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601409256	88986	0	0
T1	97825	18	0	0
T2	128374	34	0	0
T3	170024	43	0	0
T4	579948	81	0	0
T5	131161	26	0	0
T6	107827	38	0	0
T19	294484	14	0	0
T35	293402	151	0	0
T47	135245	34	0	0
T88	90883	34	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601409256	601285211	0	0
T1	97825	97767	0	0
T2	128374	128368	0	0
T3	170024	169915	0	0
T4	579948	579843	0	0
T5	131161	131110	0	0
T6	107827	107816	0	0
T19	294484	294479	0	0
T35	293402	293278	0	0
T47	135245	135239	0	0
T88	90883	90825	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601409256	601285211	0	0
T1	97825	97767	0	0
T2	128374	128368	0	0
T3	170024	169915	0	0
T4	579948	579843	0	0
T5	131161	131110	0	0
T6	107827	107816	0	0
T19	294484	294479	0	0
T35	293402	293278	0	0
T47	135245	135239	0	0
T88	90883	90825	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601409256	601285211	0	0
T1	97825	97767	0	0
T2	128374	128368	0	0
T3	170024	169915	0	0
T4	579948	579843	0	0
T5	131161	131110	0	0
T6	107827	107816	0	0
T19	294484	294479	0	0
T35	293402	293278	0	0
T47	135245	135239	0	0
T88	90883	90825	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2935	2935	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T19	1	1	0	0
T35	1	1	0	0
T47	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	601409256	50870	0	0
DepthKnown_A	601409256	601285211	0	0
RvalidKnown_A	601409256	601285211	0	0
WreadyKnown_A	601409256	601285211	0	0
gen_passthru_fifo.paramCheckPass	2935	2935	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601409256	50870	0	0
T1	97825	15	0	0
T2	128374	5	0	0
T3	170024	41	0	0
T4	579948	71	0	0
T5	131161	23	0	0
T6	107827	32	0	0
T19	294484	13	0	0
T35	293402	95	0	0
T47	135245	5	0	0
T88	90883	33	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601409256	601285211	0	0
T1	97825	97767	0	0
T2	128374	128368	0	0
T3	170024	169915	0	0
T4	579948	579843	0	0
T5	131161	131110	0	0
T6	107827	107816	0	0
T19	294484	294479	0	0
T35	293402	293278	0	0
T47	135245	135239	0	0
T88	90883	90825	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601409256	601285211	0	0
T1	97825	97767	0	0
T2	128374	128368	0	0
T3	170024	169915	0	0
T4	579948	579843	0	0
T5	131161	131110	0	0
T6	107827	107816	0	0
T19	294484	294479	0	0
T35	293402	293278	0	0
T47	135245	135239	0	0
T88	90883	90825	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601409256	601285211	0	0
T1	97825	97767	0	0
T2	128374	128368	0	0
T3	170024	169915	0	0
T4	579948	579843	0	0
T5	131161	131110	0	0
T6	107827	107816	0	0
T19	294484	294479	0	0
T35	293402	293278	0	0
T47	135245	135239	0	0
T88	90883	90825	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2935	2935	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T19	1	1	0	0
T35	1	1	0	0
T47	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	601409256	50870	0	0
DepthKnown_A	601409256	601285211	0	0
RvalidKnown_A	601409256	601285211	0	0
WreadyKnown_A	601409256	601285211	0	0
gen_passthru_fifo.paramCheckPass	2935	2935	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601409256	50870	0	0
T1	97825	15	0	0
T2	128374	5	0	0
T3	170024	41	0	0
T4	579948	71	0	0
T5	131161	23	0	0
T6	107827	32	0	0
T19	294484	13	0	0
T35	293402	95	0	0
T47	135245	5	0	0
T88	90883	33	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601409256	601285211	0	0
T1	97825	97767	0	0
T2	128374	128368	0	0
T3	170024	169915	0	0
T4	579948	579843	0	0
T5	131161	131110	0	0
T6	107827	107816	0	0
T19	294484	294479	0	0
T35	293402	293278	0	0
T47	135245	135239	0	0
T88	90883	90825	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601409256	601285211	0	0
T1	97825	97767	0	0
T2	128374	128368	0	0
T3	170024	169915	0	0
T4	579948	579843	0	0
T5	131161	131110	0	0
T6	107827	107816	0	0
T19	294484	294479	0	0
T35	293402	293278	0	0
T47	135245	135239	0	0
T88	90883	90825	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601409256	601285211	0	0
T1	97825	97767	0	0
T2	128374	128368	0	0
T3	170024	169915	0	0
T4	579948	579843	0	0
T5	131161	131110	0	0
T6	107827	107816	0	0
T19	294484	294479	0	0
T35	293402	293278	0	0
T47	135245	135239	0	0
T88	90883	90825	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2935	2935	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T19	1	1	0	0
T35	1	1	0	0
T47	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	601409256	36156	0	0
DepthKnown_A	601409256	601285211	0	0
RvalidKnown_A	601409256	601285211	0	0
WreadyKnown_A	601409256	601285211	0	0
gen_passthru_fifo.paramCheckPass	2935	2935	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601409256	36156	0	0
T1	97825	3	0	0
T2	128374	29	0	0
T3	170024	2	0	0
T4	579948	10	0	0
T5	131161	3	0	0
T6	107827	6	0	0
T19	294484	1	0	0
T35	293402	56	0	0
T47	135245	29	0	0
T88	90883	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601409256	601285211	0	0
T1	97825	97767	0	0
T2	128374	128368	0	0
T3	170024	169915	0	0
T4	579948	579843	0	0
T5	131161	131110	0	0
T6	107827	107816	0	0
T19	294484	294479	0	0
T35	293402	293278	0	0
T47	135245	135239	0	0
T88	90883	90825	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601409256	601285211	0	0
T1	97825	97767	0	0
T2	128374	128368	0	0
T3	170024	169915	0	0
T4	579948	579843	0	0
T5	131161	131110	0	0
T6	107827	107816	0	0
T19	294484	294479	0	0
T35	293402	293278	0	0
T47	135245	135239	0	0
T88	90883	90825	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601409256	601285211	0	0
T1	97825	97767	0	0
T2	128374	128368	0	0
T3	170024	169915	0	0
T4	579948	579843	0	0
T5	131161	131110	0	0
T6	107827	107816	0	0
T19	294484	294479	0	0
T35	293402	293278	0	0
T47	135245	135239	0	0
T88	90883	90825	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2935	2935	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T19	1	1	0	0
T35	1	1	0	0
T47	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	601409256	38116	0	0
DepthKnown_A	601409256	601285211	0	0
RvalidKnown_A	601409256	601285211	0	0
WreadyKnown_A	601409256	601285211	0	0
gen_passthru_fifo.paramCheckPass	2935	2935	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601409256	38116	0	0
T1	97825	3	0	0
T2	128374	29	0	0
T3	170024	2	0	0
T4	579948	10	0	0
T5	131161	3	0	0
T6	107827	6	0	0
T19	294484	1	0	0
T35	293402	56	0	0
T47	135245	29	0	0
T88	90883	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601409256	601285211	0	0
T1	97825	97767	0	0
T2	128374	128368	0	0
T3	170024	169915	0	0
T4	579948	579843	0	0
T5	131161	131110	0	0
T6	107827	107816	0	0
T19	294484	294479	0	0
T35	293402	293278	0	0
T47	135245	135239	0	0
T88	90883	90825	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601409256	601285211	0	0
T1	97825	97767	0	0
T2	128374	128368	0	0
T3	170024	169915	0	0
T4	579948	579843	0	0
T5	131161	131110	0	0
T6	107827	107816	0	0
T19	294484	294479	0	0
T35	293402	293278	0	0
T47	135245	135239	0	0
T88	90883	90825	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	601409256	601285211	0	0
T1	97825	97767	0	0
T2	128374	128368	0	0
T3	170024	169915	0	0
T4	579948	579843	0	0
T5	131161	131110	0	0
T6	107827	107816	0	0
T19	294484	294479	0	0
T35	293402	293278	0	0
T47	135245	135239	0	0
T88	90883	90825	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2935	2935	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T19	1	1	0	0
T35	1	1	0	0
T47	1	1	0	0
T88	1	1	0	0