Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T68,*T69,*T81	Yes	T68,T69,T81	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T57,T82,T83	Yes	T57,T82,T83	INPUT
tl_i.a_valid	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	INPUT
tl_o.a_ready	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	OUTPUT
tl_o.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	OUTPUT
tl_o.d_sink	Yes	Yes	T78,T80,T84	Yes	T78,T79,T80	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T69,*T264,*T699	Yes	T69,T264,T699	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T2,*T47,*T48	Yes	T2,T47,T48	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T4,T368,T700	Yes	T4,T368,T700	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T4,T86,T87	Yes	T4,T86,T87	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T4,T86,T87	Yes	T4,T86,T87	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T4,T368,T700	Yes	T4,T368,T700	OUTPUT
cio_rx_i	Yes	Yes	T1,T3,T35	Yes	T1,T3,T4	INPUT
cio_tx_o	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T196,T217,T141	Yes	T196,T217,T141	OUTPUT
intr_tx_empty_o	Yes	Yes	T217,T141,T222	Yes	T217,T141,T222	OUTPUT
intr_rx_watermark_o	Yes	Yes	T217,T141,T222	Yes	T217,T141,T222	OUTPUT
intr_tx_done_o	Yes	Yes	T217,T141,T350	Yes	T217,T141,T350	OUTPUT
intr_rx_overflow_o	Yes	Yes	T217,T141,T350	Yes	T217,T141,T350	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T328,T339,T340	Yes	T328,T339,T340	OUTPUT
intr_rx_break_err_o	Yes	Yes	T328,T339,T340	Yes	T328,T339,T340	OUTPUT
intr_rx_timeout_o	Yes	Yes	T328,T339,T340	Yes	T328,T339,T340	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T328,T339,T340	Yes	T328,T339,T340	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T68,*T69,*T81	Yes	T68,T69,T81	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T57,T82,T83	Yes	T57,T82,T83	INPUT
tl_i.a_valid	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	INPUT
tl_o.a_ready	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	OUTPUT
tl_o.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	OUTPUT
tl_o.d_sink	Yes	Yes	T78,T80,T84	Yes	T78,T79,T80	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T69,*T264,*T699	Yes	T69,T264,T699	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T80,T84	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T2,*T47,*T48	Yes	T2,T47,T48	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T4,T700,T373	Yes	T4,T700,T373	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T4,T86,T87	Yes	T4,T86,T87	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T4,T86,T87	Yes	T4,T86,T87	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T4,T700,T373	Yes	T4,T700,T373	OUTPUT
cio_rx_i	Yes	Yes	T3,T35,T36	Yes	T1,T3,T4	INPUT
cio_tx_o	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T196,T222,T328	Yes	T196,T222,T328	OUTPUT
intr_tx_empty_o	Yes	Yes	T222,T328,T223	Yes	T222,T328,T223	OUTPUT
intr_rx_watermark_o	Yes	Yes	T222,T328,T223	Yes	T222,T328,T223	OUTPUT
intr_tx_done_o	Yes	Yes	T350,T222,T328	Yes	T350,T222,T328	OUTPUT
intr_rx_overflow_o	Yes	Yes	T350,T222,T328	Yes	T350,T222,T328	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T328,T339,T340	Yes	T328,T339,T340	OUTPUT
intr_rx_break_err_o	Yes	Yes	T328,T339,T340	Yes	T328,T339,T340	OUTPUT
intr_rx_timeout_o	Yes	Yes	T328,T339,T340	Yes	T328,T339,T340	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T328,T339,T340	Yes	T328,T339,T340	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T217,T218,T219	Yes	T217,T218,T219	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T217,T218,T219	Yes	T217,T218,T219	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T68,*T69,*T81	Yes	T68,T69,T81	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T57,T82,T83	Yes	T57,T82,T83	INPUT
tl_i.a_valid	Yes	Yes	T217,T52,T218	Yes	T217,T52,T218	INPUT
tl_o.a_ready	Yes	Yes	T217,T52,T218	Yes	T217,T52,T218	OUTPUT
tl_o.d_error	Yes	Yes	T78,T80,T84	Yes	T78,T80,T84	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T217,T218,T219	Yes	T217,T218,T219	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T217,T218,T219	Yes	T217,T52,T218	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T217,T218,T219	Yes	T217,T52,T218	OUTPUT
tl_o.d_sink	Yes	Yes	T78,T80,T84	Yes	T78,T80,T84	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T78,*T80,*T84	Yes	T78,T80,T84	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T78,T80,T84	Yes	T78,T80,T84	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T217,*T218,*T219	Yes	T217,T218,T219	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T217,T52,T218	Yes	T217,T52,T218	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T4,T368,T52	Yes	T4,T368,T52	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T4,T86,T87	Yes	T4,T86,T87	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T4,T86,T87	Yes	T4,T86,T87	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T4,T368,T52	Yes	T4,T368,T52	OUTPUT
cio_rx_i	Yes	Yes	T1,T217,T218	Yes	T1,T217,T15	INPUT
cio_tx_o	Yes	Yes	T217,T218,T219	Yes	T217,T218,T219	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T217,T218,T219	Yes	T217,T218,T219	OUTPUT
intr_tx_empty_o	Yes	Yes	T217,T218,T219	Yes	T217,T218,T219	OUTPUT
intr_rx_watermark_o	Yes	Yes	T217,T218,T219	Yes	T217,T218,T219	OUTPUT
intr_tx_done_o	Yes	Yes	T217,T218,T219	Yes	T217,T218,T219	OUTPUT
intr_rx_overflow_o	Yes	Yes	T217,T218,T219	Yes	T217,T218,T219	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T328,T339,T340	Yes	T328,T339,T340	OUTPUT
intr_rx_break_err_o	Yes	Yes	T328,T339,T340	Yes	T328,T339,T340	OUTPUT
intr_rx_timeout_o	Yes	Yes	T328,T339,T340	Yes	T328,T339,T340	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T328,T339,T340	Yes	T328,T339,T340	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T141,T142,T328	Yes	T141,T142,T328	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T141,T142,T328	Yes	T141,T142,T328	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T68,*T69,*T81	Yes	T68,T69,T81	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T57,T82,T83	Yes	T57,T82,T83	INPUT
tl_i.a_valid	Yes	Yes	T52,T141,T142	Yes	T52,T141,T142	INPUT
tl_o.a_ready	Yes	Yes	T52,T141,T142	Yes	T52,T141,T142	OUTPUT
tl_o.d_error	Yes	Yes	T78,T80,T84	Yes	T78,T80,T84	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T141,T142,T328	Yes	T141,T142,T328	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T141,T142,T328	Yes	T52,T141,T142	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T141,T142,T328	Yes	T52,T141,T142	OUTPUT
tl_o.d_sink	Yes	Yes	T78,T80,T84	Yes	T78,T80,T84	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T78,*T80,*T84	Yes	T78,T80,T84	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T78,T80,T84	Yes	T78,T80,T84	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T141,*T142,*T328	Yes	T141,T142,T328	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T52,T141,T142	Yes	T52,T141,T142	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T4,T701,T52	Yes	T4,T701,T52	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T4,T86,T87	Yes	T4,T86,T87	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T4,T86,T87	Yes	T4,T86,T87	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T4,T701,T52	Yes	T4,T701,T52	OUTPUT
cio_rx_i	Yes	Yes	T141,T142,T311	Yes	T141,T142,T311	INPUT
cio_tx_o	Yes	Yes	T141,T142,T311	Yes	T141,T142,T311	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T141,T142,T328	Yes	T141,T142,T328	OUTPUT
intr_tx_empty_o	Yes	Yes	T141,T142,T328	Yes	T141,T142,T328	OUTPUT
intr_rx_watermark_o	Yes	Yes	T141,T142,T328	Yes	T141,T142,T328	OUTPUT
intr_tx_done_o	Yes	Yes	T141,T142,T328	Yes	T141,T142,T328	OUTPUT
intr_rx_overflow_o	Yes	Yes	T141,T142,T328	Yes	T141,T142,T328	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T328,T339,T340	Yes	T328,T339,T340	OUTPUT
intr_rx_break_err_o	Yes	Yes	T328,T339,T340	Yes	T328,T339,T340	OUTPUT
intr_rx_timeout_o	Yes	Yes	T328,T339,T340	Yes	T328,T339,T340	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T328,T339,T340	Yes	T328,T339,T340	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T17,T18,T328	Yes	T17,T18,T328	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T17,T18,T328	Yes	T17,T18,T328	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T68,*T69,*T81	Yes	T68,T69,T81	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T57,T82,T83	Yes	T57,T82,T83	INPUT
tl_i.a_valid	Yes	Yes	T17,T18,T52	Yes	T17,T18,T52	INPUT
tl_o.a_ready	Yes	Yes	T17,T18,T52	Yes	T17,T18,T52	OUTPUT
tl_o.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T17,T18,T328	Yes	T17,T18,T328	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T17,T18,T328	Yes	T17,T18,T52	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T17,T18,T328	Yes	T17,T18,T52	OUTPUT
tl_o.d_sink	Yes	Yes	T78,T80,T84	Yes	T78,T80,T84	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T78,*T84,*T214	Yes	T78,T79,T80	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T78,T80,T84	Yes	T78,T79,T80	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T17,*T18,*T328	Yes	T17,T18,T328	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T17,T18,T52	Yes	T17,T18,T52	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T4,T52,T374	Yes	T4,T52,T374	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T4,T86,T87	Yes	T4,T86,T87	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T4,T86,T87	Yes	T4,T86,T87	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T4,T52,T374	Yes	T4,T52,T374	OUTPUT
cio_rx_i	Yes	Yes	T17,T18,T352	Yes	T17,T18,T352	INPUT
cio_tx_o	Yes	Yes	T17,T18,T352	Yes	T17,T18,T352	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T17,T18,T328	Yes	T17,T18,T328	OUTPUT
intr_tx_empty_o	Yes	Yes	T17,T18,T328	Yes	T17,T18,T328	OUTPUT
intr_rx_watermark_o	Yes	Yes	T17,T18,T328	Yes	T17,T18,T328	OUTPUT
intr_tx_done_o	Yes	Yes	T17,T18,T328	Yes	T17,T18,T328	OUTPUT
intr_rx_overflow_o	Yes	Yes	T17,T18,T328	Yes	T17,T18,T328	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T328,T339,T340	Yes	T328,T339,T340	OUTPUT
intr_rx_break_err_o	Yes	Yes	T328,T339,T340	Yes	T328,T339,T340	OUTPUT
intr_rx_timeout_o	Yes	Yes	T328,T339,T340	Yes	T328,T339,T340	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T328,T339,T340	Yes	T328,T339,T340	OUTPUT

*Tests covering at least one bit in the range