Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T3,T4,T6	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T3,T4,T6	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T3,T4,T6	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T3,T4,T6	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T3,T4,T6	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T78,T80,T84	Yes	T78,T79,T80	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T78,T84,T258	Yes	T78,T84,T258	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T35,T9,T68	Yes	T35,T9,T68	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T35,T9,T68	Yes	T35,T9,T68	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T57,T82,T83	Yes	T57,T82,T83	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T204,T78,T79	Yes	T204,T78,T84	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T204,T78,T79	Yes	T204,T78,T79	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T35,T36,T9	Yes	T35,T36,T9	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T3,T4,T6	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T68,T69,T81	Yes	T68,T69,T81	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T3,T4,T6	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T3,T4,T6	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T68,T69,T81	Yes	T68,T69,T81	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T3,T4,T6	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T68,T69,T81	Yes	T68,T69,T81	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T3,T4,T6	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T68,T69,T81	Yes	T68,T69,T81	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T69,T225,T320	Yes	T69,T225,T320	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T68,T69,T81	Yes	T68,T69,T81	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T68,*T69,*T81	Yes	T68,T69,T81	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T68,T69,T81	Yes	T68,T69,T81	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T3,T4,T6	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T57,T78,T79	Yes	T57,T78,T79	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T57,T78,T79	Yes	T57,T78,T79	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T57,T78,T79	Yes	T57,T78,T79	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T57,T78,T79	Yes	T57,T78,T79	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T57,T78,T79	Yes	T57,T78,T79	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	*T57,T78,T79	Yes	T57,T78,T79	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T57,T78,T79	Yes	T57,T78,T79	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T57,T78,T80	Yes	T57,T78,T79	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T80,T84	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T57,T78,T79	Yes	T57,T78,T79	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T57,T78,T79	Yes	T57,T78,T79	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T57,T78,T79	Yes	T57,T78,T79	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	*T57,T78,T80	Yes	T57,T78,T79	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T57,*T78,*T79	Yes	T57,T78,T79	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T57,T78,T79	Yes	T57,T78,T79	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T3,T4,T6	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T68,T69,T81	Yes	T68,T69,T81	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T68,T69,T81	Yes	T68,T69,T81	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T68,T69,T81	Yes	T68,T69,T81	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T68,T69,T81	Yes	T68,T69,T81	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T68,T69,T81	Yes	T68,T69,T81	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T68,*T69,*T81	Yes	T68,T69,T81	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T68,T69,T81	Yes	T68,T69,T81	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T3,T4,T6	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T68,T69,T81	Yes	T68,T69,T81	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T68,T69,T81	Yes	T68,T69,T81	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T3,T4,T6	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T68,*T69,*T81	Yes	T68,T69,T81	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T3,T4,T6	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T68,T69,T81	Yes	T68,T69,T81	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T3,T4,T6	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T52,T53,T57	Yes	T52,T53,T57	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T52,T283,T406	Yes	T52,T283,T406	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T52,T283,T406	Yes	T52,T283,T406	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T52,T53,T57	Yes	T52,T53,T57	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T52,T283,T406	Yes	T52,T283,T406	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T57,T78,*T79	Yes	T57,T78,T79	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T78,T80,T84	Yes	T78,T80,T84	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T52,T283,T406	Yes	T52,T283,T406	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T52,T283,T406	Yes	T52,T283,T406	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T283,T406,T284	Yes	T283,T406,T284	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T57,T78,T79	Yes	T52,T53,T57	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T283,T406,T284	Yes	T52,T283,T406	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	*T57,T78,T84	Yes	T57,T78,T79	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T283,*T284,*T57	Yes	T283,T406,T284	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T52,T283,T406	Yes	T52,T283,T406	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T68,*T69,*T81	Yes	T68,T69,T81	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T57,T82,T83	Yes	T57,T82,T83	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T372,T368,T700	Yes	T372,T368,T700	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T68,*T69,*T81	Yes	T68,T69,T81	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T106,T13,T196	Yes	T106,T13,T196	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T106,T13,T14	Yes	T106,T13,T14	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T106,T13,T196	Yes	T106,T13,T196	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T106,T13,T196	Yes	T106,T13,T196	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T106,T13,T14	Yes	T106,T13,T14	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T106,T13,T196	Yes	T106,T13,T196	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T198,T199,T200	Yes	T198,T199,T200	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T106,T13,T196	Yes	T106,T13,T196	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T106,T13,T196	Yes	T106,T13,T196	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T78,T80,T84	Yes	T78,T80,T84	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T106,T13,T14	Yes	T106,T13,T14	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T106,T13,T196	Yes	T106,T13,T196	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T106,T13,T14	Yes	T106,T13,T14	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T78,T84,T214	Yes	T78,T84,T214	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T78,*T84,*T214	Yes	T78,T80,T84	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T78,T80,T84	Yes	T78,T84,T214	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T106,*T13,*T196	Yes	T106,T13,T196	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T106,T13,T196	Yes	T106,T13,T196	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T1,T106,T196	Yes	T1,T106,T196	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T1,T106,T395	Yes	T1,T106,T395	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T106,T196	Yes	T1,T106,T196	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T106,T196	Yes	T1,T106,T196	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T1,T106,T395	Yes	T1,T106,T395	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T1,T106,T196	Yes	T1,T106,T196	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T1,T106,T196	Yes	T1,T106,T196	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T1,T106,T196	Yes	T1,T106,T196	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T78,T80,T214	Yes	T78,T214,T258	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T1,T106,T395	Yes	T1,T106,T395	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T106,T196	Yes	T1,T106,T196	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T1,T106,T395	Yes	T1,T106,T395	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T78,*T80,*T84	Yes	T78,T79,T80	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T1,*T106,*T196	Yes	T1,T106,T196	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T1,T106,T196	Yes	T1,T106,T196	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T19,T20,T106	Yes	T19,T20,T106	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T19,T20,T106	Yes	T19,T20,T106	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T19,T20,T106	Yes	T19,T20,T106	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T19,T20,T106	Yes	T19,T20,T106	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T19,T20,T106	Yes	T19,T20,T106	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T19,T20,T106	Yes	T19,T20,T106	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T19,T20,T106	Yes	T19,T20,T106	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T19,T20,T106	Yes	T19,T20,T106	INPUT
tl_usbdev_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T19,T106,T196	Yes	T19,T106,T196	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T19,T106,T196	Yes	T19,T106,T196	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T19,T20,T106	Yes	T19,T106,T196	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T78,*T80,*T84	Yes	T78,T79,T80	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T78,T80,T84	Yes	T78,T79,T80	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T19,*T20,*T106	Yes	T19,T106,T196	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T19,T20,T106	Yes	T19,T20,T106	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T205,*T78,*T79	Yes	T205,T78,T79	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T3,T4,T6	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T2,T3,T47	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T205,*T78,*T79	Yes	T205,T78,T79	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T3,T4,T6	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T205,T78,T79	Yes	T205,T78,T79	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T205,T78,T79	Yes	T205,T78,T79	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T205,T78,T79	Yes	T205,T78,T79	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T205,T78,T79	Yes	T205,T78,T79	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T205,T78,T79	Yes	T205,T78,T79	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T205,T78,*T79	Yes	T205,T78,T79	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T78,T80,T84	Yes	T78,T80,T84	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T205,T78,T79	Yes	T205,T78,T79	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T205,T78,T80	Yes	T205,T78,T79	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T84	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T205,T78,T79	Yes	T205,T78,T79	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T205,T78,T79	Yes	T205,T78,T79	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T205,T78,T79	Yes	T205,T78,T79	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T205,T78,T79	Yes	T205,T78,T79	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T78,T79,T84	Yes	T78,T79,T80	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T205,*T78,*T79	Yes	T205,T78,T79	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T205,T78,T79	Yes	T205,T78,T79	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T3,T4,T6	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_hmac_o.d_ready	Yes	Yes	T2,T3,T47	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T205,*T78,*T79	Yes	T205,T78,T79	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T116,T107,T109	Yes	T116,T107,T109	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	INPUT
tl_hmac_i.d_error	Yes	Yes	T78,T80,T84	Yes	T78,T80,T84	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	INPUT
tl_hmac_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T205,*T78,*T84	Yes	T205,T78,T79	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T2,*T47,*T48	Yes	T2,T47,T48	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	INPUT
tl_kmac_o.d_ready	Yes	Yes	T3,T4,T6	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T3,T88,T114	Yes	T3,T88,T114	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T3,T88,T114	Yes	T3,T88,T114	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T3,T88,T114	Yes	T3,T88,T114	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T3,T88,T114	Yes	T3,T88,T114	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T3,T88,T114	Yes	T3,T88,T114	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T205,*T51,*T78	Yes	T205,T51,T78	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T88,T441,T228	Yes	T88,T441,T228	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T3,T88,T114	Yes	T3,T88,T114	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T3,T88,T114	Yes	T3,T88,T114	INPUT
tl_kmac_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T80,T84	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T3,T88,T114	Yes	T3,T88,T114	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T88,T114	Yes	T3,T88,T114	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T3,T88,T114	Yes	T3,T88,T441	INPUT
tl_kmac_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T205,*T51,*T78	Yes	T205,T51,T78	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T3,*T88,*T114	Yes	T88,T441,T120	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T3,T88,T114	Yes	T3,T88,T114	INPUT
tl_aes_o.d_ready	Yes	Yes	T3,T4,T6	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T97,T690,T325	Yes	T97,T690,T325	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T97,T690,T325	Yes	T97,T690,T325	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T121,T97,T691	Yes	T121,T97,T691	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T97,T690,T325	Yes	T97,T690,T325	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T121,T97,T691	Yes	T121,T97,T691	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T78,T80,T84	Yes	T78,T80,T84	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T121,T97,T691	Yes	T121,T97,T691	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T121,T97,T692	Yes	T121,T97,T692	INPUT
tl_aes_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T121,T97,T692	Yes	T121,T97,T692	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T121,T97,T690	Yes	T121,T97,T690	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T121,T97,T692	Yes	T121,T97,T692	INPUT
tl_aes_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T78,*T79,*T84	Yes	T78,T79,T80	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T121,*T97,*T692	Yes	T121,T97,T692	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T121,T97,T692	Yes	T121,T97,T692	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T205,*T78,*T79	Yes	T205,T78,T79	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T78,T80,T84	Yes	T78,T80,T84	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T6,T121,T114	Yes	T6,T121,T114	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T47	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T2,T3,T47	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T78,T79,T84	Yes	T78,T79,T80	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T205,*T78,*T84	Yes	T205,T78,T84	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T6,*T121,*T9	Yes	T2,T47,T6	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T6,T121,T114	Yes	T6,T121,T114	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T205,*T78,*T79	Yes	T205,T78,T79	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T78,T80,T84	Yes	T78,T80,T84	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T6,T121,T114	Yes	T6,T121,T114	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T4,T6	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T3,T4,T6	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T205,*T78,*T79	Yes	T205,T78,T79	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T6,*T121,*T114	Yes	T6,T121,T114	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T6,T121,T114	Yes	T6,T121,T114	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T6,T121,T114	Yes	T6,T121,T114	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T205,*T78,*T79	Yes	T205,T78,T79	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T78,T80,T84	Yes	T78,T80,T84	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T78,T84,T214	Yes	T78,T84,T214	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	Yes	Yes	T78,T79,T84	Yes	T78,T84,T214	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T6,T121,T114	Yes	T6,T121,T114	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T4,T6	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T3,T4,T6	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	Yes	Yes	T78,T84,T214	Yes	T78,T79,T80	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T205,*T78,*T84	Yes	T205,T78,T79	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T78,T80,T84	Yes	T78,T80,T84	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T6,*T121,*T114	Yes	T6,T121,T114	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T3,T4,T6	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T6,T121,T114	Yes	T6,T121,T114	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T6,T121,T114	Yes	T6,T121,T114	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T6,T121,T114	Yes	T6,T121,T114	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T6,T121,T114	Yes	T6,T121,T114	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T6,T121,T114	Yes	T6,T121,T114	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T205,*T78,*T79	Yes	T205,T78,T79	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T6,T121,T114	Yes	T6,T121,T114	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T6,T121,T114	Yes	T6,T121,T114	INPUT
tl_edn1_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T6,T121,T114	Yes	T6,T121,T114	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T121,T114	Yes	T6,T121,T114	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T6,T121,T114	Yes	T6,T121,T114	INPUT
tl_edn1_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T205,*T78,*T84	Yes	T205,T78,T79	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T78,T79,T84	Yes	T78,T79,T80	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T6,*T121,*T114	Yes	T6,T121,T114	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T6,T121,T114	Yes	T6,T121,T114	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T78,*T79,*T80	Yes	T78,T79,T80	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T78,*T84,*T214	Yes	T78,T79,T80	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T78,T80,T84	Yes	T78,T79,T80	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otbn_o.d_ready	Yes	Yes	T2,T3,T47	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T82,*T83,*T204	Yes	T82,T83,T204	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	INPUT
tl_otbn_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	INPUT
tl_otbn_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T82,*T83,*T204	Yes	T82,T83,T204	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T2,*T47,*T48	Yes	T2,T47,T48	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T2,T3,T47	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T47	Yes	T2,T3,T47	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T47	Yes	T2,T3,T47	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T47	Yes	T2,T3,T47	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T2,T3,T47	Yes	T2,T3,T47	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T2,T3,T47	Yes	T2,T3,T47	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T205,*T78,*T79	Yes	T205,T78,T79	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T2,T3,T47	Yes	T2,T3,T47	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T2,T3,T47	Yes	T2,T3,T47	INPUT
tl_keymgr_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T49	Yes	T2,T3,T49	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T47	Yes	T2,T3,T47	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T2,T3,T47	Yes	T2,T3,T47	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T78,T80,T84	Yes	T78,T79,T80	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T205,*T78,*T84	Yes	T205,T78,T79	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T78,T80,T84	Yes	T78,T79,T80	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T47	Yes	T2,T3,T47	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T2,T3,T47	Yes	T2,T3,T47	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T69,*T264,*T57	Yes	T69,T264,T57	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T57,T78,T80	Yes	T57,T78,T84	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T47	Yes	T1,T2,T47	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T1,T2,T47	Yes	T1,T2,T47	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T57,*T78,*T80	Yes	T69,T264,T57	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T2,T3,T47	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T320,*T438,*T78	Yes	T320,T438,T78	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T180,T181,T182	Yes	T180,T181,T182	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T9,T45,T177	Yes	T2,T47,T48	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T9,T45,T177	Yes	T2,T47,T48	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T78,*T84,*T214	Yes	T320,T438,T78	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T177,*T180,*T181	Yes	T177,T180,T181	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T2,T47,T48	Yes	T2,T47,T48	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T3,T4,T6	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T78,T79,T80	Yes	T78,T79,T80	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range