Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3600136	1			T77	42		T78	591		T79	446
values[2]	716530	1			T77	34		T79	44		T84	53
values[3]	97809	1			T77	2		T79	2		T84	2
values[4]	52581	1			T254	52		T547	205		T490	168
values[5]	35237	1			T254	46		T547	213		T490	98
values[6]	26712	1			T254	43		T547	199		T490	41
values[7]	21243	1			T254	39		T547	156		T490	23
values[8]	17879	1			T254	32		T547	93		T490	15
values[9]	16132	1			T254	16		T547	70		T490	9
values[10]	14693	1			T254	16		T547	78		T490	18
values[11]	13787	1			T254	23		T547	58		T490	15
values[12]	13184	1			T254	23		T547	46		T490	17
values[13]	12079	1			T254	34		T547	40		T490	11
values[14]	11674	1			T254	26		T547	53		T490	16
values[15]	11199	1			T254	28		T547	32		T490	19
values[16]	10730	1			T254	27		T547	14		T490	38
values[17]	10398	1			T254	41		T547	13		T490	13
values[18]	9975	1			T254	36		T547	10		T490	16
values[19]	9508	1			T254	26		T547	15		T490	11
values[20]	9342	1			T254	27		T547	9		T490	16
values[21]	8782	1			T254	18		T547	20		T490	12
values[22]	8665	1			T254	10		T547	16		T490	3
values[23]	8252	1			T254	13		T547	18		T490	10
values[24]	8306	1			T254	11		T547	7		T490	10
values[25]	8121	1			T254	20		T547	13		T490	7
values[26]	7810	1			T254	12		T547	16		T490	11
values[27]	7473	1			T254	10		T547	18		T490	9
values[28]	7099	1			T254	15		T547	10		T490	13
values[29]	6673	1			T254	18		T547	11		T490	10
values[30]	6295	1			T254	22		T547	13		T490	6
values[31]	5858	1			T254	25		T547	10		T490	6
values[32]	5267	1			T254	14		T547	9		T490	13
values[33]	4893	1			T254	7		T547	7		T490	8
values[34]	4535	1			T254	18		T547	7		T490	5
values[35]	4332	1			T254	26		T547	5		T490	9
values[36]	4115	1			T254	25		T547	10		T490	7
values[37]	3884	1			T254	12		T547	16		T490	9
values[38]	3723	1			T254	9		T547	15		T490	8
values[39]	3547	1			T254	12		T547	22		T490	13
values[40]	3458	1			T254	4		T547	24		T490	8
values[41]	3424	1			T254	4		T547	23		T490	17
values[42]	3199	1			T254	1		T547	16		T490	6
values[43]	3189	1			T254	5		T547	11		T490	6
values[44]	3127	1			T254	1		T547	14		T490	8
values[45]	3105	1			T254	1		T547	12		T490	4
values[46]	3075	1			T254	1		T547	8		T490	5
values[47]	2922	1			T254	3		T547	14		T490	3
values[48]	2888	1			T254	3		T547	16		T490	3
values[49]	2893	1			T254	8		T547	10		T490	5
values[50]	2812	1			T254	2		T547	9		T490	3
values[51]	2789	1			T254	4		T547	9		T490	6
values[52]	2761	1			T254	2		T547	13		T490	6
values[53]	2679	1			T254	3		T547	12		T490	10
values[54]	2616	1			T254	1		T547	12		T490	9
values[55]	2539	1			T254	1		T547	18		T490	4
values[56]	2460	1			T254	3		T547	8		T490	7
values[57]	2402	1			T254	1		T547	5		T490	7
values[58]	2379	1			T547	4		T490	3		T555	10
values[59]	2383	1			T547	9		T490	6		T555	10
values[60]	2427	1			T547	6		T490	5		T555	10
values[61]	2620	1			T547	4		T490	9		T555	10
values[62]	3767	1			T547	3		T490	13		T555	10
values[63]	9463	1			T547	5		T490	34		T555	10
values[64]	242329	1			T547	67		T490	56		T555	1835

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4612055	1			T77	97		T78	594		T79	968
values[2]	784557	1			T77	33		T79	131		T84	41
values[3]	81439	1			T77	14		T79	22		T84	2
values[4]	14272	1			T77	5		T254	1		T553	2
values[5]	5277	1			T77	1		T553	1		T490	22
values[6]	3093	1			T77	2		T490	13		T555	6
values[7]	2294	1			T490	19		T555	4		T767	4
values[8]	1856	1			T490	6		T555	2		T767	1
values[9]	1650	1			T490	4		T555	2		T767	1
values[10]	1494	1			T490	5		T555	2		T767	1
values[11]	1355	1			T490	9		T555	2		T767	1
values[12]	1274	1			T490	8		T555	2		T767	1
values[13]	1200	1			T555	2		T767	1		T844	10
values[14]	1060	1			T555	2		T767	1		T844	7
values[15]	970	1			T555	2		T767	1		T844	4
values[16]	931	1			T555	2		T767	1		T844	1
values[17]	872	1			T555	2		T767	1		T844	5
values[18]	880	1			T555	2		T767	1		T844	10
values[19]	768	1			T555	2		T767	1		T844	5
values[20]	774	1			T555	2		T767	1		T844	5
values[21]	799	1			T555	2		T767	1		T844	6
values[22]	695	1			T555	2		T767	1		T844	4
values[23]	673	1			T555	2		T767	1		T844	5
values[24]	668	1			T555	2		T767	1		T844	1
values[25]	667	1			T555	2		T767	1		T844	1
values[26]	611	1			T555	2		T767	1		T844	1
values[27]	582	1			T555	2		T767	1		T844	2
values[28]	529	1			T555	2		T767	1		T844	1
values[29]	534	1			T555	2		T767	1		T844	1
values[30]	553	1			T555	2		T767	1		T844	3
values[31]	557	1			T555	2		T767	1		T844	1
values[32]	519	1			T555	2		T767	1		T844	1
values[33]	479	1			T555	2		T767	1		T475	1
values[34]	445	1			T555	2		T767	1		T475	7
values[35]	437	1			T555	2		T767	1		T475	2
values[36]	446	1			T555	2		T767	1		T475	3
values[37]	428	1			T555	3		T767	1		T475	1
values[38]	420	1			T555	2		T767	1		T475	1
values[39]	411	1			T555	2		T767	1		T475	1
values[40]	381	1			T555	2		T767	1		T475	4
values[41]	412	1			T555	2		T767	1		T475	2
values[42]	393	1			T555	2		T767	1		T475	2
values[43]	359	1			T555	2		T767	1		T475	2
values[44]	364	1			T555	2		T767	1		T475	1
values[45]	351	1			T555	2		T767	1		T475	2
values[46]	385	1			T555	2		T767	1		T475	1
values[47]	367	1			T555	2		T767	1		T475	4
values[48]	383	1			T555	2		T767	1		T475	4
values[49]	348	1			T555	2		T767	1		T475	1
values[50]	354	1			T555	2		T767	1		T475	2
values[51]	334	1			T555	2		T767	1		T475	1
values[52]	335	1			T555	2		T767	1		T475	1
values[53]	370	1			T555	3		T767	1		T475	3
values[54]	343	1			T555	2		T767	1		T475	1
values[55]	333	1			T555	2		T767	1		T475	2
values[56]	346	1			T555	2		T767	1		T475	2
values[57]	358	1			T555	3		T767	1		T475	1
values[58]	362	1			T555	2		T767	1		T475	1
values[59]	343	1			T555	2		T767	1		T475	1
values[60]	358	1			T555	2		T767	1		T475	2
values[61]	403	1			T555	2		T767	1		T475	1
values[62]	551	1			T555	2		T767	1		T475	2
values[63]	2031	1			T555	2		T767	2		T475	42
values[64]	27014	1			T555	324		T767	214		T475	138

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	527219	1			T77	1		T78	614		T79	97
values[2]	2573567	1			T77	60		T79	159		T84	254
values[3]	1146252	1			T77	31		T79	191		T84	61
values[4]	138548	1			T77	1		T84	1		T123	3
values[5]	70305	1			T254	28		T553	3		T547	241
values[6]	45524	1			T254	21		T547	161		T490	158
values[7]	33948	1			T254	21		T547	136		T490	105
values[8]	27120	1			T254	38		T547	107		T490	77
values[9]	22806	1			T254	19		T547	77		T490	63
values[10]	20147	1			T254	16		T547	80		T490	81
values[11]	17788	1			T254	21		T547	84		T490	78
values[12]	16505	1			T254	25		T547	87		T490	76
values[13]	15248	1			T254	27		T547	73		T490	65
values[14]	14369	1			T254	41		T547	84		T490	33
values[15]	13924	1			T254	18		T547	76		T490	32
values[16]	13417	1			T254	13		T547	68		T490	44
values[17]	12664	1			T254	9		T547	44		T490	23
values[18]	12372	1			T254	18		T547	58		T490	26
values[19]	11919	1			T254	20		T547	27		T490	32
values[20]	11139	1			T254	14		T547	26		T490	32
values[21]	10765	1			T254	33		T547	28		T490	31
values[22]	10582	1			T254	26		T547	19		T490	30
values[23]	10111	1			T254	10		T547	18		T490	29
values[24]	9926	1			T254	27		T547	14		T490	24
values[25]	9152	1			T254	48		T547	14		T490	20
values[26]	8683	1			T254	41		T547	6		T490	30
values[27]	8637	1			T254	33		T547	7		T490	33
values[28]	8087	1			T254	21		T547	11		T490	23
values[29]	7370	1			T254	15		T547	9		T490	15
values[30]	6983	1			T254	28		T547	15		T490	31
values[31]	6571	1			T254	21		T547	13		T490	20
values[32]	6055	1			T254	17		T547	15		T490	29
values[33]	5719	1			T254	11		T547	16		T490	25
values[34]	5319	1			T254	12		T547	15		T490	24
values[35]	4950	1			T254	6		T547	23		T490	23
values[36]	4648	1			T254	2		T547	8		T490	24
values[37]	4390	1			T254	1		T547	12		T490	9
values[38]	4219	1			T254	2		T547	13		T490	18
values[39]	3941	1			T254	1		T547	7		T490	15
values[40]	3818	1			T254	1		T547	9		T490	11
values[41]	3734	1			T254	2		T547	8		T490	7
values[42]	3611	1			T254	1		T547	13		T490	8
values[43]	3455	1			T254	1		T547	6		T490	5
values[44]	3463	1			T254	3		T547	6		T490	5
values[45]	3405	1			T254	1		T547	16		T490	4
values[46]	3351	1			T547	29		T490	5		T556	8
values[47]	3257	1			T547	13		T490	3		T556	14
values[48]	3183	1			T547	13		T490	5		T556	10
values[49]	3295	1			T547	22		T490	4		T556	4
values[50]	3078	1			T547	14		T490	13		T556	2
values[51]	3192	1			T547	7		T490	7		T556	6
values[52]	3193	1			T547	8		T490	5		T556	5
values[53]	3169	1			T547	9		T490	7		T556	12
values[54]	3113	1			T547	11		T490	6		T556	3
values[55]	3139	1			T547	8		T490	7		T556	8
values[56]	2954	1			T547	6		T490	7		T556	4
values[57]	2838	1			T547	6		T490	5		T556	1
values[58]	2765	1			T547	12		T490	11		T556	3
values[59]	2737	1			T547	12		T490	9		T556	3
values[60]	2781	1			T547	7		T490	11		T556	5
values[61]	2771	1			T547	8		T490	7		T556	5
values[62]	3555	1			T547	10		T490	21		T556	1
values[63]	8304	1			T547	17		T490	54		T556	3
values[64]	235034	1			T547	81		T490	161		T556	10