Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1785545	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

37911617

1

T1

16487

T2

6164

T3

86454

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	27612302	1			T1	7717		T2	2714		T3	74384
values[0x0]	10628342	1			T1	8770		T2	3450		T3	12070
values[0x1]	1456518	1			T1	1374		T2	469		T3	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	512819	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

39184343

1

T1

17861

T2

6633

T3

86461

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18905698	1			T1	8931		T2	3317		T3	43231
valid_sources[0x01]	18904203	1			T1	8930		T2	3316		T3	43230
valid_sources[0x02]	30288	1			T139	143		T140	356		T549	12
valid_sources[0x03]	30713	1			T82	1		T139	126		T140	363
valid_sources[0x04]	30176	1			T204	39		T139	180		T140	401
valid_sources[0x05]	30534	1			T139	66		T140	431		T693	3
valid_sources[0x06]	30115	1			T139	123		T140	409		T913	5
valid_sources[0x07]	30171	1			T82	3		T139	118		T140	435
valid_sources[0x08]	30910	1			T203	4		T139	113		T140	362
valid_sources[0x09]	29990	1			T82	4		T139	96		T140	455
valid_sources[0x0a]	30327	1			T82	1		T83	3		T203	5
valid_sources[0x0b]	30389	1			T82	7		T139	131		T140	386
valid_sources[0x0c]	30072	1			T139	145		T140	396		T549	12
valid_sources[0x0d]	31178	1			T139	131		T140	438		T693	3
valid_sources[0x0e]	29762	1			T139	92		T140	378		T549	27
valid_sources[0x0f]	30313	1			T139	148		T140	391		T549	27
valid_sources[0x10]	34275	1			T139	141		T140	437		T549	14
valid_sources[0x11]	30442	1			T139	148		T140	455		T549	12
valid_sources[0x12]	30598	1			T139	91		T140	408		T549	2
valid_sources[0x13]	29859	1			T139	150		T140	439		T549	9
valid_sources[0x14]	30023	1			T203	6		T139	100		T140	420
valid_sources[0x15]	30942	1			T82	2		T139	126		T140	374
valid_sources[0x16]	30674	1			T82	3		T203	1		T139	110
valid_sources[0x17]	29970	1			T82	3		T139	112		T140	377
valid_sources[0x18]	30473	1			T139	116		T140	463		T549	21
valid_sources[0x19]	30693	1			T139	102		T140	420		T549	3
valid_sources[0x1a]	29834	1			T82	5		T139	164		T140	373
valid_sources[0x1b]	30811	1			T139	108		T140	351		T549	48
valid_sources[0x1c]	30218	1			T83	14		T139	126		T140	410
valid_sources[0x1d]	29311	1			T83	1		T139	71		T140	425
valid_sources[0x1e]	30576	1			T203	7		T139	121		T140	435
valid_sources[0x1f]	30061	1			T139	118		T140	368		T549	14
valid_sources[0x20]	30632	1			T203	1		T139	92		T140	387

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27104198

1

T1

7717

T2

2714

T3

74384

values[0x0]

all_enables

biggest_size

10566596

1

T1

8770

T2

3450

T3

12070

values[0x1]

all_enables

biggest_size

240823

1

T81

17

T82

22

T83

19

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2664012	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

420990

1

T77

15

T78

85

T79

60

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1045879	1			T77	23		T78	200		T79	144
values[0x0]	994730	1			T77	30		T78	197		T79	169
values[0x1]	1044393	1			T77	25		T78	194		T79	175

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2062892	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1022110

1

T77

28

T78

182

T79

134

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	47356	1			T77	5		T79	2		T123	2
valid_sources[0x01]	48030	1			T79	8		T123	5		T447	2
valid_sources[0x02]	47349	1			T77	1		T78	9		T79	4
valid_sources[0x03]	47415	1			T79	4		T84	1		T123	6
valid_sources[0x04]	48744	1			T77	1		T79	2		T84	8
valid_sources[0x05]	47610	1			T79	5		T84	6		T447	7
valid_sources[0x06]	48103	1			T77	3		T79	7		T84	11
valid_sources[0x07]	47855	1			T77	1		T78	7		T79	5
valid_sources[0x08]	49115	1			T77	1		T78	16		T123	9
valid_sources[0x09]	47659	1			T77	1		T79	6		T266	6
valid_sources[0x0a]	48386	1			T77	1		T78	5		T79	17
valid_sources[0x0b]	47425	1			T78	25		T79	4		T447	1
valid_sources[0x0c]	47770	1			T77	1		T78	13		T79	6
valid_sources[0x0d]	48269	1			T77	2		T79	6		T266	1
valid_sources[0x0e]	48597	1			T77	1		T78	12		T79	7
valid_sources[0x0f]	48540	1			T77	3		T78	8		T79	7
valid_sources[0x10]	47466	1			T77	1		T79	7		T266	1
valid_sources[0x11]	47052	1			T77	1		T79	13		T84	7
valid_sources[0x12]	48090	1			T78	28		T266	2		T447	2
valid_sources[0x13]	48400	1			T77	2		T78	19		T79	4
valid_sources[0x14]	48938	1			T78	20		T79	3		T84	2
valid_sources[0x15]	48713	1			T79	2		T123	3		T254	18
valid_sources[0x16]	48021	1			T77	1		T78	30		T79	8
valid_sources[0x17]	48054	1			T77	1		T79	23		T84	14
valid_sources[0x18]	47154	1			T77	1		T79	22		T84	5
valid_sources[0x19]	47246	1			T77	5		T78	5		T79	9
valid_sources[0x1a]	47281	1			T77	2		T79	12		T123	11
valid_sources[0x1b]	48149	1			T77	1		T79	26		T84	3
valid_sources[0x1c]	48447	1			T77	1		T78	20		T79	2
valid_sources[0x1d]	48388	1			T77	1		T79	5		T447	2
valid_sources[0x1e]	48749	1			T77	1		T79	4		T266	7
valid_sources[0x1f]	47078	1			T79	12		T123	2		T254	2
valid_sources[0x20]	48911	1			T77	1		T78	19		T79	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

44368

1

T77

2

T78

11

T79

7

values[0x0]

all_enables

biggest_size

332201

1

T77

13

T78

63

T79

47

values[0x1]

all_enables

biggest_size

44421

1

T78

11

T79

6

T84

5

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2835176	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

461126

1

T77

18

T78

89

T79

152

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1130095	1			T77	52		T78	213		T79	383
values[0x0]	1037406	1			T77	45		T78	196		T79	350
values[0x1]	1128801	1			T77	55		T78	185		T79	378

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2174774	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1121528

1

T77

51

T78

209

T79

350

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	50589	1			T77	1		T79	12		T84	3
valid_sources[0x01]	51667	1			T77	2		T79	17		T84	2
valid_sources[0x02]	50699	1			T77	2		T78	7		T79	21
valid_sources[0x03]	50791	1			T79	17		T84	5		T266	8
valid_sources[0x04]	51756	1			T77	1		T79	16		T84	6
valid_sources[0x05]	51617	1			T79	15		T84	6		T123	4
valid_sources[0x06]	51559	1			T77	7		T79	10		T84	3
valid_sources[0x07]	51110	1			T77	2		T78	7		T79	14
valid_sources[0x08]	52130	1			T77	1		T78	11		T79	21
valid_sources[0x09]	51769	1			T77	4		T79	19		T84	3
valid_sources[0x0a]	51154	1			T77	3		T78	5		T79	27
valid_sources[0x0b]	50957	1			T77	2		T78	16		T79	16
valid_sources[0x0c]	51344	1			T78	13		T79	16		T84	2
valid_sources[0x0d]	51443	1			T77	2		T79	16		T84	4
valid_sources[0x0e]	50762	1			T77	2		T78	9		T79	15
valid_sources[0x0f]	51589	1			T77	2		T78	6		T79	14
valid_sources[0x10]	51602	1			T77	3		T79	20		T84	2
valid_sources[0x11]	50589	1			T79	25		T84	2		T266	4
valid_sources[0x12]	51536	1			T77	7		T78	33		T79	16
valid_sources[0x13]	52005	1			T77	3		T78	15		T79	16
valid_sources[0x14]	51796	1			T78	14		T79	10		T84	7
valid_sources[0x15]	51642	1			T77	2		T79	15		T84	3
valid_sources[0x16]	51590	1			T77	3		T78	23		T79	22
valid_sources[0x17]	50802	1			T77	2		T79	11		T84	4
valid_sources[0x18]	51970	1			T77	1		T79	27		T84	5
valid_sources[0x19]	51621	1			T78	11		T79	14		T84	4
valid_sources[0x1a]	50951	1			T77	2		T79	19		T84	6
valid_sources[0x1b]	52884	1			T79	28		T84	1		T123	5
valid_sources[0x1c]	51620	1			T77	1		T78	17		T79	18
valid_sources[0x1d]	51752	1			T77	5		T79	12		T84	4
valid_sources[0x1e]	52521	1			T77	2		T79	10		T84	2
valid_sources[0x1f]	51344	1			T77	2		T79	16		T84	4
valid_sources[0x20]	52066	1			T77	3		T78	16		T79	18

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

48440

1

T77

1

T78

10

T79

11

values[0x0]

all_enables

biggest_size

364113

1

T77

17

T78

70

T79

125

values[0x1]

all_enables

biggest_size

48573

1

T78

9

T79

16

T123

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2684297	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

424051

1

T77

19

T78

93

T79

62

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1052822	1			T77	37		T78	188		T79	147
values[0x0]	1002161	1			T77	30		T78	209		T79	142
values[0x1]	1053365	1			T77	26		T78	217		T79	144

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2079875	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1028473

1

T77

34

T78

221

T79

146

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	47981	1			T79	4		T84	9		T123	5
valid_sources[0x01]	49471	1			T84	3		T123	2		T254	7
valid_sources[0x02]	47443	1			T78	16		T123	1		T266	1
valid_sources[0x03]	48629	1			T77	1		T79	4		T84	3
valid_sources[0x04]	49005	1			T79	11		T84	9		T123	1
valid_sources[0x05]	48742	1			T84	5		T254	6		T553	3
valid_sources[0x06]	47878	1			T79	5		T84	3		T254	2
valid_sources[0x07]	47630	1			T78	17		T79	1		T84	6
valid_sources[0x08]	48709	1			T77	1		T78	9		T79	9
valid_sources[0x09]	48527	1			T77	3		T79	4		T84	2
valid_sources[0x0a]	48783	1			T77	3		T78	14		T79	14
valid_sources[0x0b]	47805	1			T78	20		T79	2		T84	3
valid_sources[0x0c]	48540	1			T78	7		T79	9		T84	3
valid_sources[0x0d]	48962	1			T77	2		T79	1		T84	4
valid_sources[0x0e]	49161	1			T77	2		T78	17		T79	4
valid_sources[0x0f]	48710	1			T78	7		T79	1		T84	5
valid_sources[0x10]	48700	1			T79	8		T84	2		T123	3
valid_sources[0x11]	47877	1			T79	9		T84	2		T254	3
valid_sources[0x12]	49081	1			T77	2		T78	30		T79	9
valid_sources[0x13]	48544	1			T78	7		T79	4		T84	3
valid_sources[0x14]	48481	1			T78	8		T79	3		T84	4
valid_sources[0x15]	48350	1			T79	5		T123	6		T254	12
valid_sources[0x16]	48408	1			T77	5		T78	22		T79	5
valid_sources[0x17]	47297	1			T79	10		T84	5		T123	4
valid_sources[0x18]	48807	1			T77	4		T79	20		T84	5
valid_sources[0x19]	48627	1			T78	14		T79	1		T84	7
valid_sources[0x1a]	47505	1			T77	1		T79	17		T84	1
valid_sources[0x1b]	47953	1			T79	7		T84	4		T123	2
valid_sources[0x1c]	48035	1			T77	4		T78	13		T79	5
valid_sources[0x1d]	48769	1			T79	4		T84	9		T123	2
valid_sources[0x1e]	49069	1			T77	4		T79	8		T84	6
valid_sources[0x1f]	49238	1			T79	7		T84	2		T447	3
valid_sources[0x20]	49207	1			T77	1		T78	20		T79	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

44956

1

T77

3

T78

8

T79

3

values[0x0]

all_enables

biggest_size

334564

1

T77

13

T78

75

T79

55

values[0x1]

all_enables

biggest_size

44531

1

T77

3

T78

10

T79

4