Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	527454626	60818483	0	0
DepthKnown_A	527454626	527347469	0	0
RvalidKnown_A	527454626	527347469	0	0
WreadyKnown_A	527454626	527347469	0	0
gen_passthru_fifo.paramCheckPass	1026	1026	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527454626	60818483	0	0
T1	269122	35168	0	0
T2	123989	11913	0	0
T3	950472	114039	0	0
T4	326983	33193	0	0
T5	379344	45250	0	0
T11	460217	63294	0	0
T35	203938	48568	0	0
T63	127592	17354	0	0
T88	93420	10253	0	0
T89	460461	64939	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527454626	527347469	0	0
T1	269122	269009	0	0
T2	123989	123938	0	0
T3	950472	950421	0	0
T4	326983	326925	0	0
T5	379344	379124	0	0
T11	460217	460155	0	0
T35	203938	203821	0	0
T63	127592	127530	0	0
T88	93420	93362	0	0
T89	460461	460410	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527454626	527347469	0	0
T1	269122	269009	0	0
T2	123989	123938	0	0
T3	950472	950421	0	0
T4	326983	326925	0	0
T5	379344	379124	0	0
T11	460217	460155	0	0
T35	203938	203821	0	0
T63	127592	127530	0	0
T88	93420	93362	0	0
T89	460461	460410	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527454626	527347469	0	0
T1	269122	269009	0	0
T2	123989	123938	0	0
T3	950472	950421	0	0
T4	326983	326925	0	0
T5	379344	379124	0	0
T11	460217	460155	0	0
T35	203938	203821	0	0
T63	127592	127530	0	0
T88	93420	93362	0	0
T89	460461	460410	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1026	1026	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T35	1	1	0	0
T63	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	527454626	47236128	0	0
DepthKnown_A	527454626	527347469	0	0
RvalidKnown_A	527454626	527347469	0	0
WreadyKnown_A	527454626	527347469	0	0
gen_passthru_fifo.paramCheckPass	1026	1026	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527454626	47236128	0	0
T1	269122	25569	0	0
T2	123989	9456	0	0
T3	950472	95301	0	0
T4	326983	28602	0	0
T5	379344	35651	0	0
T11	460217	48076	0	0
T35	203938	27175	0	0
T63	127592	12168	0	0
T88	93420	8395	0	0
T89	460461	61778	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527454626	527347469	0	0
T1	269122	269009	0	0
T2	123989	123938	0	0
T3	950472	950421	0	0
T4	326983	326925	0	0
T5	379344	379124	0	0
T11	460217	460155	0	0
T35	203938	203821	0	0
T63	127592	127530	0	0
T88	93420	93362	0	0
T89	460461	460410	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527454626	527347469	0	0
T1	269122	269009	0	0
T2	123989	123938	0	0
T3	950472	950421	0	0
T4	326983	326925	0	0
T5	379344	379124	0	0
T11	460217	460155	0	0
T35	203938	203821	0	0
T63	127592	127530	0	0
T88	93420	93362	0	0
T89	460461	460410	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527454626	527347469	0	0
T1	269122	269009	0	0
T2	123989	123938	0	0
T3	950472	950421	0	0
T4	326983	326925	0	0
T5	379344	379124	0	0
T11	460217	460155	0	0
T35	203938	203821	0	0
T63	127592	127530	0	0
T88	93420	93362	0	0
T89	460461	460410	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1026	1026	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T35	1	1	0	0
T63	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	527454626	44909559	0	0
DepthKnown_A	527454626	527347469	0	0
RvalidKnown_A	527454626	527347469	0	0
WreadyKnown_A	527454626	527347469	0	0
gen_passthru_fifo.paramCheckPass	1026	1026	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527454626	44909559	0	0
T1	269122	18239	0	0
T2	123989	6785	0	0
T3	950472	164020	0	0
T4	326983	29298	0	0
T5	379344	25607	0	0
T11	460217	37507	0	0
T35	203938	18966	0	0
T63	127592	6610	0	0
T88	93420	6408	0	0
T89	460461	59079	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527454626	527347469	0	0
T1	269122	269009	0	0
T2	123989	123938	0	0
T3	950472	950421	0	0
T4	326983	326925	0	0
T5	379344	379124	0	0
T11	460217	460155	0	0
T35	203938	203821	0	0
T63	127592	127530	0	0
T88	93420	93362	0	0
T89	460461	460410	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527454626	527347469	0	0
T1	269122	269009	0	0
T2	123989	123938	0	0
T3	950472	950421	0	0
T4	326983	326925	0	0
T5	379344	379124	0	0
T11	460217	460155	0	0
T35	203938	203821	0	0
T63	127592	127530	0	0
T88	93420	93362	0	0
T89	460461	460410	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527454626	527347469	0	0
T1	269122	269009	0	0
T2	123989	123938	0	0
T3	950472	950421	0	0
T4	326983	326925	0	0
T5	379344	379124	0	0
T11	460217	460155	0	0
T35	203938	203821	0	0
T63	127592	127530	0	0
T88	93420	93362	0	0
T89	460461	460410	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1026	1026	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T35	1	1	0	0
T63	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	527454626	37853583	0	0
DepthKnown_A	527454626	527347469	0	0
RvalidKnown_A	527454626	527347469	0	0
WreadyKnown_A	527454626	527347469	0	0
gen_passthru_fifo.paramCheckPass	1026	1026	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527454626	37853583	0	0
T1	269122	17861	0	0
T2	123989	6633	0	0
T3	950472	86461	0	0
T4	326983	28984	0	0
T5	379344	25020	0	0
T11	460217	36435	0	0
T35	203938	13672	0	0
T63	127592	6333	0	0
T88	93420	6292	0	0
T89	460461	58922	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527454626	527347469	0	0
T1	269122	269009	0	0
T2	123989	123938	0	0
T3	950472	950421	0	0
T4	326983	326925	0	0
T5	379344	379124	0	0
T11	460217	460155	0	0
T35	203938	203821	0	0
T63	127592	127530	0	0
T88	93420	93362	0	0
T89	460461	460410	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527454626	527347469	0	0
T1	269122	269009	0	0
T2	123989	123938	0	0
T3	950472	950421	0	0
T4	326983	326925	0	0
T5	379344	379124	0	0
T11	460217	460155	0	0
T35	203938	203821	0	0
T63	127592	127530	0	0
T88	93420	93362	0	0
T89	460461	460410	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527454626	527347469	0	0
T1	269122	269009	0	0
T2	123989	123938	0	0
T3	950472	950421	0	0
T4	326983	326925	0	0
T5	379344	379124	0	0
T11	460217	460155	0	0
T35	203938	203821	0	0
T63	127592	127530	0	0
T88	93420	93362	0	0
T89	460461	460410	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1026	1026	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T35	1	1	0	0
T63	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	595971301	81238	0	0
DepthKnown_A	595971301	595848376	0	0
RvalidKnown_A	595971301	595848376	0	0
WreadyKnown_A	595971301	595848376	0	0
gen_passthru_fifo.paramCheckPass	2935	2935	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595971301	81238	0	0
T1	269122	151	0	0
T2	123989	21	0	0
T3	950472	34	0	0
T4	326983	23	0	0
T5	379344	72	0	0
T11	460217	21	0	0
T35	203938	26	0	0
T63	127592	26	0	0
T88	93420	13	0	0
T89	460461	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595971301	595848376	0	0
T1	269122	269009	0	0
T2	123989	123938	0	0
T3	950472	950421	0	0
T4	326983	326925	0	0
T5	379344	379124	0	0
T11	460217	460155	0	0
T35	203938	203821	0	0
T63	127592	127530	0	0
T88	93420	93362	0	0
T89	460461	460410	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595971301	595848376	0	0
T1	269122	269009	0	0
T2	123989	123938	0	0
T3	950472	950421	0	0
T4	326983	326925	0	0
T5	379344	379124	0	0
T11	460217	460155	0	0
T35	203938	203821	0	0
T63	127592	127530	0	0
T88	93420	93362	0	0
T89	460461	460410	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595971301	595848376	0	0
T1	269122	269009	0	0
T2	123989	123938	0	0
T3	950472	950421	0	0
T4	326983	326925	0	0
T5	379344	379124	0	0
T11	460217	460155	0	0
T35	203938	203821	0	0
T63	127592	127530	0	0
T88	93420	93362	0	0
T89	460461	460410	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2935	2935	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T35	1	1	0	0
T63	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	595971301	82570	0	0
DepthKnown_A	595971301	595848376	0	0
RvalidKnown_A	595971301	595848376	0	0
WreadyKnown_A	595971301	595848376	0	0
gen_passthru_fifo.paramCheckPass	2935	2935	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595971301	82570	0	0
T1	269122	151	0	0
T2	123989	21	0	0
T3	950472	34	0	0
T4	326983	23	0	0
T5	379344	72	0	0
T11	460217	21	0	0
T35	203938	26	0	0
T63	127592	26	0	0
T88	93420	13	0	0
T89	460461	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595971301	595848376	0	0
T1	269122	269009	0	0
T2	123989	123938	0	0
T3	950472	950421	0	0
T4	326983	326925	0	0
T5	379344	379124	0	0
T11	460217	460155	0	0
T35	203938	203821	0	0
T63	127592	127530	0	0
T88	93420	93362	0	0
T89	460461	460410	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595971301	595848376	0	0
T1	269122	269009	0	0
T2	123989	123938	0	0
T3	950472	950421	0	0
T4	326983	326925	0	0
T5	379344	379124	0	0
T11	460217	460155	0	0
T35	203938	203821	0	0
T63	127592	127530	0	0
T88	93420	93362	0	0
T89	460461	460410	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595971301	595848376	0	0
T1	269122	269009	0	0
T2	123989	123938	0	0
T3	950472	950421	0	0
T4	326983	326925	0	0
T5	379344	379124	0	0
T11	460217	460155	0	0
T35	203938	203821	0	0
T63	127592	127530	0	0
T88	93420	93362	0	0
T89	460461	460410	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2935	2935	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T35	1	1	0	0
T63	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	595971301	52179	0	0
DepthKnown_A	595971301	595848376	0	0
RvalidKnown_A	595971301	595848376	0	0
WreadyKnown_A	595971301	595848376	0	0
gen_passthru_fifo.paramCheckPass	2935	2935	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595971301	52179	0	0
T1	269122	95	0	0
T2	123989	20	0	0
T3	950472	5	0	0
T4	326983	20	0	0
T5	379344	68	0	0
T11	460217	20	0	0
T35	203938	24	0	0
T63	127592	23	0	0
T88	93420	12	0	0
T89	460461	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595971301	595848376	0	0
T1	269122	269009	0	0
T2	123989	123938	0	0
T3	950472	950421	0	0
T4	326983	326925	0	0
T5	379344	379124	0	0
T11	460217	460155	0	0
T35	203938	203821	0	0
T63	127592	127530	0	0
T88	93420	93362	0	0
T89	460461	460410	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595971301	595848376	0	0
T1	269122	269009	0	0
T2	123989	123938	0	0
T3	950472	950421	0	0
T4	326983	326925	0	0
T5	379344	379124	0	0
T11	460217	460155	0	0
T35	203938	203821	0	0
T63	127592	127530	0	0
T88	93420	93362	0	0
T89	460461	460410	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595971301	595848376	0	0
T1	269122	269009	0	0
T2	123989	123938	0	0
T3	950472	950421	0	0
T4	326983	326925	0	0
T5	379344	379124	0	0
T11	460217	460155	0	0
T35	203938	203821	0	0
T63	127592	127530	0	0
T88	93420	93362	0	0
T89	460461	460410	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2935	2935	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T35	1	1	0	0
T63	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	595971301	52178	0	0
DepthKnown_A	595971301	595848376	0	0
RvalidKnown_A	595971301	595848376	0	0
WreadyKnown_A	595971301	595848376	0	0
gen_passthru_fifo.paramCheckPass	2935	2935	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595971301	52178	0	0
T1	269122	95	0	0
T2	123989	20	0	0
T3	950472	5	0	0
T4	326983	20	0	0
T5	379344	68	0	0
T11	460217	20	0	0
T35	203938	24	0	0
T63	127592	23	0	0
T88	93420	12	0	0
T89	460461	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595971301	595848376	0	0
T1	269122	269009	0	0
T2	123989	123938	0	0
T3	950472	950421	0	0
T4	326983	326925	0	0
T5	379344	379124	0	0
T11	460217	460155	0	0
T35	203938	203821	0	0
T63	127592	127530	0	0
T88	93420	93362	0	0
T89	460461	460410	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595971301	595848376	0	0
T1	269122	269009	0	0
T2	123989	123938	0	0
T3	950472	950421	0	0
T4	326983	326925	0	0
T5	379344	379124	0	0
T11	460217	460155	0	0
T35	203938	203821	0	0
T63	127592	127530	0	0
T88	93420	93362	0	0
T89	460461	460410	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595971301	595848376	0	0
T1	269122	269009	0	0
T2	123989	123938	0	0
T3	950472	950421	0	0
T4	326983	326925	0	0
T5	379344	379124	0	0
T11	460217	460155	0	0
T35	203938	203821	0	0
T63	127592	127530	0	0
T88	93420	93362	0	0
T89	460461	460410	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2935	2935	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T35	1	1	0	0
T63	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	595971301	29059	0	0
DepthKnown_A	595971301	595848376	0	0
RvalidKnown_A	595971301	595848376	0	0
WreadyKnown_A	595971301	595848376	0	0
gen_passthru_fifo.paramCheckPass	2935	2935	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595971301	29059	0	0
T1	269122	56	0	0
T2	123989	1	0	0
T3	950472	29	0	0
T4	326983	3	0	0
T5	379344	4	0	0
T11	460217	1	0	0
T35	203938	2	0	0
T63	127592	3	0	0
T88	93420	1	0	0
T89	460461	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595971301	595848376	0	0
T1	269122	269009	0	0
T2	123989	123938	0	0
T3	950472	950421	0	0
T4	326983	326925	0	0
T5	379344	379124	0	0
T11	460217	460155	0	0
T35	203938	203821	0	0
T63	127592	127530	0	0
T88	93420	93362	0	0
T89	460461	460410	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595971301	595848376	0	0
T1	269122	269009	0	0
T2	123989	123938	0	0
T3	950472	950421	0	0
T4	326983	326925	0	0
T5	379344	379124	0	0
T11	460217	460155	0	0
T35	203938	203821	0	0
T63	127592	127530	0	0
T88	93420	93362	0	0
T89	460461	460410	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595971301	595848376	0	0
T1	269122	269009	0	0
T2	123989	123938	0	0
T3	950472	950421	0	0
T4	326983	326925	0	0
T5	379344	379124	0	0
T11	460217	460155	0	0
T35	203938	203821	0	0
T63	127592	127530	0	0
T88	93420	93362	0	0
T89	460461	460410	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2935	2935	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T35	1	1	0	0
T63	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	595971301	30392	0	0
DepthKnown_A	595971301	595848376	0	0
RvalidKnown_A	595971301	595848376	0	0
WreadyKnown_A	595971301	595848376	0	0
gen_passthru_fifo.paramCheckPass	2935	2935	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595971301	30392	0	0
T1	269122	56	0	0
T2	123989	1	0	0
T3	950472	29	0	0
T4	326983	3	0	0
T5	379344	4	0	0
T11	460217	1	0	0
T35	203938	2	0	0
T63	127592	3	0	0
T88	93420	1	0	0
T89	460461	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595971301	595848376	0	0
T1	269122	269009	0	0
T2	123989	123938	0	0
T3	950472	950421	0	0
T4	326983	326925	0	0
T5	379344	379124	0	0
T11	460217	460155	0	0
T35	203938	203821	0	0
T63	127592	127530	0	0
T88	93420	93362	0	0
T89	460461	460410	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595971301	595848376	0	0
T1	269122	269009	0	0
T2	123989	123938	0	0
T3	950472	950421	0	0
T4	326983	326925	0	0
T5	379344	379124	0	0
T11	460217	460155	0	0
T35	203938	203821	0	0
T63	127592	127530	0	0
T88	93420	93362	0	0
T89	460461	460410	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	595971301	595848376	0	0
T1	269122	269009	0	0
T2	123989	123938	0	0
T3	950472	950421	0	0
T4	326983	326925	0	0
T5	379344	379124	0	0
T11	460217	460155	0	0
T35	203938	203821	0	0
T63	127592	127530	0	0
T88	93420	93362	0	0
T89	460461	460410	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2935	2935	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T11	1	1	0	0
T35	1	1	0	0
T63	1	1	0	0
T88	1	1	0	0
T89	1	1	0	0