Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : tlul_adapter_host
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.09 91.11 75.79 89.44 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex 87.26 90.91 69.23 88.89 100.00
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex 90.91 91.30 82.35 90.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.26 90.91 69.23 88.89 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.90 90.48 72.22 88.89 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.74 96.47 89.29 99.75 100.00 68.18 u_rv_core_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_cmd_intg_gen 94.12 88.24 100.00
u_rsp_chk 93.33 100.00 80.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.91 91.30 82.35 90.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.79 95.35 81.82 90.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
90.74 96.47 89.29 99.75 100.00 68.18 u_rv_core_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_cmd_intg_gen 100.00 100.00 100.00
u_rsp_chk 93.33 100.00 80.00 100.00

Line Coverage for Module : tlul_adapter_host ( parameter MAX_REQS=2,EnableDataIntgGen=1,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 + MAX_REQS=2,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 )
Line Coverage for Module self-instances :
SCORELINE
90.91 91.30
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex

Line No.TotalCoveredPercent
TOTAL232191.30
ALWAYS7033100.00
ALWAYS7855100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN12011100.00
ALWAYS1324375.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN149100.00
CONT_ASSIGN15311100.00
ALWAYS16800
ALWAYS17800
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
73 1 1
78 1 1
80 1 1
81 1 1
82 1 1
84 1 1
MISSING_ELSE
89 1 1
94 1 1
96 1 1
116 1 1
118 1 1
119 1 1
120 1 1
132 1 1
133 1 1
134 1 1
135 0 1
MISSING_ELSE
141 1 1
145 1 1
149 0 1
153 1 1
168 unreachable
170 unreachable
171 unreachable
172 unreachable
173 unreachable
==> MISSING_ELSE
178 unreachable
179 unreachable
181 unreachable

Line Coverage for Module : tlul_adapter_host ( parameter MAX_REQS=8,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=4,g_multiple_reqs.ReqNumW=3 )
Line Coverage for Module self-instances :
SCORELINE
87.26 90.91
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex

Line No.TotalCoveredPercent
TOTAL222090.91
ALWAYS7033100.00
ALWAYS7855100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9400
CONT_ASSIGN9611100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN12011100.00
ALWAYS1324375.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN149100.00
CONT_ASSIGN15311100.00
ALWAYS16800
ALWAYS17800
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
73 1 1
78 1 1
80 1 1
81 1 1
82 1 1
84 1 1
MISSING_ELSE
89 1 1
94 unreachable
96 1 1
116 1 1
118 1 1
119 1 1
120 1 1
132 1 1
133 1 1
134 1 1
135 0 1
MISSING_ELSE
141 1 1
145 1 1
149 0 1
153 1 1
168 unreachable
170 unreachable
171 unreachable
172 unreachable
173 unreachable
==> MISSING_ELSE
178 unreachable
179 unreachable
181 unreachable

Cond Coverage for Module : tlul_adapter_host ( parameter MAX_REQS=8,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=4,g_multiple_reqs.ReqNumW=3 )
Cond Coverage for Module self-instances :
SCORECOND
87.26 69.23
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex

TotalCoveredPercent
Conditions13969.23
Logical13969.23
Non-Logical00
Event00

 LINE       80
 EXPRESSION (req_i && gnt_o)
             --1--    --2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       81
 EXPRESSION (g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[(g_multiple_reqs.ReqNumW - 1):0])
            --------------------------------------------1-------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       94
 EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
             ----1----
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3 

 LINE       96
 EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
             ----1----
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3 

 LINE       96
 SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
                 ----1----
-1-StatusTests
0Unreachable
1Unreachable 

 LINE       141
 EXPRESSION (tl_i.d_error | intg_err)
             ------1-----   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT35,T5,T65 

 LINE       145
 EXPRESSION (intg_err_q | intg_err)
             -----1----   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered
Cond Coverage for Module : tlul_adapter_host ( parameter MAX_REQS=2,EnableDataIntgGen=1,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 + MAX_REQS=2,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 )
Cond Coverage for Module self-instances :
SCORECOND
90.91 82.35
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex

TotalCoveredPercent
Conditions171482.35
Logical171482.35
Non-Logical00
Event00

 LINE       80
 EXPRESSION (req_i && gnt_o)
             --1--    --2--
-1--2-StatusTests
01CoveredT81,T82,T83
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       81
 EXPRESSION (g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[0])
            -----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       94
 EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
             ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       96
 EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
             ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       96
 SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       141
 EXPRESSION (tl_i.d_error | intg_err)
             ------1-----   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T35,T5 

 LINE       145
 EXPRESSION (intg_err_q | intg_err)
             -----1----   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered
Branch Coverage for Module : tlul_adapter_host ( parameter MAX_REQS=2,EnableDataIntgGen=1,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 + MAX_REQS=2,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 )
Branch Coverage for Module self-instances :
SCOREBRANCH
90.91 90.00
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex

Line No.TotalCoveredPercent
Branches 10 9 90.00
TERNARY 94 2 2 100.00
IF 132 3 2 66.67
IF 70 2 2 100.00
IF 80 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	94	((~we_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	132	if ((!rst_ni))
-2-:	134	if (intg_err)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	70	if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	80	if ((req_i && gnt_o))
-2-:	81	if ((g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[0]))

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Covered T1,T2,T3
0 - Covered T1,T2,T3

Branch Coverage for Module : tlul_adapter_host ( parameter MAX_REQS=8,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=4,g_multiple_reqs.ReqNumW=3 )
Branch Coverage for Module self-instances :
SCOREBRANCH
87.26 88.89
tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex

Line No.TotalCoveredPercent
Branches 9 8 88.89
TERNARY 94 1 1 100.00
IF 132 3 2 66.67
IF 70 2 2 100.00
IF 80 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	94	((~we_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable 



	LineNo.	Expression
-1-:	132	if ((!rst_ni))
-2-:	134	if (intg_err)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	70	if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	80	if ((req_i && gnt_o))
-2-:	81	if ((g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[(g_multiple_reqs.ReqNumW - 1):0]))

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Covered T1,T2,T3
0 - Covered T1,T2,T3

Assert Coverage for Module : tlul_adapter_host
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DontExceeedMaxReqs 1054909252 105679779 0 0


DontExceeedMaxReqs
NameAttemptsReal SuccessesFailuresIncomplete
Total 1054909252 105679779 0 0
T1 538244 53407 0 0
T2 247978 18698 0 0
T3 1900944 278059 0 0
T4 653966 62491 0 0
T5 758688 70857 0 0
T11 920434 100801 0 0
T35 407876 67534 0 0
T63 255184 23964 0 0
T88 186840 16661 0 0
T89 920922 124018 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex
Line No.TotalCoveredPercent
TOTAL222090.91
ALWAYS7033100.00
ALWAYS7855100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9400
CONT_ASSIGN9611100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN12011100.00
ALWAYS1324375.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN149100.00
CONT_ASSIGN15311100.00
ALWAYS16800
ALWAYS17800
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
73 1 1
78 1 1
80 1 1
81 1 1
82 1 1
84 1 1
MISSING_ELSE
89 1 1
94 unreachable
96 1 1
116 1 1
118 1 1
119 1 1
120 1 1
132 1 1
133 1 1
134 1 1
135 0 1
MISSING_ELSE
141 1 1
145 1 1
149 0 1
153 1 1
168 unreachable
170 unreachable
171 unreachable
172 unreachable
173 unreachable
==> MISSING_ELSE
178 unreachable
179 unreachable
181 unreachable

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex
TotalCoveredPercent
Conditions13969.23
Logical13969.23
Non-Logical00
Event00

 LINE       80
 EXPRESSION (req_i && gnt_o)
             --1--    --2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       81
 EXPRESSION (g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[(g_multiple_reqs.ReqNumW - 1):0])
            --------------------------------------------1-------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       94
 EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
             ----1----
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3 

 LINE       96
 EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
             ----1----
-1-StatusTests
0Unreachable
1CoveredT1,T2,T3 

 LINE       96
 SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
                 ----1----
-1-StatusTests
0Unreachable
1Unreachable 

 LINE       141
 EXPRESSION (tl_i.d_error | intg_err)
             ------1-----   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT35,T5,T65 

 LINE       145
 EXPRESSION (intg_err_q | intg_err)
             -----1----   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex
Line No.TotalCoveredPercent
Branches 9 8 88.89
TERNARY 94 1 1 100.00
IF 132 3 2 66.67
IF 70 2 2 100.00
IF 80 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	94	((~we_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Unreachable 



	LineNo.	Expression
-1-:	132	if ((!rst_ni))
-2-:	134	if (intg_err)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	70	if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	80	if ((req_i && gnt_o))
-2-:	81	if ((g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[(g_multiple_reqs.ReqNumW - 1):0]))

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Covered T1,T2,T3
0 - Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DontExceeedMaxReqs 527454626 60818483 0 0


DontExceeedMaxReqs
NameAttemptsReal SuccessesFailuresIncomplete
Total 527454626 60818483 0 0
T1 269122 35168 0 0
T2 123989 11913 0 0
T3 950472 114039 0 0
T4 326983 33193 0 0
T5 379344 45250 0 0
T11 460217 63294 0 0
T35 203938 48568 0 0
T63 127592 17354 0 0
T88 93420 10253 0 0
T89 460461 64939 0 0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex
Line No.TotalCoveredPercent
TOTAL232191.30
ALWAYS7033100.00
ALWAYS7855100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9611100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN12011100.00
ALWAYS1324375.00
CONT_ASSIGN14111100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN149100.00
CONT_ASSIGN15311100.00
ALWAYS16800
ALWAYS17800
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
73 1 1
78 1 1
80 1 1
81 1 1
82 1 1
84 1 1
MISSING_ELSE
89 1 1
94 1 1
96 1 1
116 1 1
118 1 1
119 1 1
120 1 1
132 1 1
133 1 1
134 1 1
135 0 1
MISSING_ELSE
141 1 1
145 1 1
149 0 1
153 1 1
168 unreachable
170 unreachable
171 unreachable
172 unreachable
173 unreachable
==> MISSING_ELSE
178 unreachable
179 unreachable
181 unreachable

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex
TotalCoveredPercent
Conditions171482.35
Logical171482.35
Non-Logical00
Event00

 LINE       80
 EXPRESSION (req_i && gnt_o)
             --1--    --2--
-1--2-StatusTests
01CoveredT81,T82,T83
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       81
 EXPRESSION (g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[0])
            -----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       94
 EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
             ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       96
 EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
             ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       96
 SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
                 ----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       141
 EXPRESSION (tl_i.d_error | intg_err)
             ------1-----   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T35,T5 

 LINE       145
 EXPRESSION (intg_err_q | intg_err)
             -----1----   ----2---
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex
Line No.TotalCoveredPercent
Branches 10 9 90.00
TERNARY 94 2 2 100.00
IF 132 3 2 66.67
IF 70 2 2 100.00
IF 80 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	94	((~we_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	132	if ((!rst_ni))
-2-:	134	if (intg_err)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	70	if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	80	if ((req_i && gnt_o))
-2-:	81	if ((g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[0]))

Branches:
-1--2-StatusTests
1 1 Covered T1,T2,T3
1 0 Covered T1,T2,T3
0 - Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DontExceeedMaxReqs 527454626 44861296 0 0


DontExceeedMaxReqs
NameAttemptsReal SuccessesFailuresIncomplete
Total 527454626 44861296 0 0
T1 269122 18239 0 0
T2 123989 6785 0 0
T3 950472 164020 0 0
T4 326983 29298 0 0
T5 379344 25607 0 0
T11 460217 37507 0 0
T35 203938 18966 0 0
T63 127592 6610 0 0
T88 93420 6408 0 0
T89 460461 59079 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%