Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T35,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T3,T11,T212	Yes	T3,T11,T212	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T3,T11,T212	Yes	T3,T11,T212	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T35,*T50,*T80	Yes	T35,T50,T80	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_i.a_valid	Yes	Yes	T3,T11,T212	Yes	T3,T11,T212	INPUT
tl_o.a_ready	Yes	Yes	T3,T11,T212	Yes	T3,T11,T212	OUTPUT
tl_o.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T3,T11,T212	Yes	T3,T11,T212	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T3,T11,T212	Yes	T3,T11,T212	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T3,T11,T212	Yes	T3,T11,T212	OUTPUT
tl_o.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T80,*T401,*T204	Yes	T80,T401,T204	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T78,T79,T84	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T3,*T11,*T212	Yes	T3,T11,T212	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T3,T11,T212	Yes	T3,T11,T212	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T85,T65,T86	Yes	T85,T65,T86	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T85,T65,T86	Yes	T85,T65,T86	OUTPUT
cio_rx_i	Yes	Yes	T1,T35,T5	Yes	T1,T2,T35	INPUT
cio_tx_o	Yes	Yes	T3,T212,T46	Yes	T3,T212,T46	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T212,T216,T217	Yes	T212,T216,T217	OUTPUT
intr_tx_empty_o	Yes	Yes	T212,T216,T217	Yes	T212,T216,T217	OUTPUT
intr_rx_watermark_o	Yes	Yes	T212,T216,T217	Yes	T212,T216,T217	OUTPUT
intr_tx_done_o	Yes	Yes	T212,T216,T217	Yes	T212,T216,T217	OUTPUT
intr_rx_overflow_o	Yes	Yes	T212,T216,T217	Yes	T212,T216,T217	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T336,T331,T335	Yes	T336,T331,T335	OUTPUT
intr_rx_break_err_o	Yes	Yes	T336,T331,T335	Yes	T336,T331,T335	OUTPUT
intr_rx_timeout_o	Yes	Yes	T336,T331,T335	Yes	T336,T331,T335	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T336,T331,T335	Yes	T336,T331,T335	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T35,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T3,T46,T47	Yes	T3,T46,T47	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T3,T46,T47	Yes	T3,T46,T47	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T35,*T50,*T80	Yes	T35,T50,T80	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_i.a_valid	Yes	Yes	T3,T46,T47	Yes	T3,T46,T47	INPUT
tl_o.a_ready	Yes	Yes	T3,T46,T47	Yes	T3,T46,T47	OUTPUT
tl_o.d_error	Yes	Yes	T78,T79,T84	Yes	T78,T84,T266	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T3,T46,T47	Yes	T3,T46,T47	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T3,T46,T47	Yes	T3,T46,T47	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T3,T46,T47	Yes	T3,T46,T47	OUTPUT
tl_o.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T80,*T401,*T204	Yes	T80,T401,T204	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T77,T78,T84	Yes	T78,T79,T84	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T3,*T46,*T47	Yes	T3,T46,T47	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T3,T46,T47	Yes	T3,T46,T47	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
cio_rx_i	Yes	Yes	T1,T35,T5	Yes	T1,T2,T35	INPUT
cio_tx_o	Yes	Yes	T3,T46,T47	Yes	T3,T46,T47	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
intr_tx_empty_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
intr_rx_watermark_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
intr_tx_done_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
intr_rx_overflow_o	Yes	Yes	T216,T217,T218	Yes	T216,T217,T218	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T336,T331,T335	Yes	T336,T331,T335	OUTPUT
intr_rx_break_err_o	Yes	Yes	T336,T331,T335	Yes	T336,T331,T335	OUTPUT
intr_rx_timeout_o	Yes	Yes	T336,T331,T335	Yes	T336,T331,T335	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T336,T331,T335	Yes	T336,T331,T335	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T35,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T11,T212,T213	Yes	T11,T212,T213	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T11,T212,T213	Yes	T11,T212,T213	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T35,*T50,*T80	Yes	T35,T50,T80	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_i.a_valid	Yes	Yes	T11,T212,T52	Yes	T11,T212,T52	INPUT
tl_o.a_ready	Yes	Yes	T11,T212,T52	Yes	T11,T212,T52	OUTPUT
tl_o.d_error	Yes	Yes	T78,T79,T84	Yes	T77,T78,T79	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T11,T212,T213	Yes	T11,T212,T213	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T11,T212,T213	Yes	T11,T212,T52	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T11,T212,T213	Yes	T11,T212,T52	OUTPUT
tl_o.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T204,*T78,*T79	Yes	T204,T77,T78	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T78,T79,T84	Yes	T78,T79,T84	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T11,*T212,*T213	Yes	T11,T212,T213	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T11,T212,T52	Yes	T11,T212,T52	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T85,T65,T86	Yes	T85,T65,T86	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T85,T65,T86	Yes	T85,T65,T86	OUTPUT
cio_rx_i	Yes	Yes	T212,T213,T214	Yes	T212,T8,T213	INPUT
cio_tx_o	Yes	Yes	T212,T213,T214	Yes	T212,T213,T214	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T212,T213,T214	Yes	T212,T213,T214	OUTPUT
intr_tx_empty_o	Yes	Yes	T212,T213,T214	Yes	T212,T213,T214	OUTPUT
intr_rx_watermark_o	Yes	Yes	T212,T213,T214	Yes	T212,T213,T214	OUTPUT
intr_tx_done_o	Yes	Yes	T212,T213,T214	Yes	T212,T213,T214	OUTPUT
intr_rx_overflow_o	Yes	Yes	T212,T213,T214	Yes	T212,T213,T214	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T336,T331,T335	Yes	T336,T331,T335	OUTPUT
intr_rx_break_err_o	Yes	Yes	T336,T331,T335	Yes	T336,T331,T335	OUTPUT
intr_rx_timeout_o	Yes	Yes	T336,T331,T335	Yes	T336,T331,T335	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T336,T331,T335	Yes	T336,T331,T335	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T35,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T11,T143,T336	Yes	T11,T143,T336	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T11,T143,T336	Yes	T11,T143,T336	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T35,*T50,*T80	Yes	T35,T50,T80	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_i.a_valid	Yes	Yes	T11,T52,T143	Yes	T11,T52,T143	INPUT
tl_o.a_ready	Yes	Yes	T11,T52,T143	Yes	T11,T52,T143	OUTPUT
tl_o.d_error	Yes	Yes	T78,T79,T84	Yes	T78,T79,T84	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T11,T143,T336	Yes	T11,T143,T336	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T11,T143,T336	Yes	T11,T52,T143	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T11,T143,T336	Yes	T11,T52,T143	OUTPUT
tl_o.d_sink	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T204,*T78,*T79	Yes	T204,T77,T78	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T78,T79,T84	Yes	T78,T79,T84	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T11,*T143,*T336	Yes	T11,T143,T336	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T11,T52,T143	Yes	T11,T52,T143	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
cio_rx_i	Yes	Yes	T143,T345,T347	Yes	T143,T345,T347	INPUT
cio_tx_o	Yes	Yes	T143,T345,T347	Yes	T143,T345,T347	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T143,T336,T345	Yes	T143,T336,T345	OUTPUT
intr_tx_empty_o	Yes	Yes	T143,T336,T345	Yes	T143,T336,T345	OUTPUT
intr_rx_watermark_o	Yes	Yes	T143,T336,T345	Yes	T143,T336,T345	OUTPUT
intr_tx_done_o	Yes	Yes	T143,T336,T345	Yes	T143,T336,T345	OUTPUT
intr_rx_overflow_o	Yes	Yes	T143,T336,T345	Yes	T143,T336,T345	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T336,T331,T335	Yes	T336,T331,T335	OUTPUT
intr_rx_break_err_o	Yes	Yes	T336,T331,T335	Yes	T336,T331,T335	OUTPUT
intr_rx_timeout_o	Yes	Yes	T336,T331,T335	Yes	T336,T331,T335	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T336,T331,T335	Yes	T336,T331,T335	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T35,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T11,T14,T15	Yes	T11,T14,T15	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T11,T14,T15	Yes	T11,T14,T15	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T77,*T78,*T79	Yes	T77,T78,T79	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T35,*T50,*T80	Yes	T35,T50,T80	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T81,T82,T83	Yes	T81,T82,T83	INPUT
tl_i.a_valid	Yes	Yes	T11,T14,T15	Yes	T11,T14,T15	INPUT
tl_o.a_ready	Yes	Yes	T11,T14,T15	Yes	T11,T14,T15	OUTPUT
tl_o.d_error	Yes	Yes	T77,T78,T79	Yes	T77,T78,T84	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T11,T14,T15	Yes	T11,T14,T15	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T11,T14,T15	Yes	T11,T14,T15	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T11,T14,T15	Yes	T11,T14,T15	OUTPUT
tl_o.d_sink	Yes	Yes	T77,T78,T84	Yes	T77,T78,T79	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T204,*T77,*T78	Yes	T204,T77,T78	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T77,T78,T84	Yes	T78,T79,T84	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T11,*T14,*T15	Yes	T11,T14,T15	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T11,T14,T15	Yes	T11,T14,T15	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T85,T86,T87	Yes	T85,T86,T87	OUTPUT
cio_rx_i	Yes	Yes	T14,T15,T332	Yes	T14,T15,T332	INPUT
cio_tx_o	Yes	Yes	T14,T15,T332	Yes	T14,T15,T332	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T14,T15,T332	Yes	T14,T15,T332	OUTPUT
intr_tx_empty_o	Yes	Yes	T14,T15,T332	Yes	T14,T15,T332	OUTPUT
intr_rx_watermark_o	Yes	Yes	T14,T15,T332	Yes	T14,T15,T332	OUTPUT
intr_tx_done_o	Yes	Yes	T14,T15,T332	Yes	T14,T15,T332	OUTPUT
intr_rx_overflow_o	Yes	Yes	T14,T15,T332	Yes	T14,T15,T332	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T336,T331,T335	Yes	T336,T331,T335	OUTPUT
intr_rx_break_err_o	Yes	Yes	T336,T331,T335	Yes	T336,T331,T335	OUTPUT
intr_rx_timeout_o	Yes	Yes	T336,T331,T335	Yes	T336,T331,T335	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T336,T331,T335	Yes	T336,T331,T335	OUTPUT

*Tests covering at least one bit in the range