Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.77	97.29			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.77	97.29			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.77	97.29			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.77	97.29			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.77	97.29			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.77	97.29			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.68	96.99	84.51			93.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.77	97.29			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	92.06	95.92	81.63			90.70	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T56,T139,T140

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T56,T139,T140
1	1	Covered	T56,T139,T140

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T56,T139,T140

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T56,T139,T140
1	1	Covered	T56,T139,T140

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T56,T139,T140
0	0	1	Covered	T56,T139,T140
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T56,T139,T140
0	0	1	Covered	T56,T139,T140
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	149653808	79163	0	0
DstReqKnown_A	1808055	1583373	0	0
SrcAckBusyChk_A	149653808	202	0	0
SrcBusyKnown_A	149653808	148838867	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149653808	79163	0	0
T56	250439	445	0	0
T94	66147	0	0	0
T139	0	475	0	0
T140	0	2376	0	0
T141	0	1741	0	0
T175	15758	0	0	0
T241	39145	0	0	0
T322	68501	0	0	0
T395	0	2428	0	0
T396	0	303	0	0
T397	0	354	0	0
T416	0	823	0	0
T417	0	282	0	0
T423	569728	0	0	0
T424	46488	0	0	0
T425	531742	0	0	0
T426	39883	0	0	0
T427	320577	0	0	0
T428	0	2030	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1808055	1583373	0	0
T1	803	628	0	0
T2	477	305	0	0
T3	2136	1965	0	0
T4	838	664	0	0
T5	1775	1419	0	0
T11	1119	1054	0	0
T35	934	759	0	0
T63	523	349	0	0
T88	454	281	0	0
T89	1215	1044	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149653808	202	0	0
T56	250439	1	0	0
T94	66147	0	0	0
T139	0	1	0	0
T140	0	6	0	0
T141	0	4	0	0
T175	15758	0	0	0
T241	39145	0	0	0
T322	68501	0	0	0
T395	0	6	0	0
T396	0	1	0	0
T397	0	1	0	0
T416	0	2	0	0
T417	0	1	0	0
T423	569728	0	0	0
T424	46488	0	0	0
T425	531742	0	0	0
T426	39883	0	0	0
T427	320577	0	0	0
T428	0	6	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149653808	148838867	0	0
T1	66206	65331	0	0
T2	30667	30127	0	0
T3	228951	228499	0	0
T4	79671	78848	0	0
T5	93849	92514	0	0
T11	111171	110825	0	0
T35	50036	49694	0	0
T63	35635	34991	0	0
T88	23162	22789	0	0
T89	111199	110886	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T56,T139,T140

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T56,T139,T140
1	1	Covered	T56,T139,T140

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T56,T139,T140

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T56,T139,T140
1	1	Covered	T56,T139,T140

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T56,T139,T140
0	0	1	Covered	T56,T139,T140
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T56,T139,T140
0	0	1	Covered	T56,T139,T140
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	149653808	89620	0	0
DstReqKnown_A	1808055	1583373	0	0
SrcAckBusyChk_A	149653808	227	0	0
SrcBusyKnown_A	149653808	148838867	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149653808	89620	0	0
T56	250439	387	0	0
T94	66147	0	0	0
T139	0	447	0	0
T140	0	389	0	0
T141	0	3385	0	0
T175	15758	0	0	0
T241	39145	0	0	0
T322	68501	0	0	0
T395	0	287	0	0
T396	0	360	0	0
T397	0	309	0	0
T416	0	926	0	0
T417	0	330	0	0
T423	569728	0	0	0
T424	46488	0	0	0
T425	531742	0	0	0
T426	39883	0	0	0
T427	320577	0	0	0
T428	0	6747	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1808055	1583373	0	0
T1	803	628	0	0
T2	477	305	0	0
T3	2136	1965	0	0
T4	838	664	0	0
T5	1775	1419	0	0
T11	1119	1054	0	0
T35	934	759	0	0
T63	523	349	0	0
T88	454	281	0	0
T89	1215	1044	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149653808	227	0	0
T56	250439	1	0	0
T94	66147	0	0	0
T139	0	1	0	0
T140	0	1	0	0
T141	0	8	0	0
T175	15758	0	0	0
T241	39145	0	0	0
T322	68501	0	0	0
T395	0	1	0	0
T396	0	1	0	0
T397	0	1	0	0
T416	0	2	0	0
T417	0	1	0	0
T423	569728	0	0	0
T424	46488	0	0	0
T425	531742	0	0	0
T426	39883	0	0	0
T427	320577	0	0	0
T428	0	17	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149653808	148838867	0	0
T1	66206	65331	0	0
T2	30667	30127	0	0
T3	228951	228499	0	0
T4	79671	78848	0	0
T5	93849	92514	0	0
T11	111171	110825	0	0
T35	50036	49694	0	0
T63	35635	34991	0	0
T88	23162	22789	0	0
T89	111199	110886	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T56,T139,T140

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T56,T139,T140
1	1	Covered	T56,T139,T140

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T56,T139,T140

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T56,T139,T140
1	1	Covered	T56,T139,T140

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T56,T139,T140
0	0	1	Covered	T56,T139,T140
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T56,T139,T140
0	0	1	Covered	T56,T139,T140
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	149653808	81258	0	0
DstReqKnown_A	1808055	1583373	0	0
SrcAckBusyChk_A	149653808	210	0	0
SrcBusyKnown_A	149653808	148838867	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149653808	81258	0	0
T56	250439	387	0	0
T94	66147	0	0	0
T139	0	371	0	0
T140	0	2434	0	0
T141	0	1293	0	0
T175	15758	0	0	0
T241	39145	0	0	0
T322	68501	0	0	0
T395	0	811	0	0
T396	0	271	0	0
T397	0	290	0	0
T416	0	936	0	0
T417	0	314	0	0
T423	569728	0	0	0
T424	46488	0	0	0
T425	531742	0	0	0
T426	39883	0	0	0
T427	320577	0	0	0
T428	0	2039	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1808055	1583373	0	0
T1	803	628	0	0
T2	477	305	0	0
T3	2136	1965	0	0
T4	838	664	0	0
T5	1775	1419	0	0
T11	1119	1054	0	0
T35	934	759	0	0
T63	523	349	0	0
T88	454	281	0	0
T89	1215	1044	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149653808	210	0	0
T56	250439	1	0	0
T94	66147	0	0	0
T139	0	1	0	0
T140	0	6	0	0
T141	0	3	0	0
T175	15758	0	0	0
T241	39145	0	0	0
T322	68501	0	0	0
T395	0	2	0	0
T396	0	1	0	0
T397	0	1	0	0
T416	0	2	0	0
T417	0	1	0	0
T423	569728	0	0	0
T424	46488	0	0	0
T425	531742	0	0	0
T426	39883	0	0	0
T427	320577	0	0	0
T428	0	6	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149653808	148838867	0	0
T1	66206	65331	0	0
T2	30667	30127	0	0
T3	228951	228499	0	0
T4	79671	78848	0	0
T5	93849	92514	0	0
T11	111171	110825	0	0
T35	50036	49694	0	0
T63	35635	34991	0	0
T88	23162	22789	0	0
T89	111199	110886	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T56,T256,T139

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T56,T139,T140
1	1	Covered	T56,T139,T140

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T56,T139,T140

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T56,T139,T140
1	1	Covered	T56,T139,T140

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T56,T139,T140
0	0	1	Covered	T56,T139,T140
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T56,T139,T140
0	0	1	Covered	T56,T139,T140
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	149653808	87880	0	0
DstReqKnown_A	1808055	1583373	0	0
SrcAckBusyChk_A	149653808	224	0	0
SrcBusyKnown_A	149653808	148838867	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149653808	87880	0	0
T56	250439	480	0	0
T94	66147	0	0	0
T139	0	409	0	0
T140	0	4781	0	0
T141	0	2604	0	0
T175	15758	0	0	0
T241	39145	0	0	0
T322	68501	0	0	0
T395	0	5006	0	0
T396	0	320	0	0
T397	0	343	0	0
T416	0	865	0	0
T417	0	264	0	0
T423	569728	0	0	0
T424	46488	0	0	0
T425	531742	0	0	0
T426	39883	0	0	0
T427	320577	0	0	0
T428	0	2657	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1808055	1583373	0	0
T1	803	628	0	0
T2	477	305	0	0
T3	2136	1965	0	0
T4	838	664	0	0
T5	1775	1419	0	0
T11	1119	1054	0	0
T35	934	759	0	0
T63	523	349	0	0
T88	454	281	0	0
T89	1215	1044	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149653808	224	0	0
T56	250439	1	0	0
T94	66147	0	0	0
T139	0	1	0	0
T140	0	12	0	0
T141	0	6	0	0
T175	15758	0	0	0
T241	39145	0	0	0
T322	68501	0	0	0
T395	0	12	0	0
T396	0	1	0	0
T397	0	1	0	0
T416	0	2	0	0
T417	0	1	0	0
T423	569728	0	0	0
T424	46488	0	0	0
T425	531742	0	0	0
T426	39883	0	0	0
T427	320577	0	0	0
T428	0	7	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149653808	148838867	0	0
T1	66206	65331	0	0
T2	30667	30127	0	0
T3	228951	228499	0	0
T4	79671	78848	0	0
T5	93849	92514	0	0
T11	111171	110825	0	0
T35	50036	49694	0	0
T63	35635	34991	0	0
T88	23162	22789	0	0
T89	111199	110886	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T56,T139,T140

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T56,T139,T140
1	1	Covered	T56,T139,T140

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T56,T139,T140

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T56,T139,T140
1	1	Covered	T56,T139,T140

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T56,T139,T140
0	0	1	Covered	T56,T139,T140
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T56,T139,T140
0	0	1	Covered	T56,T139,T140
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	149653808	98793	0	0
DstReqKnown_A	1808055	1583373	0	0
SrcAckBusyChk_A	149653808	251	0	0
SrcBusyKnown_A	149653808	148838867	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149653808	98793	0	0
T56	250439	363	0	0
T94	66147	0	0	0
T139	0	451	0	0
T140	0	4407	0	0
T141	0	3378	0	0
T175	15758	0	0	0
T241	39145	0	0	0
T322	68501	0	0	0
T395	0	3792	0	0
T396	0	284	0	0
T397	0	315	0	0
T416	0	807	0	0
T417	0	274	0	0
T423	569728	0	0	0
T424	46488	0	0	0
T425	531742	0	0	0
T426	39883	0	0	0
T427	320577	0	0	0
T428	0	8684	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1808055	1583373	0	0
T1	803	628	0	0
T2	477	305	0	0
T3	2136	1965	0	0
T4	838	664	0	0
T5	1775	1419	0	0
T11	1119	1054	0	0
T35	934	759	0	0
T63	523	349	0	0
T88	454	281	0	0
T89	1215	1044	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149653808	251	0	0
T56	250439	1	0	0
T94	66147	0	0	0
T139	0	1	0	0
T140	0	11	0	0
T141	0	8	0	0
T175	15758	0	0	0
T241	39145	0	0	0
T322	68501	0	0	0
T395	0	9	0	0
T396	0	1	0	0
T397	0	1	0	0
T416	0	2	0	0
T417	0	1	0	0
T423	569728	0	0	0
T424	46488	0	0	0
T425	531742	0	0	0
T426	39883	0	0	0
T427	320577	0	0	0
T428	0	22	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149653808	148838867	0	0
T1	66206	65331	0	0
T2	30667	30127	0	0
T3	228951	228499	0	0
T4	79671	78848	0	0
T5	93849	92514	0	0
T11	111171	110825	0	0
T35	50036	49694	0	0
T63	35635	34991	0	0
T88	23162	22789	0	0
T89	111199	110886	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T56,T139,T140

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T56,T139,T140
1	1	Covered	T56,T139,T140

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T56,T139,T140

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T56,T139,T140
1	1	Covered	T56,T139,T140

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T56,T139,T140
0	0	1	Covered	T56,T139,T140
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T56,T139,T140
0	0	1	Covered	T56,T139,T140
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	149653808	84952	0	0
DstReqKnown_A	1808055	1583373	0	0
SrcAckBusyChk_A	149653808	218	0	0
SrcBusyKnown_A	149653808	148838867	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149653808	84952	0	0
T56	250439	409	0	0
T94	66147	0	0	0
T139	0	374	0	0
T140	0	3274	0	0
T141	0	771	0	0
T175	15758	0	0	0
T241	39145	0	0	0
T322	68501	0	0	0
T395	0	1164	0	0
T396	0	293	0	0
T397	0	358	0	0
T416	0	780	0	0
T417	0	322	0	0
T423	569728	0	0	0
T424	46488	0	0	0
T425	531742	0	0	0
T426	39883	0	0	0
T427	320577	0	0	0
T428	0	3664	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1808055	1583373	0	0
T1	803	628	0	0
T2	477	305	0	0
T3	2136	1965	0	0
T4	838	664	0	0
T5	1775	1419	0	0
T11	1119	1054	0	0
T35	934	759	0	0
T63	523	349	0	0
T88	454	281	0	0
T89	1215	1044	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149653808	218	0	0
T56	250439	1	0	0
T94	66147	0	0	0
T139	0	1	0	0
T140	0	8	0	0
T141	0	2	0	0
T175	15758	0	0	0
T241	39145	0	0	0
T322	68501	0	0	0
T395	0	3	0	0
T396	0	1	0	0
T397	0	1	0	0
T416	0	2	0	0
T417	0	1	0	0
T423	569728	0	0	0
T424	46488	0	0	0
T425	531742	0	0	0
T426	39883	0	0	0
T427	320577	0	0	0
T428	0	10	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149653808	148838867	0	0
T1	66206	65331	0	0
T2	30667	30127	0	0
T3	228951	228499	0	0
T4	79671	78848	0	0
T5	93849	92514	0	0
T11	111171	110825	0	0
T35	50036	49694	0	0
T63	35635	34991	0	0
T88	23162	22789	0	0
T89	111199	110886	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T17,T18,T20

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T17,T18,T20
1	1	Covered	T17,T18,T20

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T17,T60,T18
1	0	Covered	T17,T18,T20

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T17,T18,T20
1	1	Covered	T17,T18,T20

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T17,T60,T18

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T17,T18,T20
0	0	1	Covered	T17,T18,T20
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T17,T18,T20
0	0	1	Covered	T17,T60,T18
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	149653808	113582	0	0
DstReqKnown_A	1808055	1583373	0	0
SrcAckBusyChk_A	149653808	255	0	0
SrcBusyKnown_A	149653808	148838867	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149653808	113582	0	0
T6	45045	0	0	0
T7	145544	0	0	0
T16	0	1918	0	0
T17	147625	646	0	0
T18	0	939	0	0
T20	0	1630	0	0
T28	0	1390	0	0
T39	43086	0	0	0
T51	53042	0	0	0
T55	0	347	0	0
T57	0	822	0	0
T58	0	1073	0	0
T64	63901	0	0	0
T103	0	1684	0	0
T104	0	1596	0	0
T105	31056	0	0	0
T106	22271	0	0	0
T107	75661	0	0	0
T108	38995	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1808055	1583373	0	0
T1	803	628	0	0
T2	477	305	0	0
T3	2136	1965	0	0
T4	838	664	0	0
T5	1775	1419	0	0
T11	1119	1054	0	0
T35	934	759	0	0
T63	523	349	0	0
T88	454	281	0	0
T89	1215	1044	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149653808	255	0	0
T6	45045	0	0	0
T7	145544	0	0	0
T16	0	6	0	0
T17	147625	2	0	0
T18	0	2	0	0
T20	0	4	0	0
T28	0	3	0	0
T39	43086	0	0	0
T51	53042	0	0	0
T57	0	3	0	0
T58	0	3	0	0
T64	63901	0	0	0
T103	0	4	0	0
T104	0	4	0	0
T105	31056	0	0	0
T106	22271	0	0	0
T107	75661	0	0	0
T108	38995	0	0	0
T422	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149653808	148838867	0	0
T1	66206	65331	0	0
T2	30667	30127	0	0
T3	228951	228499	0	0
T4	79671	78848	0	0
T5	93849	92514	0	0
T11	111171	110825	0	0
T35	50036	49694	0	0
T63	35635	34991	0	0
T88	23162	22789	0	0
T89	111199	110886	0	0