Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1117508	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

38163430

1

T1

12435

T2

98575

T3

3642

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	27297188	1			T1	4824		T2	55406		T3	925
values[0x0]	10865281	1			T1	7611		T2	43169		T3	2717
values[0x1]	1118469	1			T1	796		T2	514		T3	121

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	9443	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

39271495

1

T1

13231

T2

99089

T3

3763

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	19625833	1			T1	6616		T2	49545		T3	1882
valid_sources[0x01]	19624942	1			T1	6615		T2	49544		T3	1881
valid_sources[0x02]	277	1			T49	1		T53	1		T28	64
valid_sources[0x03]	451	1			T49	2		T52	3		T108	13
valid_sources[0x04]	456	1			T53	1		T101	4		T190	9
valid_sources[0x05]	585	1			T28	93		T29	56		T232	26
valid_sources[0x06]	319	1			T49	1		T28	35		T232	43
valid_sources[0x07]	479	1			T49	1		T190	8		T28	79
valid_sources[0x08]	276	1			T52	1		T28	66		T232	39
valid_sources[0x09]	723	1			T53	1		T28	96		T29	73
valid_sources[0x0a]	376	1			T53	1		T108	26		T28	37
valid_sources[0x0b]	365	1			T53	1		T28	43		T29	107
valid_sources[0x0c]	384	1			T53	1		T28	58		T29	129
valid_sources[0x0d]	346	1			T49	2		T53	1		T28	55
valid_sources[0x0e]	421	1			T49	1		T28	81		T29	101
valid_sources[0x0f]	317	1			T53	1		T28	14		T29	62
valid_sources[0x10]	329	1			T49	1		T52	1		T53	1
valid_sources[0x11]	282	1			T53	1		T28	32		T29	20
valid_sources[0x12]	294	1			T28	27		T29	24		T232	37
valid_sources[0x13]	415	1			T28	97		T232	34		T233	33
valid_sources[0x14]	262	1			T52	6		T53	1		T28	32
valid_sources[0x15]	476	1			T49	3		T52	1		T53	2
valid_sources[0x16]	338	1			T28	53		T29	58		T232	66
valid_sources[0x17]	234	1			T53	1		T28	25		T29	8
valid_sources[0x18]	421	1			T49	1		T52	7		T190	6
valid_sources[0x19]	256	1			T28	44		T29	1		T232	70
valid_sources[0x1a]	384	1			T53	1		T28	33		T29	32
valid_sources[0x1b]	609	1			T53	1		T28	59		T29	26
valid_sources[0x1c]	395	1			T53	1		T28	33		T29	6
valid_sources[0x1d]	467	1			T49	1		T28	45		T29	67
valid_sources[0x1e]	367	1			T52	4		T28	65		T232	76
valid_sources[0x1f]	587	1			T49	1		T28	70		T29	183
valid_sources[0x20]	291	1			T49	1		T28	60		T29	41

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27297188

1

T1

4824

T2

55406

T3

925

values[0x0]

all_enables

biggest_size

10860536

1

T1

7611

T2

43169

T3

2717

values[0x1]

all_enables

biggest_size

5706

1

T49

21

T52

20

T53

17