Unified Coverage Report :: Module :: spi_host

Module : spi_host

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.92			84.92

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_host_1.0/rtl/spi_host.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_spi_host0	83.52			83.52
tb.dut.top_earlgrey.u_spi_host1	83.95			83.95

---

Module Instance : tb.dut.top_earlgrey.u_spi_host0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.52			83.52

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.52			83.52

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.22	92.47		87.18			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_spi_host1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.95			83.95

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.95			83.95

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.22	92.47		87.18			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : spi_host

	Total	Covered	Percent
Totals	46	33	71.74
Total Bits	358	304	84.92
Total Bits 0->1	179	152	84.92
Total Bits 1->0	179	152	84.92

Ports	46	33	71.74
Port Bits	358	304	84.92
Port Bits 0->1	179	152	84.92
Port Bits 1->0	179	152	84.92

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T11,T150,T12	Yes	T11,T150,T12	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T11,T12,T91	Yes	T11,T12,T91	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T11,T150,T12	Yes	T11,T150,T12	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T11,*T150,*T12	Yes	T11,T150,T12	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T11,T150,T12	Yes	T11,T150,T12	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T11,T12,T91	Yes	T11,T12,T91	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T11,T150,T12	Yes	T11,T150,T12	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T11,*T150,T12	Yes	T11,T150,T12	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T150,*T91,*T141	Yes	T150,T91,T141	INPUT
tl_i.a_address[19:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[21:20]	Yes	Yes	T11,T150,T12	Yes	T11,T150,T12	INPUT
tl_i.a_address[29:22]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T11,*T150,*T12	Yes	T11,T150,T12	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[0]	No	No		No		INPUT
tl_i.a_source[1]	Yes	Yes	*T11,*T150,*T12	Yes	T11,T150,T12	INPUT
tl_i.a_source[5:2]	No	No		No		INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[0]	No	No		No		INPUT
tl_i.a_size[1]	Yes	Yes	T11,T150,T12	Yes	T11,T150,T12	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T12,*T13,*T97	Yes	T12,T13,T97	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T11,T150,T12	Yes	T11,T150,T12	INPUT
tl_i.a_valid	Yes	Yes	T11,T150,T12	Yes	T11,T150,T12	INPUT
tl_o.a_ready	Yes	Yes	T11,T150,T12	Yes	T11,T150,T12	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T11,T12,T91	Yes	T11,T12,T91	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T11,T150,T12	Yes	T11,T150,T12	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T11,T150,T12	Yes	T11,T150,T12	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T11,T12,T91	Yes	T11,T12,T91	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T11,*T150,*T12	Yes	T11,T150,T12	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T11,T150,T12	Yes	T11,T150,T12	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T11,*T150,*T12	Yes	T11,T150,T12	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T11,T150,T12	Yes	T11,T150,T12	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T54,T93,T161	Yes	T54,T93,T161	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T54,T93,T161	Yes	T54,T93,T161	OUTPUT
cio_sck_o	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
cio_sck_en_o	Yes	Yes	T12,T13,T96	Yes	T11,T12,T13	OUTPUT
cio_csb_o	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
cio_csb_en_o	Yes	Yes	T12,T13,T96	Yes	T11,T12,T13	OUTPUT
cio_sd_o[3:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
cio_sd_en_o[3:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
cio_sd_i[3:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
passthrough_i.s_en[0]	Yes	Yes	*T12,*T13,*T96	Yes	T12,T13,T96	INPUT
passthrough_i.s_en[3:1]	No	No		No		INPUT
passthrough_i.s[3:0]	Yes	Yes	T37,T12,T13	Yes	T37,T12,T13	INPUT
passthrough_i.csb_en	No	No		No		INPUT
passthrough_i.csb	Yes	Yes	T12,T13,T95	Yes	T12,T13,T95	INPUT
passthrough_i.sck_en	No	No		No		INPUT
passthrough_i.sck	Yes	Yes	T37,T12,T13	Yes	T37,T12,T13	INPUT
passthrough_i.passthrough_en	Yes	Yes	T12,T13,T97	Yes	T12,T13,T96	INPUT
passthrough_o.s[3:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
intr_error_o	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	OUTPUT
intr_spi_event_o	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_spi_host0

	Total	Covered	Percent
Totals	44	31	70.45
Total Bits	352	294	83.52
Total Bits 0->1	176	147	83.52
Total Bits 1->0	176	147	83.52

Ports	44	31	70.45
Port Bits	352	294	83.52
Port Bits 0->1	176	147	83.52
Port Bits 1->0	176	147	83.52

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T11,T150,T12	Yes	T11,T150,T12	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T11,T12,T91	Yes	T11,T12,T91	INPUT
tl_i.a_user.cmd_intg[0]	Yes	Yes	*T11,*T150,*T12	Yes	T11,T150,T12	INPUT
tl_i.a_user.cmd_intg[1]	No	No		No		INPUT
tl_i.a_user.cmd_intg[6:2]	Yes	Yes	T11,T150,T12	Yes	T11,T150,T12	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T11,*T150,*T12	Yes	T11,T150,T12	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T11,T150,T12	Yes	T11,T150,T12	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T11,T12,T91	Yes	T11,T12,T91	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T11,T150,T12	Yes	T11,T150,T12	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	T11,*T150,T12	Yes	T11,T150,T12	INPUT
tl_i.a_address[19:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[21:20]	Yes	Yes	T11,T150,T12	Yes	T11,T150,T12	INPUT
tl_i.a_address[29:22]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T11,*T150,*T12	Yes	T11,T150,T12	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[0]	No	No		No		INPUT
tl_i.a_source[1]	Yes	Yes	*T11,*T150,*T12	Yes	T11,T150,T12	INPUT
tl_i.a_source[5:2]	No	No		No		INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[0]	No	No		No		INPUT
tl_i.a_size[1]	Yes	Yes	T11,T150,T12	Yes	T11,T150,T12	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T12,*T13,*T97	Yes	T12,T13,T97	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T11,T150,T12	Yes	T11,T150,T12	INPUT
tl_i.a_valid	Yes	Yes	T11,T150,T12	Yes	T11,T150,T12	INPUT
tl_o.a_ready	Yes	Yes	T11,T150,T12	Yes	T11,T150,T12	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T11,T12,T91	Yes	T11,T12,T91	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T11,T150,T12	Yes	T11,T150,T12	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T11,T150,T12	Yes	T11,T150,T12	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T11,T12,T91	Yes	T11,T12,T91	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T11,*T150,*T12	Yes	T11,T150,T12	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T11,T150,T12	Yes	T11,T150,T12	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T11,*T150,*T12	Yes	T11,T150,T12	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T11,T150,T12	Yes	T11,T150,T12	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T54,T93,T161	Yes	T54,T93,T161	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T54,T93,T161	Yes	T54,T93,T161	OUTPUT
cio_sck_o	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
cio_sck_en_o	Yes	Yes	T12,T13,T96	Yes	T11,T12,T13	OUTPUT
cio_csb_o	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
cio_csb_en_o	Yes	Yes	T12,T13,T96	Yes	T11,T12,T13	OUTPUT
cio_sd_o[3:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
cio_sd_en_o[0]	Yes	Yes	*T11,*T12,*T13	Yes	T11,T12,T13	OUTPUT
cio_sd_en_o[3:1]	No	No		No		OUTPUT
cio_sd_i[3:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	INPUT
passthrough_i.s_en[0]	Yes	Yes	*T12,*T13,*T96	Yes	T12,T13,T96	INPUT
passthrough_i.s_en[3:1]	No	No		No		INPUT
passthrough_i.s[3:0]	Yes	Yes	T37,T12,T13	Yes	T37,T12,T13	INPUT
passthrough_i.csb_en[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off.
passthrough_i.csb	Yes	Yes	T12,T13,T95	Yes	T12,T13,T95	INPUT
passthrough_i.sck_en[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off.
passthrough_i.sck	Yes	Yes	T37,T12,T13	Yes	T37,T12,T13	INPUT
passthrough_i.passthrough_en	Yes	Yes	T12,T13,T97	Yes	T12,T13,T96	INPUT
passthrough_o.s[3:0]	Yes	Yes	T11,T12,T13	Yes	T11,T12,T13	OUTPUT
intr_error_o	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	OUTPUT
intr_spi_event_o	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_spi_host1

	Total	Covered	Percent
Totals	38	25	65.79
Total Bits	324	272	83.95
Total Bits 0->1	162	138	85.19
Total Bits 1->0	162	134	82.72

Ports	38	25	65.79
Port Bits	324	272	83.95
Port Bits 0->1	162	138	85.19
Port Bits 1->0	162	134	82.72

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T150,T91,T141	Yes	T150,T91,T141	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T91,T141,T98	Yes	T91,T141,T98	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T150,T91,T141	Yes	T150,T91,T141	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T150,*T91,*T141	Yes	T150,T91,T141	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T150,T91,T141	Yes	T150,T91,T141	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T91,T141,T98	Yes	T91,T141,T98	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T150,T91,T141	Yes	T150,T91,T141	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[5:2]	Yes	Yes	*T150,*T91,*T141	Yes	T150,T91,T141	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T150,*T91,*T141	Yes	T150,T91,T141	INPUT
tl_i.a_address[19:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[21:20]	Yes	Yes	T150,T91,T141	Yes	T150,T91,T141	INPUT
tl_i.a_address[29:22]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T150,*T91,*T141	Yes	T150,T91,T141	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[0]	No	No		No		INPUT
tl_i.a_source[1]	Yes	Yes	*T150,*T91,*T141	Yes	T150,T91,T141	INPUT
tl_i.a_source[5:2]	No	No		No		INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[0]	No	No		No		INPUT
tl_i.a_size[1]	Yes	Yes	T150,T91,T141	Yes	T150,T91,T141	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[1:0]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T150,T91,T141	Yes	T150,T91,T141	INPUT
tl_i.a_valid	Yes	Yes	T150,T91,T141	Yes	T150,T91,T141	INPUT
tl_o.a_ready	Yes	Yes	T150,T91,T141	Yes	T150,T91,T141	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T91,T141,T98	Yes	T91,T141,T98	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T150,T91,T141	Yes	T150,T91,T141	OUTPUT
tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T150,T91,T141	Yes	T150,T91,T141	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T91,T141,T98	Yes	T91,T141,T98	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[1]	Yes	Yes	*T150,*T91,*T141	Yes	T150,T91,T141	OUTPUT
tl_o.d_source[5:2]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[0]	No	No		No		OUTPUT
tl_o.d_size[1]	Yes	Yes	T150,T91,T141	Yes	T150,T91,T141	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T150,*T91,*T141	Yes	T150,T91,T141	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T150,T91,T141	Yes	T150,T91,T141	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	OUTPUT
cio_sck_o	Yes	Yes	T40,T229,T230	Yes	T40,T229,T230	OUTPUT
cio_sck_en_o	No	No		Yes	T40,T229,T230	OUTPUT
cio_csb_o	Yes	Yes	T40,T229,T230	Yes	T40,T229,T230	OUTPUT
cio_csb_en_o	No	No		Yes	T40,T229,T230	OUTPUT
cio_sd_o[0]	Yes	Yes	*T33	Yes	T33	OUTPUT
cio_sd_o[1]	No	No		Yes	T40,T229,T230	OUTPUT
cio_sd_o[2]	No	No		No		OUTPUT
cio_sd_o[3]	No	No		Yes	T40,T229,T230	OUTPUT
cio_sd_en_o[3:0]	Yes	Yes	T40,T229,T230	Yes	T40,T229,T230	OUTPUT
cio_sd_i[3:0]	Yes	Yes	T40,T229,T230	Yes	T11,T32,T40	INPUT
passthrough_i.s_en[3:0]	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.s[3:0]	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.csb_en	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.csb	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.sck_en	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.sck	Unreachable	Unreachable		Unreachable		INPUT
passthrough_i.passthrough_en	Unreachable	Unreachable		Unreachable		INPUT
passthrough_o.s[3:0]	Unreachable	Unreachable		Unreachable		OUTPUT
intr_error_o	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	OUTPUT
intr_spi_event_o	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	OUTPUT

*Tests covering at least one bit in the range