Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	529253896	61285584	0	0
DepthKnown_A	529253896	529145477	0	0
RvalidKnown_A	529253896	529145477	0	0
WreadyKnown_A	529253896	529145477	0	0
gen_passthru_fifo.paramCheckPass	1027	1027	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	61285584	0	0
T1	219930	28983	0	0
T2	610375	83206	0	0
T3	82768	7881	0	0
T4	266866	34790	0	0
T31	233232	30773	0	0
T54	493951	70603	0	0
T58	450658	56752	0	0
T59	131504	12779	0	0
T60	152022	20858	0	0
T119	237771	31254	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	529145477	0	0
T1	219930	219810	0	0
T2	610375	610317	0	0
T3	82768	82710	0	0
T4	266866	266764	0	0
T31	233232	233115	0	0
T54	493951	493842	0	0
T58	450658	450546	0	0
T59	131504	131406	0	0
T60	152022	151964	0	0
T119	237771	237647	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	529145477	0	0
T1	219930	219810	0	0
T2	610375	610317	0	0
T3	82768	82710	0	0
T4	266866	266764	0	0
T31	233232	233115	0	0
T54	493951	493842	0	0
T58	450658	450546	0	0
T59	131504	131406	0	0
T60	152022	151964	0	0
T119	237771	237647	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	529145477	0	0
T1	219930	219810	0	0
T2	610375	610317	0	0
T3	82768	82710	0	0
T4	266866	266764	0	0
T31	233232	233115	0	0
T54	493951	493842	0	0
T58	450658	450546	0	0
T59	131504	131406	0	0
T60	152022	151964	0	0
T119	237771	237647	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T31	1	1	0	0
T54	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T119	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	529253896	47385771	0	0
DepthKnown_A	529253896	529145477	0	0
RvalidKnown_A	529253896	529145477	0	0
WreadyKnown_A	529253896	529145477	0	0
gen_passthru_fifo.paramCheckPass	1027	1027	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	47385771	0	0
T1	219930	19297	0	0
T2	610375	77546	0	0
T3	82768	5679	0	0
T4	266866	25319	0	0
T31	233232	21115	0	0
T54	493951	51219	0	0
T58	450658	52293	0	0
T59	131504	8677	0	0
T60	152022	15562	0	0
T119	237771	21607	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	529145477	0	0
T1	219930	219810	0	0
T2	610375	610317	0	0
T3	82768	82710	0	0
T4	266866	266764	0	0
T31	233232	233115	0	0
T54	493951	493842	0	0
T58	450658	450546	0	0
T59	131504	131406	0	0
T60	152022	151964	0	0
T119	237771	237647	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	529145477	0	0
T1	219930	219810	0	0
T2	610375	610317	0	0
T3	82768	82710	0	0
T4	266866	266764	0	0
T31	233232	233115	0	0
T54	493951	493842	0	0
T58	450658	450546	0	0
T59	131504	131406	0	0
T60	152022	151964	0	0
T119	237771	237647	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	529145477	0	0
T1	219930	219810	0	0
T2	610375	610317	0	0
T3	82768	82710	0	0
T4	266866	266764	0	0
T31	233232	233115	0	0
T54	493951	493842	0	0
T58	450658	450546	0	0
T59	131504	131406	0	0
T60	152022	151964	0	0
T119	237771	237647	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T31	1	1	0	0
T54	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T119	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	529253896	46580826	0	0
DepthKnown_A	529253896	529145477	0	0
RvalidKnown_A	529253896	529145477	0	0
WreadyKnown_A	529253896	529145477	0	0
gen_passthru_fifo.paramCheckPass	1027	1027	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	46580826	0	0
T1	219930	13620	0	0
T2	610375	99249	0	0
T3	82768	3906	0	0
T4	266866	18141	0	0
T31	233232	14963	0	0
T54	493951	30358	0	0
T58	450658	7230	0	0
T59	131504	6518	0	0
T60	152022	9020	0	0
T119	237771	15317	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	529145477	0	0
T1	219930	219810	0	0
T2	610375	610317	0	0
T3	82768	82710	0	0
T4	266866	266764	0	0
T31	233232	233115	0	0
T54	493951	493842	0	0
T58	450658	450546	0	0
T59	131504	131406	0	0
T60	152022	151964	0	0
T119	237771	237647	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	529145477	0	0
T1	219930	219810	0	0
T2	610375	610317	0	0
T3	82768	82710	0	0
T4	266866	266764	0	0
T31	233232	233115	0	0
T54	493951	493842	0	0
T58	450658	450546	0	0
T59	131504	131406	0	0
T60	152022	151964	0	0
T119	237771	237647	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	529145477	0	0
T1	219930	219810	0	0
T2	610375	610317	0	0
T3	82768	82710	0	0
T4	266866	266764	0	0
T31	233232	233115	0	0
T54	493951	493842	0	0
T58	450658	450546	0	0
T59	131504	131406	0	0
T60	152022	151964	0	0
T119	237771	237647	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T31	1	1	0	0
T54	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T119	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	529253896	39354754	0	0
DepthKnown_A	529253896	529145477	0	0
RvalidKnown_A	529253896	529145477	0	0
WreadyKnown_A	529253896	529145477	0	0
gen_passthru_fifo.paramCheckPass	1027	1027	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	39354754	0	0
T1	219930	13231	0	0
T2	610375	99089	0	0
T3	82768	3763	0	0
T4	266866	17760	0	0
T31	233232	14575	0	0
T54	493951	29591	0	0
T58	450658	6951	0	0
T59	131504	6251	0	0
T60	152022	8736	0	0
T119	237771	14928	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	529145477	0	0
T1	219930	219810	0	0
T2	610375	610317	0	0
T3	82768	82710	0	0
T4	266866	266764	0	0
T31	233232	233115	0	0
T54	493951	493842	0	0
T58	450658	450546	0	0
T59	131504	131406	0	0
T60	152022	151964	0	0
T119	237771	237647	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	529145477	0	0
T1	219930	219810	0	0
T2	610375	610317	0	0
T3	82768	82710	0	0
T4	266866	266764	0	0
T31	233232	233115	0	0
T54	493951	493842	0	0
T58	450658	450546	0	0
T59	131504	131406	0	0
T60	152022	151964	0	0
T119	237771	237647	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	529145477	0	0
T1	219930	219810	0	0
T2	610375	610317	0	0
T3	82768	82710	0	0
T4	266866	266764	0	0
T31	233232	233115	0	0
T54	493951	493842	0	0
T58	450658	450546	0	0
T59	131504	131406	0	0
T60	152022	151964	0	0
T119	237771	237647	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T31	1	1	0	0
T54	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T119	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	529253896	65478	0	0
DepthKnown_A	529253896	529145477	0	0
RvalidKnown_A	529253896	529145477	0	0
WreadyKnown_A	529253896	529145477	0	0
gen_passthru_fifo.paramCheckPass	1027	1027	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	65478	0	0
T1	219930	151	0	0
T2	610375	13	0	0
T3	82768	19	0	0
T4	266866	151	0	0
T31	233232	151	0	0
T54	493951	69	0	0
T58	450658	30	0	0
T59	131504	27	0	0
T60	152022	26	0	0
T119	237771	151	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	529145477	0	0
T1	219930	219810	0	0
T2	610375	610317	0	0
T3	82768	82710	0	0
T4	266866	266764	0	0
T31	233232	233115	0	0
T54	493951	493842	0	0
T58	450658	450546	0	0
T59	131504	131406	0	0
T60	152022	151964	0	0
T119	237771	237647	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	529145477	0	0
T1	219930	219810	0	0
T2	610375	610317	0	0
T3	82768	82710	0	0
T4	266866	266764	0	0
T31	233232	233115	0	0
T54	493951	493842	0	0
T58	450658	450546	0	0
T59	131504	131406	0	0
T60	152022	151964	0	0
T119	237771	237647	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	529145477	0	0
T1	219930	219810	0	0
T2	610375	610317	0	0
T3	82768	82710	0	0
T4	266866	266764	0	0
T31	233232	233115	0	0
T54	493951	493842	0	0
T58	450658	450546	0	0
T59	131504	131406	0	0
T60	152022	151964	0	0
T119	237771	237647	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T31	1	1	0	0
T54	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T119	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	529253896	65478	0	0
DepthKnown_A	529253896	529145477	0	0
RvalidKnown_A	529253896	529145477	0	0
WreadyKnown_A	529253896	529145477	0	0
gen_passthru_fifo.paramCheckPass	1027	1027	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	65478	0	0
T1	219930	151	0	0
T2	610375	13	0	0
T3	82768	19	0	0
T4	266866	151	0	0
T31	233232	151	0	0
T54	493951	69	0	0
T58	450658	30	0	0
T59	131504	27	0	0
T60	152022	26	0	0
T119	237771	151	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	529145477	0	0
T1	219930	219810	0	0
T2	610375	610317	0	0
T3	82768	82710	0	0
T4	266866	266764	0	0
T31	233232	233115	0	0
T54	493951	493842	0	0
T58	450658	450546	0	0
T59	131504	131406	0	0
T60	152022	151964	0	0
T119	237771	237647	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	529145477	0	0
T1	219930	219810	0	0
T2	610375	610317	0	0
T3	82768	82710	0	0
T4	266866	266764	0	0
T31	233232	233115	0	0
T54	493951	493842	0	0
T58	450658	450546	0	0
T59	131504	131406	0	0
T60	152022	151964	0	0
T119	237771	237647	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	529145477	0	0
T1	219930	219810	0	0
T2	610375	610317	0	0
T3	82768	82710	0	0
T4	266866	266764	0	0
T31	233232	233115	0	0
T54	493951	493842	0	0
T58	450658	450546	0	0
T59	131504	131406	0	0
T60	152022	151964	0	0
T119	237771	237647	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T31	1	1	0	0
T54	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T119	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	529253896	52016	0	0
DepthKnown_A	529253896	529145477	0	0
RvalidKnown_A	529253896	529145477	0	0
WreadyKnown_A	529253896	529145477	0	0
gen_passthru_fifo.paramCheckPass	1027	1027	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	52016	0	0
T1	219930	95	0	0
T2	610375	12	0	0
T3	82768	18	0	0
T4	266866	95	0	0
T31	233232	95	0	0
T54	493951	59	0	0
T58	450658	28	0	0
T59	131504	25	0	0
T60	152022	23	0	0
T119	237771	95	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	529145477	0	0
T1	219930	219810	0	0
T2	610375	610317	0	0
T3	82768	82710	0	0
T4	266866	266764	0	0
T31	233232	233115	0	0
T54	493951	493842	0	0
T58	450658	450546	0	0
T59	131504	131406	0	0
T60	152022	151964	0	0
T119	237771	237647	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	529145477	0	0
T1	219930	219810	0	0
T2	610375	610317	0	0
T3	82768	82710	0	0
T4	266866	266764	0	0
T31	233232	233115	0	0
T54	493951	493842	0	0
T58	450658	450546	0	0
T59	131504	131406	0	0
T60	152022	151964	0	0
T119	237771	237647	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	529145477	0	0
T1	219930	219810	0	0
T2	610375	610317	0	0
T3	82768	82710	0	0
T4	266866	266764	0	0
T31	233232	233115	0	0
T54	493951	493842	0	0
T58	450658	450546	0	0
T59	131504	131406	0	0
T60	152022	151964	0	0
T119	237771	237647	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T31	1	1	0	0
T54	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T119	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	529253896	52016	0	0
DepthKnown_A	529253896	529145477	0	0
RvalidKnown_A	529253896	529145477	0	0
WreadyKnown_A	529253896	529145477	0	0
gen_passthru_fifo.paramCheckPass	1027	1027	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	52016	0	0
T1	219930	95	0	0
T2	610375	12	0	0
T3	82768	18	0	0
T4	266866	95	0	0
T31	233232	95	0	0
T54	493951	59	0	0
T58	450658	28	0	0
T59	131504	25	0	0
T60	152022	23	0	0
T119	237771	95	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	529145477	0	0
T1	219930	219810	0	0
T2	610375	610317	0	0
T3	82768	82710	0	0
T4	266866	266764	0	0
T31	233232	233115	0	0
T54	493951	493842	0	0
T58	450658	450546	0	0
T59	131504	131406	0	0
T60	152022	151964	0	0
T119	237771	237647	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	529145477	0	0
T1	219930	219810	0	0
T2	610375	610317	0	0
T3	82768	82710	0	0
T4	266866	266764	0	0
T31	233232	233115	0	0
T54	493951	493842	0	0
T58	450658	450546	0	0
T59	131504	131406	0	0
T60	152022	151964	0	0
T119	237771	237647	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	529145477	0	0
T1	219930	219810	0	0
T2	610375	610317	0	0
T3	82768	82710	0	0
T4	266866	266764	0	0
T31	233232	233115	0	0
T54	493951	493842	0	0
T58	450658	450546	0	0
T59	131504	131406	0	0
T60	152022	151964	0	0
T119	237771	237647	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T31	1	1	0	0
T54	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T119	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	529253896	13462	0	0
DepthKnown_A	529253896	529145477	0	0
RvalidKnown_A	529253896	529145477	0	0
WreadyKnown_A	529253896	529145477	0	0
gen_passthru_fifo.paramCheckPass	1027	1027	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	13462	0	0
T1	219930	56	0	0
T2	610375	1	0	0
T3	82768	1	0	0
T4	266866	56	0	0
T31	233232	56	0	0
T54	493951	10	0	0
T58	450658	2	0	0
T59	131504	2	0	0
T60	152022	3	0	0
T119	237771	56	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	529145477	0	0
T1	219930	219810	0	0
T2	610375	610317	0	0
T3	82768	82710	0	0
T4	266866	266764	0	0
T31	233232	233115	0	0
T54	493951	493842	0	0
T58	450658	450546	0	0
T59	131504	131406	0	0
T60	152022	151964	0	0
T119	237771	237647	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	529145477	0	0
T1	219930	219810	0	0
T2	610375	610317	0	0
T3	82768	82710	0	0
T4	266866	266764	0	0
T31	233232	233115	0	0
T54	493951	493842	0	0
T58	450658	450546	0	0
T59	131504	131406	0	0
T60	152022	151964	0	0
T119	237771	237647	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	529145477	0	0
T1	219930	219810	0	0
T2	610375	610317	0	0
T3	82768	82710	0	0
T4	266866	266764	0	0
T31	233232	233115	0	0
T54	493951	493842	0	0
T58	450658	450546	0	0
T59	131504	131406	0	0
T60	152022	151964	0	0
T119	237771	237647	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T31	1	1	0	0
T54	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T119	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	529253896	13462	0	0
DepthKnown_A	529253896	529145477	0	0
RvalidKnown_A	529253896	529145477	0	0
WreadyKnown_A	529253896	529145477	0	0
gen_passthru_fifo.paramCheckPass	1027	1027	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	13462	0	0
T1	219930	56	0	0
T2	610375	1	0	0
T3	82768	1	0	0
T4	266866	56	0	0
T31	233232	56	0	0
T54	493951	10	0	0
T58	450658	2	0	0
T59	131504	2	0	0
T60	152022	3	0	0
T119	237771	56	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	529145477	0	0
T1	219930	219810	0	0
T2	610375	610317	0	0
T3	82768	82710	0	0
T4	266866	266764	0	0
T31	233232	233115	0	0
T54	493951	493842	0	0
T58	450658	450546	0	0
T59	131504	131406	0	0
T60	152022	151964	0	0
T119	237771	237647	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	529145477	0	0
T1	219930	219810	0	0
T2	610375	610317	0	0
T3	82768	82710	0	0
T4	266866	266764	0	0
T31	233232	233115	0	0
T54	493951	493842	0	0
T58	450658	450546	0	0
T59	131504	131406	0	0
T60	152022	151964	0	0
T119	237771	237647	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	529253896	529145477	0	0
T1	219930	219810	0	0
T2	610375	610317	0	0
T3	82768	82710	0	0
T4	266866	266764	0	0
T31	233232	233115	0	0
T54	493951	493842	0	0
T58	450658	450546	0	0
T59	131504	131406	0	0
T60	152022	151964	0	0
T119	237771	237647	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T31	1	1	0	0
T54	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T119	1	1	0	0