Unified Coverage Report :: Module :: sram_ctrl

Module : sram_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.64			93.64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sram_ctrl_0.1/rtl/sram_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_sram_ctrl_main	88.91			88.91
tb.dut.top_earlgrey.u_sram_ctrl_ret_aon	94.19			94.19

---

Module Instance : tb.dut.top_earlgrey.u_sram_ctrl_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.91			88.91

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.91			88.91

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.22	92.47		87.18			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_sram_ctrl_ret_aon

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.19			94.19

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.19			94.19

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.22	92.47		87.18			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : sram_ctrl

	Total	Covered	Percent
Totals	66	45	68.18
Total Bits	1164	1090	93.64
Total Bits 0->1	582	545	93.64
Total Bits 1->0	582	545	93.64

Ports	66	45	68.18
Port Bits	1164	1090	93.64
Port Bits 0->1	582	545	93.64
Port Bits 1->0	582	545	93.64

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
clk_otp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_otp_ni	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
ram_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_address[1:0]	No	No		No		INPUT
ram_tl_i.a_address[16:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_address[20:17]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_address[22:21]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_address[27:23]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_address[28]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_address[29]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
ram_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_opcode[1]	No	No		No		INPUT
ram_tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T4,T54	OUTPUT
ram_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_user.rsp_intg[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_user.rsp_intg[3]	No	No		No		OUTPUT
ram_tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
ram_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_sink	No	No		No		OUTPUT
ram_tl_o.d_source[4:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_source[5]	No	No		No		OUTPUT
ram_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_size[0]	No	No		No		OUTPUT
ram_tl_o.d_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T44,T41,T45	Yes	T44,T41,T45	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
regs_tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T44,T41,T45	Yes	T44,T41,T45	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_address[1:0]	No	No		No		INPUT
regs_tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_address[17:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[20:18]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_address[21]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[22]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_address[23]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[24]	Yes	Yes	*T44,*T41,*T45	Yes	T44,T41,T45	INPUT
regs_tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_source[5:0]	Yes	Yes	*T49,*T50,*T51	Yes	T49,T50,T51	INPUT
regs_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[0]	Yes	Yes	*T49,*T52,*T53	Yes	T49,T52,T53	INPUT
regs_tl_i.a_opcode[1]	No	No		No		INPUT
regs_tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_valid	Yes	Yes	T44,T41,T45	Yes	T44,T41,T45	INPUT
regs_tl_o.a_ready	Yes	Yes	T44,T41,T45	Yes	T44,T41,T45	OUTPUT
regs_tl_o.d_error	No	No		No		OUTPUT
regs_tl_o.d_user.data_intg[5:0]	Yes	Yes	*T169,T178,T179	Yes	T169,T178,T179	OUTPUT
regs_tl_o.d_user.data_intg[6]	No	No		No		OUTPUT
regs_tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T41,T169,T178	Yes	T44,T41,T45	OUTPUT
regs_tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
regs_tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T41,T169,T178	Yes	T44,T41,T45	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T41,T169,T178	Yes	T44,T41,T45	OUTPUT
regs_tl_o.d_sink	No	No		No		OUTPUT
regs_tl_o.d_source[0]	No	No		No		OUTPUT
regs_tl_o.d_source[1]	Yes	Yes	*T41,*T169,*T178	Yes	T44,T41,T45	OUTPUT
regs_tl_o.d_source[5:2]	No	No		No		OUTPUT
regs_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_size[0]	No	No		No		OUTPUT
regs_tl_o.d_size[1]	Yes	Yes	T41,T169,T178	Yes	T44,T41,T45	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T169,*T178,*T179	Yes	T169,T209,T178	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T44,T41,T45	Yes	T44,T41,T45	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	OUTPUT
lc_escalate_en_i[3:0]	Yes	Yes	T1,T4,T31	Yes	T1,T4,T31	INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
otp_en_sram_ifetch_i[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T4,T54	INPUT
sram_otp_key_o.req	Yes	Yes	T44,T41,T45	Yes	T44,T41,T45	OUTPUT
sram_otp_key_i.seed_valid	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
sram_otp_key_i.nonce[127:0]	Yes	Yes	T4,T54,T31	Yes	T3,T4,T54	INPUT
sram_otp_key_i.key[127:0]	Yes	Yes	T2,T4,T54	Yes	T2,T4,T54	INPUT
sram_otp_key_i.ack	Yes	Yes	T44,T41,T45	Yes	T44,T41,T45	INPUT
cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
cfg_i.rf_cfg.test	No	No		No		INPUT
cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
cfg_i.ram_cfg.test	No	No		No		INPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_sram_ctrl_main

	Total	Covered	Percent
Totals	62	39	62.90
Total Bits	1136	1010	88.91
Total Bits 0->1	568	505	88.91
Total Bits 1->0	568	505	88.91

Ports	62	39	62.90
Port Bits	1136	1010	88.91
Port Bits 0->1	568	505	88.91
Port Bits 1->0	568	505	88.91

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
clk_otp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_otp_ni	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
ram_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_address[1:0]	No	No		No		INPUT
ram_tl_i.a_address[16:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_address[27:17]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_address[28]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_address[31:29]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_source[4:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_source[5]	No	No		No		INPUT
ram_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_size[0]	No	No		No		INPUT
ram_tl_i.a_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_opcode[1]	No	No		No		INPUT
ram_tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T4,T54	OUTPUT
ram_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_user.rsp_intg[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_user.rsp_intg[3]	No	No		No		OUTPUT
ram_tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
ram_tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_sink	No	No		No		OUTPUT
ram_tl_o.d_source[4:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_source[5]	No	No		No		OUTPUT
ram_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_size[0]	No	No		No		OUTPUT
ram_tl_o.d_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T44,T41,T45	Yes	T44,T41,T45	INPUT
regs_tl_i.a_user.cmd_intg[0]	Yes	Yes	*T44,*T41,*T45	Yes	T44,T41,T45	INPUT
regs_tl_i.a_user.cmd_intg[1]	No	No		No		INPUT
regs_tl_i.a_user.cmd_intg[6:2]	Yes	Yes	T169,T209,T178	Yes	T169,T209,T178	INPUT
regs_tl_i.a_user.instr_type[0]	Yes	Yes	*T44,*T41,*T45	Yes	T44,T41,T45	INPUT
regs_tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
regs_tl_i.a_user.instr_type[3]	Yes	Yes	T44,T41,T45	Yes	T44,T41,T45	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[4:0]	Yes	Yes	*T44,*T41,*T45	Yes	T44,T41,T45	INPUT
regs_tl_i.a_data[6:5]	No	No		No		INPUT
regs_tl_i.a_data[7]	Yes	Yes	*T44,*T41,*T45	Yes	T44,T41,T45	INPUT
regs_tl_i.a_data[31:8]	No	No		No		INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T44,T41,T45	Yes	T44,T41,T45	INPUT
regs_tl_i.a_address[1:0]	No	No		No		INPUT
regs_tl_i.a_address[5:2]	Yes	Yes	*T44,*T41,*T45	Yes	T44,T41,T45	INPUT
regs_tl_i.a_address[17:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[20:18]	Yes	Yes	T44,T41,T45	Yes	T44,T41,T45	INPUT
regs_tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[24]	Yes	Yes	*T44,*T41,*T45	Yes	T44,T41,T45	INPUT
regs_tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[30]	Yes	Yes	*T44,*T41,*T45	Yes	T44,T41,T45	INPUT
regs_tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_source[0]	No	No		No		INPUT
regs_tl_i.a_source[1]	Yes	Yes	*T44,*T41,*T45	Yes	T44,T41,T45	INPUT
regs_tl_i.a_source[5:2]	No	No		No		INPUT
regs_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_size[0]	No	No		No		INPUT
regs_tl_i.a_size[1]	Yes	Yes	T44,T41,T45	Yes	T44,T41,T45	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[1:0]	No	No		No		INPUT
regs_tl_i.a_opcode[2]	Yes	Yes	T169,T209,T178	Yes	T169,T209,T178	INPUT
regs_tl_i.a_valid	Yes	Yes	T44,T41,T45	Yes	T44,T41,T45	INPUT
regs_tl_o.a_ready	Yes	Yes	T44,T41,T45	Yes	T44,T41,T45	OUTPUT
regs_tl_o.d_error	No	No		No		OUTPUT
regs_tl_o.d_user.data_intg[5:0]	Yes	Yes	*T169,*T210,*T211	Yes	T169,T210,T211	OUTPUT
regs_tl_o.d_user.data_intg[6]	No	No		No		OUTPUT
regs_tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T41,T169,T178	Yes	T44,T41,T45	OUTPUT
regs_tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
regs_tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T41,T169,T178	Yes	T44,T41,T45	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T41,T169,T178	Yes	T44,T41,T45	OUTPUT
regs_tl_o.d_sink	No	No		No		OUTPUT
regs_tl_o.d_source[0]	No	No		No		OUTPUT
regs_tl_o.d_source[1]	Yes	Yes	*T41,*T169,*T178	Yes	T44,T41,T45	OUTPUT
regs_tl_o.d_source[5:2]	No	No		No		OUTPUT
regs_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_size[0]	No	No		No		OUTPUT
regs_tl_o.d_size[1]	Yes	Yes	T41,T169,T178	Yes	T44,T41,T45	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T169,*T178,*T179	Yes	T169,T209,T178	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T44,T41,T45	Yes	T44,T41,T45	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	OUTPUT
lc_escalate_en_i[3:0]	Yes	Yes	T1,T4,T31	Yes	T1,T4,T31	INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
otp_en_sram_ifetch_i[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T4,T54	INPUT
sram_otp_key_o.req	Yes	Yes	T44,T41,T45	Yes	T44,T41,T45	OUTPUT
sram_otp_key_i.seed_valid	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
sram_otp_key_i.nonce[127:0]	Yes	Yes	T4,T54,T31	Yes	T3,T4,T54	INPUT
sram_otp_key_i.key[127:0]	Yes	Yes	T2,T4,T54	Yes	T2,T4,T54	INPUT
sram_otp_key_i.ack	Yes	Yes	T44,T41,T45	Yes	T44,T41,T45	INPUT
cfg_i.rf_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.test	No	No		No		INPUT
cfg_i.ram_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.test	No	No		No		INPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_sram_ctrl_ret_aon

	Total	Covered	Percent
Totals	60	42	70.00
Total Bits	1102	1038	94.19
Total Bits 0->1	551	519	94.19
Total Bits 1->0	551	519	94.19

Ports	60	42	70.00
Port Bits	1102	1038	94.19
Port Bits 0->1	551	519	94.19
Port Bits 1->0	551	519	94.19

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T31	Yes	T1,T2,T3	INPUT
clk_otp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_otp_ni	Yes	Yes	T1,T4,T31	Yes	T1,T2,T3	INPUT
ram_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T4,T54	Yes	T1,T4,T54	INPUT
ram_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
ram_tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_address[1:0]	No	No		No		INPUT
ram_tl_i.a_address[11:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_address[20:12]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_address[22:21]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_address[29:23]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_source[5:0]	Yes	Yes	*T49,*T50,*T51	Yes	T49,T50,T51	INPUT
ram_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
ram_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
ram_tl_i.a_opcode[0]	Yes	Yes	*T49,*T52,*T53	Yes	T49,T52,T53	INPUT
ram_tl_i.a_opcode[1]	No	No		No		INPUT
ram_tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ram_tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T4,T31	OUTPUT
ram_tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T4,T54	Yes	T1,T4,T54	OUTPUT
ram_tl_o.d_user.rsp_intg[2:0]	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_user.rsp_intg[3]	No	No		No		OUTPUT
ram_tl_o.d_user.rsp_intg[5:4]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
ram_tl_o.d_data[31:0]	Yes	Yes	T1,T4,T54	Yes	T1,T4,T54	OUTPUT
ram_tl_o.d_sink	No	No		No		OUTPUT
ram_tl_o.d_source[1:0]	Yes	Yes	*T49,*T53,*T190	Yes	T49,T53,T190	OUTPUT
ram_tl_o.d_source[5:2]	No	No		No		OUTPUT
ram_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_size[0]	No	No		No		OUTPUT
ram_tl_o.d_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
ram_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
ram_tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
regs_tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.data_intg[6:0]	Yes	Yes	T44,T41,T45	Yes	T44,T41,T45	INPUT
regs_tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
regs_tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_data[31:0]	Yes	Yes	T44,T41,T45	Yes	T44,T41,T45	INPUT
regs_tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_address[1:0]	No	No		No		INPUT
regs_tl_i.a_address[5:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_address[19:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[20]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_address[21]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[22]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_address[29:23]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_source[5:0]	Yes	Yes	*T49,*T50,*T51	Yes	T49,T50,T51	INPUT
regs_tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
regs_tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_i.a_opcode[0]	Yes	Yes	*T49,*T52,*T53	Yes	T49,T52,T53	INPUT
regs_tl_i.a_opcode[1]	No	No		No		INPUT
regs_tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
regs_tl_i.a_valid	Yes	Yes	T44,T41,T45	Yes	T44,T41,T45	INPUT
regs_tl_o.a_ready	Yes	Yes	T44,T41,T45	Yes	T44,T41,T45	OUTPUT
regs_tl_o.d_error	No	No		No		OUTPUT
regs_tl_o.d_user.data_intg[5:0]	Yes	Yes	*T178,*T179,T131	Yes	T178,T179,T131	OUTPUT
regs_tl_o.d_user.data_intg[6]	No	No		No		OUTPUT
regs_tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T41,T178,T42	Yes	T44,T41,T45	OUTPUT
regs_tl_o.d_user.rsp_intg[3:2]	No	No		No		OUTPUT
regs_tl_o.d_user.rsp_intg[5:4]	Yes	Yes	*T41,*T42,*T43	Yes	T44,T41,T45	OUTPUT
regs_tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
regs_tl_o.d_data[31:0]	Yes	Yes	T41,T178,T42	Yes	T44,T41,T45	OUTPUT
regs_tl_o.d_sink	No	No		No		OUTPUT
regs_tl_o.d_source[0]	No	No		No		OUTPUT
regs_tl_o.d_source[1]	Yes	Yes	*T41,*T178,*T42	Yes	T44,T41,T355	OUTPUT
regs_tl_o.d_source[5:2]	No	No		No		OUTPUT
regs_tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_size[0]	No	No		No		OUTPUT
regs_tl_o.d_size[1]	Yes	Yes	T41,T42,T43	Yes	T44,T41,T45	OUTPUT
regs_tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_opcode[0]	Yes	Yes	*T178,*T179,*T131	Yes	T209,T178,T179	OUTPUT
regs_tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_o.d_valid	Yes	Yes	T44,T41,T45	Yes	T44,T41,T45	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T54,T93,T94	Yes	T54,T93,T94	OUTPUT
lc_escalate_en_i[3:0]	Yes	Yes	T1,T4,T31	Yes	T1,T4,T31	INPUT
lc_hw_debug_en_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
otp_en_sram_ifetch_i[7:0]	Unreachable	Unreachable		Unreachable		INPUT
sram_otp_key_o.req	Yes	Yes	T178,T179,T131	Yes	T178,T179,T131	OUTPUT
sram_otp_key_i.seed_valid	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
sram_otp_key_i.nonce[127:0]	Yes	Yes	T4,T54,T31	Yes	T3,T4,T54	INPUT
sram_otp_key_i.key[127:0]	Yes	Yes	T2,T4,T54	Yes	T2,T4,T54	INPUT
sram_otp_key_i.ack	Yes	Yes	T178,T179,T131	Yes	T178,T179,T131	INPUT
cfg_i.rf_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.rf_cfg.test	No	No		No		INPUT
cfg_i.ram_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
cfg_i.ram_cfg.test	No	No		No		INPUT

*Tests covering at least one bit in the range