Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.03			84.03

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	84.03			84.03

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.03			84.03

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
84.03			84.03

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.22	92.47		87.18			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	309	56.18
Total Bits	6824	5734	84.03
Total Bits 0->1	3412	2867	84.03
Total Bits 1->0	3412	2867	84.03

Ports	550	309	56.18
Port Bits	6824	5734	84.03
Port Bits 0->1	3412	2867	84.03
Port Bits 1->0	3412	2867	84.03

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[5:3]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	No	No		No		INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T31,T187,T188	Yes	T31,T187,T188	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[5:0]	Yes	Yes	*T31,*T187,*T189	Yes	T31,T187,T189	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	No	No		No		OUTPUT
tl_rv_core_ibex__corei_o.d_source[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:3]	No	No		No		OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[0]	No	No		No		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T49,T52,T53	Yes	T49,T52,T53	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T49,T53,T190	Yes	T49,T53,T190	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T49,T53,T190	Yes	T49,T53,T190	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_opcode[1]	No	No		No		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T1,T4,T31	Yes	T1,T4,T31	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[5:0]	Yes	Yes	T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	No	No		No		OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T46,T114,T49	Yes	T46,T114,T49	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.instr_type[0]	Yes	Yes	*T1,*T4,*T54	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_rv_dm__sba_i.a_user.instr_type[3]	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T46,T114,T49	Yes	T46,T114,T49	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	No	No		No		INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[0]	No	No		No		INPUT
tl_rv_dm__sba_i.a_size[1]	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[1:0]	No	No		No		INPUT
tl_rv_dm__sba_i.a_opcode[2]	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T46,T114,T49	Yes	T46,T114,T49	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	No	No		No		OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T46,T114,T49	Yes	T46,T114,T49	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[1:0]	Yes	Yes	T46,T114,T49	Yes	T46,T114,T49	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[2]	No	No		No		OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[5:3]	Yes	Yes	T46,T114,T49	Yes	T46,T114,T49	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T46,T114,T49	Yes	T46,T114,T49	OUTPUT
tl_rv_dm__sba_o.d_sink	No	No		No		OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	No	No		No		OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[0]	No	No		No		OUTPUT
tl_rv_dm__sba_o.d_size[1]	Yes	Yes	T46,T114,T49	Yes	T46,T114,T49	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T46,*T114,*T49	Yes	T46,T114,T49	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T46,T114,T49	Yes	T46,T114,T49	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[1:0]	Yes	Yes	T108	Yes	T108	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[2]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:3]	Yes	Yes	T108	Yes	T108	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[0]	Yes	Yes	*T108	Yes	T108	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:2]	Yes	Yes	T108	Yes	T108	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[0]	Yes	Yes	*T108	Yes	T108	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3]	Yes	Yes	T108	Yes	T108	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[3:0]	Yes	Yes	T108	Yes	T108	OUTPUT
tl_rv_dm__regs_o.a_data[4]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_data[10:5]	Yes	Yes	T108	Yes	T108	OUTPUT
tl_rv_dm__regs_o.a_data[11]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_data[17:12]	Yes	Yes	T108	Yes	T108	OUTPUT
tl_rv_dm__regs_o.a_data[18]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_data[31:19]	Yes	Yes	T108	Yes	T108	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T108	Yes	T108	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[0]	Yes	Yes	*T108	Yes	T108	OUTPUT
tl_rv_dm__regs_o.a_source[5:1]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[0]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_size[1]	Yes	Yes	T108	Yes	T108	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_rv_dm__regs_o.a_opcode[2]	Yes	Yes	T108	Yes	T108	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T108	Yes	T108	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T108	Yes	T108	INPUT
tl_rv_dm__regs_i.d_error	No	No		No		INPUT
tl_rv_dm__regs_i.d_user.data_intg[0]	Yes	Yes	*T108	Yes	T108	INPUT
tl_rv_dm__regs_i.d_user.data_intg[2:1]	No	No		No		INPUT
tl_rv_dm__regs_i.d_user.data_intg[4:3]	Yes	Yes	T108	Yes	T108	INPUT
tl_rv_dm__regs_i.d_user.data_intg[5]	No	No		No		INPUT
tl_rv_dm__regs_i.d_user.data_intg[6]	Yes	Yes	T108	Yes	T108	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[1:0]	Yes	Yes	T108	Yes	T108	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[5:4]	Yes	Yes	T108	Yes	T108	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T108	Yes	T108	INPUT
tl_rv_dm__regs_i.d_sink	No	No		No		INPUT
tl_rv_dm__regs_i.d_source[0]	Yes	Yes	*T108	Yes	T108	INPUT
tl_rv_dm__regs_i.d_source[5:1]	No	No		No		INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[0]	No	No		No		INPUT
tl_rv_dm__regs_i.d_size[1]	Yes	Yes	T108	Yes	T108	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T108	Yes	T108	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T108	Yes	T108	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T191,T51,T192	Yes	T191,T51,T192	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T191,T51,T192	Yes	T191,T51,T192	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T191,T51,T192	Yes	T191,T51,T192	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T191,T51,T192	Yes	T191,T51,T192	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T191,T51,T192	Yes	T191,T51,T192	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[4:0]	Yes	Yes	*T191,*T51,*T192	Yes	T191,T51,T192	OUTPUT
tl_rv_dm__mem_o.a_source[5]	No	No		No		OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[0]	No	No		No		OUTPUT
tl_rv_dm__mem_o.a_size[1]	Yes	Yes	T191,T51,T192	Yes	T191,T51,T192	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_rv_dm__mem_o.a_opcode[2]	Yes	Yes	T191,T51,T192	Yes	T191,T51,T192	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T191,T51,T192	Yes	T191,T51,T192	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T4,T54	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T191,T51,T192	Yes	T191,T51,T192	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[2:0]	Yes	Yes	*T191,*T51,*T192	Yes	T191,T51,T192	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[3]	No	No		No		INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[5:4]	Yes	Yes	*T192,*T193,*T108	Yes	T191,T51,T192	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T4,T54	INPUT
tl_rv_dm__mem_i.d_sink	No	No		No		INPUT
tl_rv_dm__mem_i.d_source[4:0]	Yes	Yes	*T191,*T51,*T192	Yes	T191,T51,T192	INPUT
tl_rv_dm__mem_i.d_source[5]	No	No		No		INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[0]	No	No		No		INPUT
tl_rv_dm__mem_i.d_size[1]	Yes	Yes	T192,T193,T108	Yes	T191,T51,T192	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T4,T54	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T191,T51,T192	Yes	T191,T51,T192	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T44,T46,T41	Yes	T44,T46,T41	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T44,T41,T45	Yes	T44,T41,T45	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[4:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[5]	No	No		No		OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[0]	No	No		No		OUTPUT
tl_rom_ctrl__rom_o.a_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[4]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:5]	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_source[4:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[5]	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[0]	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	No	No		No		INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T6,T194,T102	Yes	T6,T194,T102	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[0]	Yes	Yes	*T6,*T194,*T102	Yes	T6,T194,T102	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3]	Yes	Yes	T6,T194,T102	Yes	T6,T194,T102	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T102,T103,T104	Yes	T102,T103,T104	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T6,T194,T102	Yes	T6,T194,T102	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[1:0]	Yes	Yes	*T108,*T6,*T194	Yes	T108,T6,T194	OUTPUT
tl_rom_ctrl__regs_o.a_source[5:2]	No	No		No		OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[0]	No	No		No		OUTPUT
tl_rom_ctrl__regs_o.a_size[1]	Yes	Yes	T6,T194,T102	Yes	T6,T194,T102	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2]	Yes	Yes	T6,T194,T129	Yes	T6,T194,T129	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T6,T194,T102	Yes	T6,T194,T102	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T6,T194,T102	Yes	T6,T194,T102	INPUT
tl_rom_ctrl__regs_i.d_error	No	No		No		INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T6,T129,T195	Yes	T6,T129,T195	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[1:0]	Yes	Yes	T108,*T102,*T103	Yes	T102,T103,T104	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[5:4]	Yes	Yes	T6,T194,T108	Yes	T6,T194,T102	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T6,T129,T195	Yes	T6,T102,T129	INPUT
tl_rom_ctrl__regs_i.d_sink	No	No		No		INPUT
tl_rom_ctrl__regs_i.d_source[1:0]	Yes	Yes	*T108,*T6,*T194	Yes	T108,T6,T194	INPUT
tl_rom_ctrl__regs_i.d_source[5:2]	No	No		No		INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[0]	No	No		No		INPUT
tl_rom_ctrl__regs_i.d_size[1]	Yes	Yes	T6,T194,T108	Yes	T6,T194,T102	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T6,*T194,*T108	Yes	T6,T194,T129	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T6,T194,T102	Yes	T6,T194,T102	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_peri_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T49,*T50,*T51	Yes	T49,T50,T51	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[0]	Yes	Yes	*T49,*T52,*T53	Yes	T49,T52,T53	OUTPUT
tl_peri_o.a_opcode[1]	No	No		No		OUTPUT
tl_peri_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T1,T187,T196	Yes	T1,T187,T196	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	No	No		No		INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T49,*T50,*T157	Yes	T49,T50,T51	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T11,T150,T12	Yes	T11,T150,T12	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T11,T12,T91	Yes	T11,T12,T91	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[0]	Yes	Yes	*T11,*T150,*T12	Yes	T11,T150,T12	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:2]	Yes	Yes	T11,T150,T12	Yes	T11,T150,T12	OUTPUT
tl_spi_host0_o.a_user.instr_type[0]	Yes	Yes	*T11,*T150,*T12	Yes	T11,T150,T12	OUTPUT
tl_spi_host0_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_spi_host0_o.a_user.instr_type[3]	Yes	Yes	T11,T150,T12	Yes	T11,T150,T12	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T11,T12,T91	Yes	T11,T12,T91	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T11,T150,T12	Yes	T11,T150,T12	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[0]	No	No		No		OUTPUT
tl_spi_host0_o.a_source[1]	Yes	Yes	*T11,*T150,*T12	Yes	T11,T150,T12	OUTPUT
tl_spi_host0_o.a_source[5:2]	No	No		No		OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[0]	No	No		No		OUTPUT
tl_spi_host0_o.a_size[1]	Yes	Yes	T11,T150,T12	Yes	T11,T150,T12	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[0]	Yes	Yes	*T12,*T13,*T97	Yes	T12,T13,T97	OUTPUT
tl_spi_host0_o.a_opcode[1]	No	No		No		OUTPUT
tl_spi_host0_o.a_opcode[2]	Yes	Yes	T11,T150,T12	Yes	T11,T150,T12	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T11,T150,T12	Yes	T11,T150,T12	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T11,T150,T12	Yes	T11,T150,T12	INPUT
tl_spi_host0_i.d_error	No	No		No		INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T11,T12,T91	Yes	T11,T12,T91	INPUT
tl_spi_host0_i.d_user.rsp_intg[1:0]	Yes	Yes	T11,T150,T12	Yes	T11,T150,T12	INPUT
tl_spi_host0_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_spi_host0_i.d_user.rsp_intg[5:4]	Yes	Yes	T11,T150,T12	Yes	T11,T150,T12	INPUT
tl_spi_host0_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T11,T12,T91	Yes	T11,T12,T91	INPUT
tl_spi_host0_i.d_sink	No	No		No		INPUT
tl_spi_host0_i.d_source[0]	No	No		No		INPUT
tl_spi_host0_i.d_source[1]	Yes	Yes	*T11,*T150,*T12	Yes	T11,T150,T12	INPUT
tl_spi_host0_i.d_source[5:2]	No	No		No		INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[0]	No	No		No		INPUT
tl_spi_host0_i.d_size[1]	Yes	Yes	T11,T150,T12	Yes	T11,T150,T12	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T11,*T150,*T12	Yes	T11,T150,T12	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T11,T150,T12	Yes	T11,T150,T12	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T150,T91,T141	Yes	T150,T91,T141	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T91,T141,T98	Yes	T91,T141,T98	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T150,T91,T141	Yes	T150,T91,T141	OUTPUT
tl_spi_host1_o.a_user.instr_type[0]	Yes	Yes	*T150,*T91,*T141	Yes	T150,T91,T141	OUTPUT
tl_spi_host1_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_spi_host1_o.a_user.instr_type[3]	Yes	Yes	T150,T91,T141	Yes	T150,T91,T141	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T91,T141,T98	Yes	T91,T141,T98	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T150,T91,T141	Yes	T150,T91,T141	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[0]	No	No		No		OUTPUT
tl_spi_host1_o.a_source[1]	Yes	Yes	*T150,*T91,*T141	Yes	T150,T91,T141	OUTPUT
tl_spi_host1_o.a_source[5:2]	No	No		No		OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[0]	No	No		No		OUTPUT
tl_spi_host1_o.a_size[1]	Yes	Yes	T150,T91,T141	Yes	T150,T91,T141	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_spi_host1_o.a_opcode[2]	Yes	Yes	T150,T91,T141	Yes	T150,T91,T141	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T150,T91,T141	Yes	T150,T91,T141	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T150,T91,T141	Yes	T150,T91,T141	INPUT
tl_spi_host1_i.d_error	No	No		No		INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T91,T141,T98	Yes	T91,T141,T98	INPUT
tl_spi_host1_i.d_user.rsp_intg[1:0]	Yes	Yes	T150,T91,T141	Yes	T150,T91,T141	INPUT
tl_spi_host1_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_spi_host1_i.d_user.rsp_intg[5:4]	Yes	Yes	T150,T91,T141	Yes	T150,T91,T141	INPUT
tl_spi_host1_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T91,T141,T98	Yes	T91,T141,T98	INPUT
tl_spi_host1_i.d_sink	No	No		No		INPUT
tl_spi_host1_i.d_source[0]	No	No		No		INPUT
tl_spi_host1_i.d_source[1]	Yes	Yes	*T150,*T91,*T141	Yes	T150,T91,T141	INPUT
tl_spi_host1_i.d_source[5:2]	No	No		No		INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[0]	No	No		No		INPUT
tl_spi_host1_i.d_size[1]	Yes	Yes	T150,T91,T141	Yes	T150,T91,T141	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T150,*T91,*T141	Yes	T150,T91,T141	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T150,T91,T141	Yes	T150,T91,T141	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T2,T149,T117	Yes	T2,T149,T117	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T2,T149,T117	Yes	T2,T149,T117	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T149,T117	Yes	T2,T149,T117	OUTPUT
tl_usbdev_o.a_user.instr_type[0]	Yes	Yes	*T2,*T149,*T117	Yes	T2,T149,T117	OUTPUT
tl_usbdev_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_usbdev_o.a_user.instr_type[3]	Yes	Yes	T2,T149,T117	Yes	T2,T149,T117	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T2,T149,T117	Yes	T2,T149,T117	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T2,T149,T117	Yes	T2,T149,T117	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[1:0]	Yes	Yes	*T108,*T2,*T149	Yes	T108,T2,T149	OUTPUT
tl_usbdev_o.a_source[5:2]	No	No		No		OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[0]	No	No		No		OUTPUT
tl_usbdev_o.a_size[1]	Yes	Yes	T2,T149,T117	Yes	T2,T149,T117	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_usbdev_o.a_opcode[2]	Yes	Yes	T2,T149,T117	Yes	T2,T149,T117	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T2,T149,T117	Yes	T2,T149,T117	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T2,T149,T117	Yes	T2,T149,T117	INPUT
tl_usbdev_i.d_error	No	No		No		INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T2,T149,T150	Yes	T2,T149,T150	INPUT
tl_usbdev_i.d_user.rsp_intg[1:0]	Yes	Yes	T2,T149,T117	Yes	T2,T149,T117	INPUT
tl_usbdev_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_usbdev_i.d_user.rsp_intg[5:4]	Yes	Yes	T2,T150,T91	Yes	T2,T149,T117	INPUT
tl_usbdev_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T2,T149,T117	Yes	T2,T149,T150	INPUT
tl_usbdev_i.d_sink	No	No		No		INPUT
tl_usbdev_i.d_source[1:0]	Yes	Yes	*T108,*T2,*T149	Yes	T108,T2,T149	INPUT
tl_usbdev_i.d_source[5:2]	No	No		No		INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[0]	No	No		No		INPUT
tl_usbdev_i.d_size[1]	Yes	Yes	T2,T150,T91	Yes	T2,T149,T117	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T2,*T149,*T117	Yes	T2,T149,T150	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T2,T149,T117	Yes	T2,T149,T117	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[1:0]	Yes	Yes	*T52,*T1,*T2	Yes	T52,T1,T2	OUTPUT
tl_flash_ctrl__core_o.a_source[5:2]	No	No		No		OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[0]	No	No		No		OUTPUT
tl_flash_ctrl__core_o.a_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T4,T54	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[3]	No	No		No		INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[5:4]	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T4,T54	INPUT
tl_flash_ctrl__core_i.d_sink	No	No		No		INPUT
tl_flash_ctrl__core_i.d_source[1:0]	Yes	Yes	*T52,*T1,*T2	Yes	T52,T1,T2	INPUT
tl_flash_ctrl__core_i.d_source[5:2]	No	No		No		INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[0]	No	No		No		INPUT
tl_flash_ctrl__core_i.d_size[1]	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T52	Yes	T52	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T52	Yes	T52	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[0]	Yes	Yes	*T52	Yes	T52	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3]	Yes	Yes	T52	Yes	T52	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T52	Yes	T52	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T52	Yes	T52	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[0]	Yes	Yes	*T52	Yes	T52	OUTPUT
tl_flash_ctrl__prim_o.a_source[5:1]	No	No		No		OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[0]	No	No		No		OUTPUT
tl_flash_ctrl__prim_o.a_size[1]	Yes	Yes	T52	Yes	T52	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2]	Yes	Yes	T52	Yes	T52	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T52	Yes	T52	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T52	Yes	T52	INPUT
tl_flash_ctrl__prim_i.d_error	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T52	Yes	T52	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[1:0]	Yes	Yes	T52	Yes	T52	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[5:4]	Yes	Yes	T52	Yes	T52	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T52	Yes	T52	INPUT
tl_flash_ctrl__prim_i.d_sink	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_source[0]	Yes	Yes	*T52	Yes	T52	INPUT
tl_flash_ctrl__prim_i.d_source[5:1]	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[0]	No	No		No		INPUT
tl_flash_ctrl__prim_i.d_size[1]	Yes	Yes	T52	Yes	T52	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T52	Yes	T52	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T52	Yes	T52	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_source[1]	No	No		No		OUTPUT
tl_flash_ctrl__mem_o.a_source[4:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_source[5]	No	No		No		OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[0]	No	No		No		OUTPUT
tl_flash_ctrl__mem_o.a_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T4,T54	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[3]	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[4]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:5]	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_sink	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_source[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_source[1]	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_source[4:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_source[5]	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[0]	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	No	No		No		INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_hmac_o.d_ready	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T44,T197,T41	Yes	T44,T197,T41	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T44,T197,T41	Yes	T44,T197,T41	OUTPUT
tl_hmac_o.a_user.instr_type[0]	Yes	Yes	*T44,*T197,*T41	Yes	T44,T197,T41	OUTPUT
tl_hmac_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_hmac_o.a_user.instr_type[3]	Yes	Yes	T44,T197,T41	Yes	T44,T197,T41	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T44,T197,T41	Yes	T44,T197,T41	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T44,T197,T41	Yes	T44,T197,T41	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[1:0]	Yes	Yes	*T52,*T44,*T197	Yes	T52,T44,T197	OUTPUT
tl_hmac_o.a_source[5:2]	No	No		No		OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[0]	No	No		No		OUTPUT
tl_hmac_o.a_size[1]	Yes	Yes	T44,T197,T41	Yes	T44,T197,T41	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[0]	Yes	Yes	*T197,*T198,*T199	Yes	T197,T198,T199	OUTPUT
tl_hmac_o.a_opcode[1]	No	No		No		OUTPUT
tl_hmac_o.a_opcode[2]	Yes	Yes	T44,T197,T41	Yes	T44,T197,T41	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T44,T197,T41	Yes	T44,T197,T41	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T44,T197,T41	Yes	T44,T197,T41	INPUT
tl_hmac_i.d_error	No	No		No		INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T44,T197,T41	Yes	T44,T197,T41	INPUT
tl_hmac_i.d_user.rsp_intg[1:0]	Yes	Yes	T44,T197,T41	Yes	T44,T197,T41	INPUT
tl_hmac_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_hmac_i.d_user.rsp_intg[5:4]	Yes	Yes	T44,T197,T41	Yes	T44,T197,T41	INPUT
tl_hmac_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T44,T197,T41	Yes	T44,T197,T41	INPUT
tl_hmac_i.d_sink	No	No		No		INPUT
tl_hmac_i.d_source[1:0]	Yes	Yes	*T52,*T44,*T197	Yes	T52,T44,T197	INPUT
tl_hmac_i.d_source[5:2]	No	No		No		INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[0]	No	No		No		INPUT
tl_hmac_i.d_size[1]	Yes	Yes	T44,T197,T41	Yes	T44,T197,T41	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T44,*T197,*T41	Yes	T44,T197,T41	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T44,T197,T41	Yes	T44,T197,T41	INPUT
tl_kmac_o.d_ready	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T200,T69,T201	Yes	T200,T69,T201	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T31,T200,T69	Yes	T31,T200,T69	OUTPUT
tl_kmac_o.a_user.instr_type[0]	Yes	Yes	*T31,*T200,*T69	Yes	T31,T200,T69	OUTPUT
tl_kmac_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_kmac_o.a_user.instr_type[3]	Yes	Yes	T31,T200,T69	Yes	T31,T200,T69	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T200,T69,T201	Yes	T200,T69,T201	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T31,T200,T69	Yes	T31,T200,T69	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[1:0]	Yes	Yes	*T52,*T101,*T31	Yes	T52,T101,T31	OUTPUT
tl_kmac_o.a_source[5:2]	No	No		No		OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[0]	No	No		No		OUTPUT
tl_kmac_o.a_size[1]	Yes	Yes	T31,T200,T69	Yes	T31,T200,T69	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[0]	Yes	Yes	*T200,*T201,*T202	Yes	T200,T201,T202	OUTPUT
tl_kmac_o.a_opcode[1]	No	No		No		OUTPUT
tl_kmac_o.a_opcode[2]	Yes	Yes	T31,T200,T69	Yes	T31,T200,T69	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T31,T200,T69	Yes	T31,T200,T69	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T31,T200,T69	Yes	T31,T200,T69	INPUT
tl_kmac_i.d_error	No	No		No		INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T200,T69,T201	Yes	T31,T200,T69	INPUT
tl_kmac_i.d_user.rsp_intg[1:0]	Yes	Yes	T31,T200,T69	Yes	T31,T200,T69	INPUT
tl_kmac_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_kmac_i.d_user.rsp_intg[5:4]	Yes	Yes	*T31,T200,T201	Yes	T31,T200,T69	INPUT
tl_kmac_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T31,T200,T69	Yes	T31,T200,T201	INPUT
tl_kmac_i.d_sink	No	No		No		INPUT
tl_kmac_i.d_source[1:0]	Yes	Yes	*T52,*T101,*T31	Yes	T52,T101,T31	INPUT
tl_kmac_i.d_source[5:2]	No	No		No		INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[0]	No	No		No		INPUT
tl_kmac_i.d_size[1]	Yes	Yes	T31,T200,T201	Yes	T31,T200,T69	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T200,*T69,*T201	Yes	T200,T201,T202	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T31,T200,T69	Yes	T31,T200,T69	INPUT
tl_aes_o.d_ready	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T203,T70,T68	Yes	T203,T70,T68	OUTPUT
tl_aes_o.a_user.cmd_intg[0]	Yes	Yes	*T203,*T70,*T68	Yes	T203,T70,T68	OUTPUT
tl_aes_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_aes_o.a_user.cmd_intg[6:2]	Yes	Yes	T203,T61,T70	Yes	T203,T61,T70	OUTPUT
tl_aes_o.a_user.instr_type[0]	Yes	Yes	*T203,*T61,*T70	Yes	T203,T61,T70	OUTPUT
tl_aes_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_aes_o.a_user.instr_type[3]	Yes	Yes	T203,T61,T70	Yes	T203,T61,T70	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T203,T70,T68	Yes	T203,T70,T68	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T203,T61,T70	Yes	T203,T61,T70	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[0]	No	No		No		OUTPUT
tl_aes_o.a_source[1]	Yes	Yes	*T203,*T61,*T70	Yes	T203,T61,T70	OUTPUT
tl_aes_o.a_source[5:2]	No	No		No		OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[0]	No	No		No		OUTPUT
tl_aes_o.a_size[1]	Yes	Yes	T203,T61,T70	Yes	T203,T61,T70	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_aes_o.a_opcode[2]	Yes	Yes	T203,T61,T70	Yes	T203,T61,T70	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T203,T61,T70	Yes	T203,T61,T70	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T203,T61,T70	Yes	T203,T61,T70	INPUT
tl_aes_i.d_error	No	No		No		INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T203,T61,T70	Yes	T203,T61,T70	INPUT
tl_aes_i.d_user.rsp_intg[1:0]	Yes	Yes	T203,T61,T70	Yes	T203,T61,T70	INPUT
tl_aes_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_aes_i.d_user.rsp_intg[5:4]	Yes	Yes	T204,T205,*T206	Yes	T203,T61,T70	INPUT
tl_aes_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T203,T61,T70	Yes	T203,T61,T70	INPUT
tl_aes_i.d_sink	No	No		No		INPUT
tl_aes_i.d_source[0]	No	No		No		INPUT
tl_aes_i.d_source[1]	Yes	Yes	*T203,*T61,*T70	Yes	T203,T61,T70	INPUT
tl_aes_i.d_source[5:2]	No	No		No		INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[0]	No	No		No		INPUT
tl_aes_i.d_size[1]	Yes	Yes	T204,T205,T206	Yes	T203,T61,T70	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T203,*T61,*T70	Yes	T203,T61,T70	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T203,T61,T70	Yes	T203,T61,T70	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_entropy_src_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[1:0]	Yes	Yes	*T52,*T1,*T2	Yes	T52,T1,T2	OUTPUT
tl_entropy_src_o.a_source[5:2]	No	No		No		OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[0]	No	No		No		OUTPUT
tl_entropy_src_o.a_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_entropy_src_o.a_opcode[2]	Yes	Yes	T69,T61,T70	Yes	T69,T61,T70	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	No	No		No		INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T69,T61,T70	Yes	T69,T61,T70	INPUT
tl_entropy_src_i.d_user.rsp_intg[1:0]	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_entropy_src_i.d_user.rsp_intg[5:4]	Yes	Yes	*T1,*T4,*T54	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	No	No		No		INPUT
tl_entropy_src_i.d_source[1:0]	Yes	Yes	*T52,*T1,*T4	Yes	T52,T1,T2	INPUT
tl_entropy_src_i.d_source[5:2]	No	No		No		INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[0]	No	No		No		INPUT
tl_entropy_src_i.d_size[1]	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T69,*T61,*T70	Yes	T69,T61,T70	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_csrng_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T69,T61,T70	Yes	T69,T61,T70	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[1:0]	Yes	Yes	*T52,*T69,*T61	Yes	T52,T69,T61	OUTPUT
tl_csrng_o.a_source[5:2]	No	No		No		OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[0]	No	No		No		OUTPUT
tl_csrng_o.a_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_csrng_o.a_opcode[2]	Yes	Yes	T69,T61,T70	Yes	T69,T61,T70	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	No	No		No		INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T69,T61,T70	Yes	T69,T61,T70	INPUT
tl_csrng_i.d_user.rsp_intg[1:0]	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_csrng_i.d_user.rsp_intg[5:4]	Yes	Yes	*T1,*T4,*T54	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	No	No		No		INPUT
tl_csrng_i.d_source[1:0]	Yes	Yes	*T52,*T69,*T61	Yes	T52,T69,T61	INPUT
tl_csrng_i.d_source[5:2]	No	No		No		INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[0]	No	No		No		INPUT
tl_csrng_i.d_size[1]	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T69,*T61,*T70	Yes	T69,T61,T70	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T69,T61,T70	Yes	T69,T61,T70	OUTPUT
tl_edn0_o.a_user.cmd_intg[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_edn0_o.a_user.cmd_intg[6:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_edn0_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T69,T61,T70	Yes	T69,T61,T70	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[1:0]	Yes	Yes	*T52,*T1,*T2	Yes	T52,T1,T2	OUTPUT
tl_edn0_o.a_source[5:2]	No	No		No		OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[0]	No	No		No		OUTPUT
tl_edn0_o.a_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_edn0_o.a_opcode[2]	Yes	Yes	T69,T61,T70	Yes	T69,T61,T70	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	No	No		No		INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T69,T61,T70	Yes	T69,T61,T70	INPUT
tl_edn0_i.d_user.rsp_intg[1:0]	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_edn0_i.d_user.rsp_intg[5:4]	Yes	Yes	*T1,*T4,*T54	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	No	No		No		INPUT
tl_edn0_i.d_source[1:0]	Yes	Yes	*T52,*T1,*T4	Yes	T52,T1,T2	INPUT
tl_edn0_i.d_source[5:2]	No	No		No		INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[0]	No	No		No		INPUT
tl_edn0_i.d_size[1]	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T69,*T61,*T70	Yes	T69,T61,T70	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T69,T61,T70	Yes	T69,T61,T70	OUTPUT
tl_edn1_o.a_user.cmd_intg[0]	Yes	Yes	*T69,*T61,*T70	Yes	T69,T61,T70	OUTPUT
tl_edn1_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_edn1_o.a_user.cmd_intg[6:2]	Yes	Yes	T69,T61,T70	Yes	T69,T61,T70	OUTPUT
tl_edn1_o.a_user.instr_type[0]	Yes	Yes	*T69,*T61,*T70	Yes	T69,T61,T70	OUTPUT
tl_edn1_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_edn1_o.a_user.instr_type[3]	Yes	Yes	T69,T61,T70	Yes	T69,T61,T70	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T69,T61,T70	Yes	T69,T61,T70	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T69,T61,T70	Yes	T69,T61,T70	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[1:0]	Yes	Yes	*T52,*T69,*T61	Yes	T52,T69,T61	OUTPUT
tl_edn1_o.a_source[5:2]	No	No		No		OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[0]	No	No		No		OUTPUT
tl_edn1_o.a_size[1]	Yes	Yes	T69,T61,T70	Yes	T69,T61,T70	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_edn1_o.a_opcode[2]	Yes	Yes	T69,T61,T70	Yes	T69,T61,T70	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T69,T61,T70	Yes	T69,T61,T70	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T69,T61,T70	Yes	T69,T61,T70	INPUT
tl_edn1_i.d_error	No	No		No		INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T69,T61,T70	Yes	T69,T61,T70	INPUT
tl_edn1_i.d_user.rsp_intg[1:0]	Yes	Yes	T69,T61,T70	Yes	T69,T61,T70	INPUT
tl_edn1_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_edn1_i.d_user.rsp_intg[5:4]	Yes	Yes	T63,*T65,*T207	Yes	T69,T61,T70	INPUT
tl_edn1_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T69,T61,T70	Yes	T69,T61,T70	INPUT
tl_edn1_i.d_sink	No	No		No		INPUT
tl_edn1_i.d_source[1:0]	Yes	Yes	*T52,*T69,*T61	Yes	T52,T69,T61	INPUT
tl_edn1_i.d_source[5:2]	No	No		No		INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[0]	No	No		No		INPUT
tl_edn1_i.d_size[1]	Yes	Yes	T63,T65,T207	Yes	T69,T61,T70	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T69,*T61,*T70	Yes	T69,T61,T70	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T69,T61,T70	Yes	T69,T61,T70	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T1,T4,T54	Yes	T1,T4,T54	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T4,T54	Yes	T1,T4,T54	OUTPUT
tl_rv_plic_o.a_user.instr_type[0]	Yes	Yes	*T1,*T4,*T54	Yes	T1,T4,T54	OUTPUT
tl_rv_plic_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_rv_plic_o.a_user.instr_type[3]	Yes	Yes	T1,T4,T54	Yes	T1,T4,T54	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T1,T4,T54	Yes	T1,T4,T54	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T1,T4,T54	Yes	T1,T4,T54	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[0]	No	No		No		OUTPUT
tl_rv_plic_o.a_source[1]	Yes	Yes	*T1,*T4,*T54	Yes	T1,T4,T54	OUTPUT
tl_rv_plic_o.a_source[5:2]	No	No		No		OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[0]	No	No		No		OUTPUT
tl_rv_plic_o.a_size[1]	Yes	Yes	T1,T4,T54	Yes	T1,T4,T54	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_rv_plic_o.a_opcode[2]	Yes	Yes	T1,T4,T54	Yes	T1,T4,T54	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T1,T4,T54	Yes	T1,T4,T54	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T1,T4,T54	Yes	T1,T4,T54	INPUT
tl_rv_plic_i.d_error	No	No		No		INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T1,T4,T54	Yes	T1,T4,T54	INPUT
tl_rv_plic_i.d_user.rsp_intg[1:0]	Yes	Yes	T1,T4,T54	Yes	T1,T4,T54	INPUT
tl_rv_plic_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_rv_plic_i.d_user.rsp_intg[5:4]	Yes	Yes	T1,T4,T54	Yes	T1,T4,T54	INPUT
tl_rv_plic_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T1,T4,T54	Yes	T1,T4,T54	INPUT
tl_rv_plic_i.d_sink	No	No		No		INPUT
tl_rv_plic_i.d_source[0]	No	No		No		INPUT
tl_rv_plic_i.d_source[1]	Yes	Yes	*T1,*T4,*T54	Yes	T1,T4,T54	INPUT
tl_rv_plic_i.d_source[5:2]	No	No		No		INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[0]	No	No		No		INPUT
tl_rv_plic_i.d_size[1]	Yes	Yes	T1,T4,T54	Yes	T1,T4,T54	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T1,*T4,*T54	Yes	T1,T4,T54	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T1,T4,T54	Yes	T1,T4,T54	INPUT
tl_otbn_o.d_ready	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T61,T68,T44	Yes	T61,T68,T44	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T61,T68,T44	Yes	T61,T68,T44	OUTPUT
tl_otbn_o.a_user.instr_type[0]	Yes	Yes	*T61,*T68,*T44	Yes	T61,T68,T44	OUTPUT
tl_otbn_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_otbn_o.a_user.instr_type[3]	Yes	Yes	T61,T68,T44	Yes	T61,T68,T44	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T61,T68,T44	Yes	T61,T68,T44	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T61,T68,T44	Yes	T61,T68,T44	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[1:0]	Yes	Yes	*T49,*T53,*T101	Yes	T49,T53,T101	OUTPUT
tl_otbn_o.a_source[5:2]	No	No		No		OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[0]	No	No		No		OUTPUT
tl_otbn_o.a_size[1]	Yes	Yes	T61,T68,T44	Yes	T61,T68,T44	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_otbn_o.a_opcode[2]	Yes	Yes	T61,T68,T44	Yes	T61,T68,T44	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T61,T68,T44	Yes	T61,T68,T44	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T61,T68,T44	Yes	T61,T68,T44	INPUT
tl_otbn_i.d_error	No	No		No		INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T61,T68,T44	Yes	T61,T68,T44	INPUT
tl_otbn_i.d_user.rsp_intg[1:0]	Yes	Yes	T61,T68,T44	Yes	T61,T68,T44	INPUT
tl_otbn_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_otbn_i.d_user.rsp_intg[5:4]	Yes	Yes	T61,T68,T44	Yes	T61,T68,T44	INPUT
tl_otbn_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T61,T68,T44	Yes	T61,T68,T44	INPUT
tl_otbn_i.d_sink	No	No		No		INPUT
tl_otbn_i.d_source[1:0]	Yes	Yes	*T49,*T53,*T101	Yes	T49,T53,T101	INPUT
tl_otbn_i.d_source[5:2]	No	No		No		INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[0]	No	No		No		INPUT
tl_otbn_i.d_size[1]	Yes	Yes	T61,T68,T44	Yes	T61,T68,T44	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T61,*T68,*T44	Yes	T61,T68,T44	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T61,T68,T44	Yes	T61,T68,T44	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T69,T44,T45	Yes	T69,T44,T45	OUTPUT
tl_keymgr_o.a_user.cmd_intg[0]	Yes	Yes	*T69,*T44,*T45	Yes	T69,T44,T45	OUTPUT
tl_keymgr_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:2]	Yes	Yes	T69,T44,T45	Yes	T69,T44,T45	OUTPUT
tl_keymgr_o.a_user.instr_type[0]	Yes	Yes	*T69,*T44,*T45	Yes	T69,T44,T45	OUTPUT
tl_keymgr_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_keymgr_o.a_user.instr_type[3]	Yes	Yes	T69,T44,T45	Yes	T69,T44,T45	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T69,T175,T172	Yes	T69,T175,T172	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T69,T44,T45	Yes	T69,T44,T45	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[1:0]	Yes	Yes	*T52,*T69,*T44	Yes	T52,T69,T44	OUTPUT
tl_keymgr_o.a_source[5:2]	No	No		No		OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[0]	No	No		No		OUTPUT
tl_keymgr_o.a_size[1]	Yes	Yes	T69,T44,T45	Yes	T69,T44,T45	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_keymgr_o.a_opcode[2]	Yes	Yes	T69,T44,T45	Yes	T69,T44,T45	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T69,T44,T45	Yes	T69,T44,T45	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T69,T44,T45	Yes	T69,T44,T45	INPUT
tl_keymgr_i.d_error	No	No		No		INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T69,T45,T175	Yes	T69,T45,T175	INPUT
tl_keymgr_i.d_user.rsp_intg[1:0]	Yes	Yes	T69,T44,T45	Yes	T69,T44,T45	INPUT
tl_keymgr_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_keymgr_i.d_user.rsp_intg[5:4]	Yes	Yes	T172,*T145,*T42	Yes	T69,T44,T45	INPUT
tl_keymgr_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T69,T44,T45	Yes	T69,T44,T45	INPUT
tl_keymgr_i.d_sink	No	No		No		INPUT
tl_keymgr_i.d_source[1:0]	Yes	Yes	*T52,*T69,*T44	Yes	T52,T69,T44	INPUT
tl_keymgr_i.d_source[5:2]	No	No		No		INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[0]	No	No		No		INPUT
tl_keymgr_i.d_size[1]	Yes	Yes	T172,T145,T42	Yes	T69,T44,T45	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T69,*T44,*T45	Yes	T69,T44,T45	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T69,T44,T45	Yes	T69,T44,T45	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[1:0]	Yes	Yes	*T208,*T108,*T1	Yes	T208,T108,T1	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:2]	No	No		No		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[0]	No	No		No		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T108	Yes	T108	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T1,T4,T54	Yes	T1,T4,T54	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[2:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[3]	No	No		No		INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[5:4]	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T1,T4,T54	Yes	T1,T4,T54	INPUT
tl_rv_core_ibex__cfg_i.d_sink	No	No		No		INPUT
tl_rv_core_ibex__cfg_i.d_source[1:0]	Yes	Yes	*T108,*T1,*T2	Yes	T208,T108,T1	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:2]	No	No		No		INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[0]	No	No		No		INPUT
tl_rv_core_ibex__cfg_i.d_size[1]	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T1,T4,T54	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T44,T41,T45	Yes	T44,T41,T45	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[0]	Yes	Yes	*T44,*T41,*T45	Yes	T44,T41,T45	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[1]	No	No		No		OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:2]	Yes	Yes	T169,T209,T178	Yes	T169,T209,T178	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[0]	Yes	Yes	*T44,*T41,*T45	Yes	T44,T41,T45	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[2:1]	No	No		No		OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3]	Yes	Yes	T44,T41,T45	Yes	T44,T41,T45	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[4:0]	Yes	Yes	*T44,*T41,*T45	Yes	T44,T41,T45	OUTPUT
tl_sram_ctrl_main__regs_o.a_data[6:5]	No	No		No		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[7]	Yes	Yes	*T44,*T41,*T45	Yes	T44,T41,T45	OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:8]	No	No		No		OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T44,T41,T45	Yes	T44,T41,T45	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[0]	No	No		No		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[1]	Yes	Yes	*T44,*T41,*T45	Yes	T44,T41,T45	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:2]	No	No		No		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[0]	No	No		No		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1]	Yes	Yes	T44,T41,T45	Yes	T44,T41,T45	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[1:0]	No	No		No		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2]	Yes	Yes	T169,T209,T178	Yes	T169,T209,T178	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T44,T41,T45	Yes	T44,T41,T45	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T44,T41,T45	Yes	T44,T41,T45	INPUT
tl_sram_ctrl_main__regs_i.d_error	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[5:0]	Yes	Yes	*T169,*T210,*T211	Yes	T169,T210,T211	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6]	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[1:0]	Yes	Yes	T41,T169,T178	Yes	T44,T41,T45	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[3:2]	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[5:4]	Yes	Yes	*T41,T169,T178	Yes	T44,T41,T45	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T41,T169,T178	Yes	T44,T41,T45	INPUT
tl_sram_ctrl_main__regs_i.d_sink	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_source[0]	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_source[1]	Yes	Yes	*T41,*T169,*T178	Yes	T44,T41,T45	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:2]	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[0]	No	No		No		INPUT
tl_sram_ctrl_main__regs_i.d_size[1]	Yes	Yes	T41,T169,T178	Yes	T44,T41,T45	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T169,*T178,*T179	Yes	T169,T209,T178	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T44,T41,T45	Yes	T44,T41,T45	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[4:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5]	No	No		No		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[0]	No	No		No		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[1]	No	No		No		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T1,T4,T54	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[3]	No	No		No		INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[5:4]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6]	No	No		No		INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	No	No		No		INPUT
tl_sram_ctrl_main__ram_i.d_source[4:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[5]	No	No		No		INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[0]	No	No		No		INPUT
tl_sram_ctrl_main__ram_i.d_size[1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range