Unified Coverage Report :: Module :: prim_mubi4_sync

Module : prim_mubi4_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync	100.00						100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.41	99.34	100.00			98.31	100.00	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : prim_mubi4_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1027	1027	0	0
OutputsKnown_A	132004135	131303296	0	0
gen_no_flops.OutputDelay_A	132004135	131303296	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T31	1	1	0	0
T54	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T119	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132004135	131303296	0	0
T1	53951	53521	0	0
T2	147269	146866	0	0
T3	21074	20233	0	0
T4	65175	64790	0	0
T31	57264	56716	0	0
T54	142438	141958	0	0
T58	110312	109645	0	0
T59	33335	32932	0	0
T60	41354	40856	0	0
T119	58105	57803	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132004135	131303296	0	0
T1	53951	53521	0	0
T2	147269	146866	0	0
T3	21074	20233	0	0
T4	65175	64790	0	0
T31	57264	56716	0	0
T54	142438	141958	0	0
T58	110312	109645	0	0
T59	33335	32932	0	0
T60	41354	40856	0	0
T119	58105	57803	0	0

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1027	1027	0	0
OutputsKnown_A	132004135	131303296	0	0
gen_no_flops.OutputDelay_A	132004135	131303296	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1027	1027	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T31	1	1	0	0
T54	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0
T119	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132004135	131303296	0	0
T1	53951	53521	0	0
T2	147269	146866	0	0
T3	21074	20233	0	0
T4	65175	64790	0	0
T31	57264	56716	0	0
T54	142438	141958	0	0
T58	110312	109645	0	0
T59	33335	32932	0	0
T60	41354	40856	0	0
T119	58105	57803	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132004135	131303296	0	0
T1	53951	53521	0	0
T2	147269	146866	0	0
T3	21074	20233	0	0
T4	65175	64790	0	0
T31	57264	56716	0	0
T54	142438	141958	0	0
T58	110312	109645	0	0
T59	33335	32932	0	0
T60	41354	40856	0	0
T119	58105	57803	0	0