Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : edn
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.70 95.70

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_edn1 92.86 92.86
tb.dut.top_earlgrey.u_edn0 95.61 95.61


Module Instance : tb.dut.top_earlgrey.u_edn1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.86 92.86


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.86 92.86


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.22 92.47 87.18 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_edn0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.61 95.61


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.61 95.61


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.22 92.47 87.18 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : edn
TotalCoveredPercent
Totals 78 64 82.05
Total Bits 1210 1158 95.70
Total Bits 0->1 605 580 95.87
Total Bits 1->0 605 578 95.54

Ports 78 64 82.05
Port Bits 1210 1158 95.70
Port Bits 0->1 605 580 95.87
Port Bits 1->0 605 578 95.54

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T54 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T69,T61,T70 Yes T69,T61,T70 INPUT
tl_i.a_user.cmd_intg[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[1] No No No INPUT
tl_i.a_user.cmd_intg[6:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T69,T61,T70 Yes T69,T61,T70 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[6:2] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20:16] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[1:0] Yes Yes *T52,*T1,*T2 Yes T52,T1,T2 INPUT
tl_i.a_source[5:2] No No No INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[0] No No No INPUT
tl_i.a_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[1:0] No No No INPUT
tl_i.a_opcode[2] Yes Yes T69,T61,T70 Yes T69,T61,T70 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T69,T61,T70 Yes T69,T61,T70 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T1,T4,T54 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes *T1,*T4,*T54 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T4,T54 Yes T1,T2,T3 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[1:0] Yes Yes *T52,*T1,*T4 Yes T52,T1,T2 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T1,T4,T54 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T69,*T61,*T70 Yes T69,T61,T70 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_i[0].edn_req Yes Yes T69,T61,T68 Yes T69,T61,T68 INPUT
edn_i[1].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[2].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[3].edn_req Yes Yes T410,T411,T412 Yes T410,T411,T412 INPUT
edn_i[4].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[5].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[6].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[7].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T69,T61,T68 Yes T69,T61,T68 OUTPUT
edn_o[0].edn_fips Yes Yes T61,T68,T413 Yes T69,T61,T68 OUTPUT
edn_o[0].edn_ack Yes Yes T69,T61,T68 Yes T69,T61,T68 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[1].edn_fips No No Yes T71,T155,T156 OUTPUT
edn_o[1].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[2].edn_fips Yes Yes T61,T63,T65 Yes T61,T63,T71 OUTPUT
edn_o[2].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T410,T411,T412 Yes T410,T411,T412 OUTPUT
edn_o[3].edn_fips No No Yes T412,T40,T229 OUTPUT
edn_o[3].edn_ack Yes Yes T410,T411,T412 Yes T410,T411,T412 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T1,T4,T54 Yes T1,T2,T3 OUTPUT
edn_o[4].edn_fips Yes Yes T61 Yes T61,T155,T137 OUTPUT
edn_o[4].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[5].edn_fips Yes Yes T61,T68,T413 Yes T61,T70,T68 OUTPUT
edn_o[5].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[6].edn_fips Yes Yes T61,T68,T413 Yes T61,T68,T71 OUTPUT
edn_o[6].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[7].edn_bus[31:0] Yes Yes T1,T54,T60 Yes T1,T3,T54 OUTPUT
edn_o[7].edn_fips Yes Yes T61,T63,T68 Yes T61,T63,T68 OUTPUT
edn_o[7].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T1,T4,T54 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.genbits_fips Yes Yes T63,T65,T414 Yes T69,T61,T70 INPUT
csrng_cmd_i.genbits_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_rsp_sts[2:0] No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T61,T68,T413 Yes T61,T68,T413 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T54,T93,T94 Yes T54,T93,T94 INPUT
alert_rx_i[0].ping_n Yes Yes T54,T93,T94 Yes T54,T93,T94 INPUT
alert_rx_i[0].ping_p Yes Yes T54,T93,T94 Yes T54,T93,T94 INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T54,T93,T94 Yes T54,T93,T94 INPUT
alert_rx_i[1].ping_n Yes Yes T54,T93,T94 Yes T54,T93,T94 INPUT
alert_rx_i[1].ping_p Yes Yes T54,T93,T94 Yes T54,T93,T94 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T54,T93,T94 Yes T54,T93,T94 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T54,T93,T94 Yes T54,T93,T94 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T257,T365,T216 Yes T257,T365,T216 OUTPUT
intr_edn_fatal_err_o Yes Yes T216,T217,T218 Yes T216,T217,T218 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn1
TotalCoveredPercent
Totals 50 37 74.00
Total Bits 714 663 92.86
Total Bits 0->1 357 332 93.00
Total Bits 1->0 357 331 92.72

Ports 50 37 74.00
Port Bits 714 663 92.86
Port Bits 0->1 357 332 93.00
Port Bits 1->0 357 331 92.72

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T54 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T4,T54 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T69,T61,T70 Yes T69,T61,T70 INPUT
tl_i.a_user.cmd_intg[0] Yes Yes *T69,*T61,*T70 Yes T69,T61,T70 INPUT
tl_i.a_user.cmd_intg[1] No No No INPUT
tl_i.a_user.cmd_intg[6:2] Yes Yes T69,T61,T70 Yes T69,T61,T70 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T69,*T61,*T70 Yes T69,T61,T70 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T69,T61,T70 Yes T69,T61,T70 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T69,T61,T70 Yes T69,T61,T70 INPUT
tl_i.a_mask[3:0] Yes Yes T69,T61,T70 Yes T69,T61,T70 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[6:2] Yes Yes *T69,*T61,*T70 Yes T69,T61,T70 INPUT
tl_i.a_address[18:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20:19] Yes Yes T69,T61,T70 Yes T69,T61,T70 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T69,*T61,*T70 Yes T69,T61,T70 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T69,*T61,*T70 Yes T69,T61,T70 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[1:0] Yes Yes *T52,*T69,*T61 Yes T52,T69,T61 INPUT
tl_i.a_source[5:2] No No No INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[0] No No No INPUT
tl_i.a_size[1] Yes Yes T69,T61,T70 Yes T69,T61,T70 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[1:0] No No No INPUT
tl_i.a_opcode[2] Yes Yes T69,T61,T70 Yes T69,T61,T70 INPUT
tl_i.a_valid Yes Yes T69,T61,T70 Yes T69,T61,T70 INPUT
tl_o.a_ready Yes Yes T69,T61,T70 Yes T69,T61,T70 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T69,T61,T70 Yes T69,T61,T70 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T69,T61,T70 Yes T69,T61,T70 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes T63,*T65,*T207 Yes T69,T61,T70 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T69,T61,T70 Yes T69,T61,T70 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[1:0] Yes Yes *T52,*T69,*T61 Yes T52,T69,T61 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T63,T65,T207 Yes T69,T61,T70 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T69,*T61,*T70 Yes T69,T61,T70 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T69,T61,T70 Yes T69,T61,T70 OUTPUT
edn_i[0].edn_req Yes Yes T61,T68,T71 Yes T61,T68,T71 INPUT
edn_i[1].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[2].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[3].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[4].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[5].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[6].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_i[7].edn_req[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off and unused.
edn_o[0].edn_bus[31:0] Yes Yes T61,T68,T71 Yes T61,T68,T71 OUTPUT
edn_o[0].edn_fips Yes Yes T61,T68,T413 Yes T61,T68,T71 OUTPUT
edn_o[0].edn_ack Yes Yes T61,T68,T71 Yes T61,T68,T71 OUTPUT
edn_o[1].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[1].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[1].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[2].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[3].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[4].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[5].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[6].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_bus[31:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_fips[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
edn_o[7].edn_ack[0:0] Excluded Excluded Excluded OUTPUT [UNR] Tied off and unused.
csrng_cmd_o.genbits_ready Yes Yes T69,T61,T70 Yes T69,T61,T70 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T61,T63,T68 Yes T69,T61,T70 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T69,T61,T70 Yes T69,T61,T70 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T61,T63,T68 Yes T61,T70,T63 INPUT
csrng_cmd_i.genbits_fips No No Yes T414,T415,T416 INPUT
csrng_cmd_i.genbits_valid Yes Yes T69,T61,T70 Yes T69,T61,T70 INPUT
csrng_cmd_i.csrng_rsp_sts[2:0] No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T69,T61,T70 Yes T69,T61,T70 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T61,T68,T413 Yes T61,T68,T413 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T54,T93,T94 Yes T54,T93,T94 INPUT
alert_rx_i[0].ping_n Yes Yes T54,T93,T94 Yes T54,T93,T94 INPUT
alert_rx_i[0].ping_p Yes Yes T54,T93,T94 Yes T54,T93,T94 INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T54,T93,T94 Yes T54,T93,T94 INPUT
alert_rx_i[1].ping_n Yes Yes T54,T93,T94 Yes T54,T93,T94 INPUT
alert_rx_i[1].ping_p Yes Yes T54,T93,T94 Yes T54,T93,T94 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T54,T93,T94 Yes T54,T93,T94 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T54,T93,T94 Yes T54,T93,T94 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T257,T365,T216 Yes T257,T365,T216 OUTPUT
intr_edn_fatal_err_o Yes Yes T216,T217,T218 Yes T216,T217,T218 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn0
TotalCoveredPercent
Totals 78 63 80.77
Total Bits 1208 1155 95.61
Total Bits 0->1 604 579 95.86
Total Bits 1->0 604 576 95.36

Ports 78 63 80.77
Port Bits 1208 1155 95.61
Port Bits 0->1 604 579 95.86
Port Bits 1->0 604 576 95.36

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T4,T54 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T69,T61,T70 Yes T69,T61,T70 INPUT
tl_i.a_user.cmd_intg[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[1] No No No INPUT
tl_i.a_user.cmd_intg[6:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[2:1] No No No INPUT
tl_i.a_user.instr_type[3] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T69,T61,T70 Yes T69,T61,T70 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[1:0] No No No INPUT
tl_i.a_address[6:2] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[18:16] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[19] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[20] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[23:21] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[24] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:25] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[1:0] Yes Yes *T52,*T1,*T2 Yes T52,T1,T2 INPUT
tl_i.a_source[5:2] No No No INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[0] No No No INPUT
tl_i.a_size[1] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[1:0] No No No INPUT
tl_i.a_opcode[2] Yes Yes T69,T61,T70 Yes T69,T61,T70 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error No No No OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T69,T61,T70 Yes T69,T61,T70 OUTPUT
tl_o.d_user.rsp_intg[1:0] Yes Yes T1,T4,T54 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[3:2] No No No OUTPUT
tl_o.d_user.rsp_intg[5:4] Yes Yes *T1,*T4,*T54 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] No No No OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T4,T54 Yes T1,T2,T3 OUTPUT
tl_o.d_sink No No No OUTPUT
tl_o.d_source[1:0] Yes Yes *T52,*T1,*T4 Yes T52,T1,T2 OUTPUT
tl_o.d_source[5:2] No No No OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[0] No No No OUTPUT
tl_o.d_size[1] Yes Yes T1,T4,T54 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T69,*T61,*T70 Yes T69,T61,T70 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_i[0].edn_req Yes Yes T69,T175,T172 Yes T69,T175,T172 INPUT
edn_i[1].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[2].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[3].edn_req Yes Yes T410,T411,T412 Yes T410,T411,T412 INPUT
edn_i[4].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[5].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[6].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[7].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T69,T175,T324 Yes T69,T175,T64 OUTPUT
edn_o[0].edn_fips No No Yes T69,T175,T64 OUTPUT
edn_o[0].edn_ack Yes Yes T69,T175,T172 Yes T69,T175,T172 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[1].edn_fips No No Yes T71,T155,T156 OUTPUT
edn_o[1].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[2].edn_fips Yes Yes T61,T63,T65 Yes T61,T63,T71 OUTPUT
edn_o[2].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T410,T411,T412 Yes T410,T411,T412 OUTPUT
edn_o[3].edn_fips No No Yes T412,T40,T229 OUTPUT
edn_o[3].edn_ack Yes Yes T410,T411,T412 Yes T410,T411,T412 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T1,T4,T54 Yes T1,T2,T3 OUTPUT
edn_o[4].edn_fips Yes Yes T61 Yes T61,T155,T137 OUTPUT
edn_o[4].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[5].edn_fips Yes Yes T61,T68,T413 Yes T61,T70,T68 OUTPUT
edn_o[5].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[6].edn_fips Yes Yes T61,T68,T413 Yes T61,T68,T71 OUTPUT
edn_o[6].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[7].edn_bus[31:0] Yes Yes T1,T54,T60 Yes T1,T3,T54 OUTPUT
edn_o[7].edn_fips Yes Yes T61,T63,T68 Yes T61,T63,T68 OUTPUT
edn_o[7].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T1,T4,T54 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.genbits_fips Yes Yes T63,T65,T414 Yes T69,T61,T70 INPUT
csrng_cmd_i.genbits_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_rsp_sts[2:0] No No No INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T61,T68,T413 Yes T61,T68,T413 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T54,T93,T94 Yes T54,T93,T94 INPUT
alert_rx_i[0].ping_n Yes Yes T54,T93,T94 Yes T54,T93,T94 INPUT
alert_rx_i[0].ping_p Yes Yes T54,T93,T94 Yes T54,T93,T94 INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T54,T93,T94 Yes T54,T93,T94 INPUT
alert_rx_i[1].ping_n Yes Yes T54,T93,T94 Yes T54,T93,T94 INPUT
alert_rx_i[1].ping_p Yes Yes T54,T93,T94 Yes T54,T93,T94 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T54,T93,T94 Yes T54,T93,T94 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T54,T93,T94 Yes T54,T93,T94 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T257,T365,T216 Yes T257,T365,T216 OUTPUT
intr_edn_fatal_err_o Yes Yes T216,T217,T218 Yes T216,T217,T218 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%