Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1097939	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

36469910

1

T1

6988

T2

14794

T3

17606

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	26133558	1			T1	3037		T2	6511		T3	8519
values[0x0]	10335433	1			T1	3951		T2	8283		T3	9087
values[0x1]	1098858	1			T1	294		T2	1134		T3	1536

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	9160	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

37558689

1

T1

7282

T2

15928

T3

19142

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18769832	1			T1	3641		T2	7965		T3	9572
valid_sources[0x01]	18768710	1			T1	3641		T2	7963		T3	9570
valid_sources[0x02]	436	1			T29	47		T31	61		T33	22
valid_sources[0x03]	438	1			T150	1		T110	5		T29	37
valid_sources[0x04]	466	1			T29	34		T31	41		T33	25
valid_sources[0x05]	369	1			T6	2		T53	3		T150	4
valid_sources[0x06]	522	1			T174	2		T29	34		T31	61
valid_sources[0x07]	411	1			T53	4		T29	24		T31	52
valid_sources[0x08]	350	1			T150	1		T110	1		T29	41
valid_sources[0x09]	308	1			T29	36		T30	20		T31	61
valid_sources[0x0a]	421	1			T6	2		T110	1		T29	40
valid_sources[0x0b]	414	1			T29	28		T31	47		T33	34
valid_sources[0x0c]	357	1			T6	1		T52	5		T150	2
valid_sources[0x0d]	608	1			T6	2		T29	32		T30	259
valid_sources[0x0e]	303	1			T29	28		T30	16		T31	49
valid_sources[0x0f]	583	1			T6	1		T174	1		T29	40
valid_sources[0x10]	355	1			T6	1		T29	39		T31	59
valid_sources[0x11]	364	1			T6	1		T52	6		T29	49
valid_sources[0x12]	383	1			T150	2		T29	37		T31	44
valid_sources[0x13]	420	1			T53	22		T29	40		T31	56
valid_sources[0x14]	401	1			T174	1		T29	27		T31	54
valid_sources[0x15]	365	1			T150	5		T29	41		T30	16
valid_sources[0x16]	332	1			T110	3		T174	2		T29	39
valid_sources[0x17]	325	1			T6	1		T29	37		T31	63
valid_sources[0x18]	393	1			T53	2		T174	1		T29	39
valid_sources[0x19]	386	1			T6	1		T174	1		T29	40
valid_sources[0x1a]	649	1			T6	1		T174	1		T29	33
valid_sources[0x1b]	442	1			T6	1		T29	33		T31	75
valid_sources[0x1c]	324	1			T174	2		T29	29		T30	16
valid_sources[0x1d]	415	1			T110	4		T174	1		T29	41
valid_sources[0x1e]	473	1			T6	3		T53	2		T150	1
valid_sources[0x1f]	337	1			T6	1		T174	3		T29	43
valid_sources[0x20]	362	1			T174	2		T29	34		T31	55

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26133558

1

T1

3037

T2

6511

T3

8519

values[0x0]

all_enables

biggest_size

10330748

1

T1

3951

T2

8283

T3

9087

values[0x1]

all_enables

biggest_size

5604

1

T6

19

T52

20

T53

17