| SCORE |
LINE |
COND |
TOGGLE |
FSM |
BRANCH |
ASSERT |
GROUP |
|
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
| 40.87 |
40.87 |
44.76 |
44.76 |
43.06 |
43.06 |
31.74 |
31.74 |
|
|
57.96 |
57.96 |
59.62 |
59.62 |
8.11 |
8.11 |
/workspace/coverage/default/73.chip_sw_all_escalation_resets.1965330380 |
| 51.75 |
10.88 |
52.94 |
8.19 |
52.03 |
8.96 |
37.44 |
5.70 |
|
|
65.82 |
7.85 |
85.84 |
26.22 |
16.45 |
8.33 |
/workspace/coverage/default/1.chip_jtag_csr_rw.240350244 |
| 60.47 |
8.72 |
53.62 |
0.67 |
52.88 |
0.85 |
42.77 |
5.33 |
|
|
66.34 |
0.52 |
86.01 |
0.17 |
61.18 |
44.74 |
/workspace/coverage/default/2.chip_sw_alert_test.1882210423 |
| 66.29 |
5.82 |
64.40 |
10.78 |
60.74 |
7.86 |
46.55 |
3.78 |
|
|
76.05 |
9.71 |
86.19 |
0.17 |
63.82 |
2.63 |
/workspace/coverage/default/0.chip_jtag_csr_rw.2100078205 |
| 71.48 |
5.18 |
74.92 |
10.53 |
66.31 |
5.57 |
50.57 |
4.02 |
|
|
79.20 |
3.16 |
90.73 |
4.55 |
67.11 |
3.29 |
/workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1696240559 |
| 73.93 |
2.45 |
74.92 |
0.00 |
66.31 |
0.00 |
65.29 |
14.72 |
|
|
79.20 |
0.00 |
90.73 |
0.00 |
67.11 |
0.00 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.3711260549 |
| 75.49 |
1.56 |
75.01 |
0.08 |
66.33 |
0.01 |
74.39 |
9.10 |
|
|
79.21 |
0.01 |
90.91 |
0.17 |
67.11 |
0.00 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.1894993273 |
| 77.00 |
1.51 |
78.50 |
3.49 |
68.41 |
2.09 |
75.43 |
1.04 |
|
|
81.62 |
2.41 |
90.91 |
0.00 |
67.11 |
0.00 |
/workspace/coverage/default/1.chip_plic_all_irqs_0.2321696261 |
| 78.35 |
1.35 |
80.67 |
2.17 |
71.07 |
2.66 |
75.67 |
0.23 |
|
|
84.67 |
3.05 |
90.91 |
0.00 |
67.11 |
0.00 |
/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.900818954 |
| 79.55 |
1.20 |
82.59 |
1.92 |
72.01 |
0.93 |
78.33 |
2.66 |
|
|
85.34 |
0.67 |
91.96 |
1.05 |
67.11 |
0.00 |
/workspace/coverage/default/0.chip_sw_power_virus.1689778779 |
| 80.74 |
1.18 |
84.46 |
1.87 |
74.21 |
2.21 |
79.59 |
1.26 |
|
|
86.92 |
1.58 |
92.13 |
0.17 |
67.11 |
0.00 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.3372471740 |
| 81.52 |
0.78 |
84.61 |
0.15 |
74.30 |
0.09 |
80.06 |
0.48 |
|
|
87.03 |
0.11 |
95.98 |
3.85 |
67.11 |
0.00 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.3956392936 |
| 82.14 |
0.63 |
85.84 |
1.23 |
75.37 |
1.07 |
80.30 |
0.24 |
|
|
88.27 |
1.24 |
95.98 |
0.00 |
67.11 |
0.00 |
/workspace/coverage/default/0.chip_plic_all_irqs_20.3302073435 |
| 82.64 |
0.50 |
85.84 |
0.00 |
75.37 |
0.00 |
83.30 |
3.00 |
|
|
88.27 |
0.00 |
95.98 |
0.00 |
67.11 |
0.00 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.2457576546 |
| 83.09 |
0.45 |
86.46 |
0.62 |
75.98 |
0.61 |
83.53 |
0.23 |
|
|
88.98 |
0.71 |
96.50 |
0.52 |
67.11 |
0.00 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.506069404 |
| 83.50 |
0.41 |
87.01 |
0.55 |
76.86 |
0.88 |
83.63 |
0.10 |
|
|
89.88 |
0.90 |
96.50 |
0.00 |
67.11 |
0.00 |
/workspace/coverage/default/2.chip_jtag_csr_rw.2538820230 |
| 83.84 |
0.34 |
87.01 |
0.00 |
76.86 |
0.00 |
84.16 |
0.53 |
|
|
89.88 |
0.00 |
96.50 |
0.00 |
68.64 |
1.54 |
/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.367998010 |
| 84.11 |
0.27 |
87.49 |
0.48 |
77.12 |
0.25 |
84.45 |
0.30 |
|
|
90.07 |
0.19 |
96.68 |
0.17 |
68.86 |
0.22 |
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1382428357 |
| 84.35 |
0.24 |
87.98 |
0.49 |
77.56 |
0.44 |
84.57 |
0.12 |
|
|
90.46 |
0.39 |
96.68 |
0.00 |
68.86 |
0.00 |
/workspace/coverage/default/2.chip_plic_all_irqs_10.3098320807 |
| 84.58 |
0.23 |
88.47 |
0.49 |
77.82 |
0.26 |
85.02 |
0.45 |
|
|
90.65 |
0.19 |
96.68 |
0.00 |
68.86 |
0.00 |
/workspace/coverage/default/2.chip_sw_gpio_smoketest.219251301 |
| 84.73 |
0.15 |
88.75 |
0.28 |
78.05 |
0.24 |
85.11 |
0.09 |
|
|
90.95 |
0.30 |
96.68 |
0.00 |
68.86 |
0.00 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1874775843 |
| 84.88 |
0.14 |
88.76 |
0.01 |
78.06 |
0.01 |
85.96 |
0.86 |
|
|
90.95 |
0.00 |
96.68 |
0.00 |
68.86 |
0.00 |
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.48115269 |
| 85.02 |
0.14 |
88.96 |
0.20 |
78.51 |
0.46 |
85.97 |
0.01 |
|
|
91.12 |
0.16 |
96.68 |
0.00 |
68.86 |
0.00 |
/workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.833432390 |
| 85.14 |
0.12 |
88.96 |
0.00 |
78.52 |
0.01 |
86.49 |
0.52 |
|
|
91.12 |
0.00 |
96.68 |
0.00 |
69.08 |
0.22 |
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.664302519 |
| 85.26 |
0.12 |
89.12 |
0.17 |
78.78 |
0.26 |
86.77 |
0.28 |
|
|
91.12 |
0.00 |
96.68 |
0.00 |
69.08 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3682576021 |
| 85.37 |
0.11 |
89.13 |
0.01 |
78.78 |
0.00 |
87.43 |
0.66 |
|
|
91.12 |
0.00 |
96.68 |
0.00 |
69.08 |
0.00 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.1111106889 |
| 85.46 |
0.09 |
89.16 |
0.02 |
79.03 |
0.25 |
87.43 |
0.00 |
|
|
91.40 |
0.28 |
96.68 |
0.00 |
69.08 |
0.00 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3823349441 |
| 85.55 |
0.08 |
89.25 |
0.09 |
79.08 |
0.05 |
87.54 |
0.11 |
|
|
91.44 |
0.04 |
96.68 |
0.00 |
69.30 |
0.22 |
/workspace/coverage/default/78.chip_sw_all_escalation_resets.3984325915 |
| 85.63 |
0.08 |
89.27 |
0.03 |
79.26 |
0.18 |
87.56 |
0.02 |
|
|
91.50 |
0.06 |
96.68 |
0.00 |
69.52 |
0.22 |
/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1409371235 |
| 85.71 |
0.08 |
89.27 |
0.00 |
79.26 |
0.01 |
88.06 |
0.50 |
|
|
91.50 |
0.00 |
96.68 |
0.00 |
69.52 |
0.00 |
/workspace/coverage/default/79.chip_sw_all_escalation_resets.1581574519 |
| 85.79 |
0.07 |
89.43 |
0.16 |
79.37 |
0.11 |
88.11 |
0.05 |
|
|
91.62 |
0.12 |
96.68 |
0.00 |
69.52 |
0.00 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.1480211564 |
| 85.86 |
0.07 |
89.43 |
0.00 |
79.37 |
0.00 |
88.55 |
0.44 |
|
|
91.62 |
0.00 |
96.68 |
0.00 |
69.52 |
0.00 |
/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.3100733597 |
| 85.93 |
0.07 |
89.43 |
0.01 |
79.38 |
0.01 |
88.56 |
0.01 |
|
|
91.63 |
0.01 |
96.85 |
0.17 |
69.74 |
0.22 |
/workspace/coverage/default/20.chip_sw_all_escalation_resets.3496768922 |
| 86.00 |
0.07 |
89.44 |
0.01 |
79.39 |
0.01 |
88.56 |
0.01 |
|
|
91.63 |
0.01 |
97.03 |
0.17 |
69.96 |
0.22 |
/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.1576391600 |
| 86.06 |
0.06 |
89.46 |
0.02 |
79.42 |
0.03 |
88.60 |
0.03 |
|
|
91.67 |
0.03 |
97.03 |
0.00 |
70.18 |
0.22 |
/workspace/coverage/default/75.chip_sw_all_escalation_resets.1911775280 |
| 86.11 |
0.06 |
89.46 |
0.00 |
79.58 |
0.16 |
88.60 |
0.00 |
|
|
91.85 |
0.18 |
97.03 |
0.00 |
70.18 |
0.00 |
/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1185865151 |
| 86.16 |
0.04 |
89.47 |
0.01 |
79.61 |
0.03 |
88.64 |
0.04 |
|
|
91.85 |
0.01 |
97.20 |
0.17 |
70.18 |
0.00 |
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.504143099 |
| 86.20 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.65 |
0.02 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
70.39 |
0.22 |
/workspace/coverage/default/14.chip_sw_all_escalation_resets.2700741735 |
| 86.23 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.66 |
0.01 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
70.61 |
0.22 |
/workspace/coverage/default/39.chip_sw_all_escalation_resets.3131042909 |
| 86.27 |
0.04 |
89.47 |
0.01 |
79.61 |
0.01 |
88.67 |
0.01 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
70.83 |
0.22 |
/workspace/coverage/default/1.chip_sw_all_escalation_resets.2553149636 |
| 86.31 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.67 |
0.01 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
71.05 |
0.22 |
/workspace/coverage/default/62.chip_sw_all_escalation_resets.790411554 |
| 86.35 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.01 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
71.27 |
0.22 |
/workspace/coverage/default/37.chip_sw_all_escalation_resets.3539955759 |
| 86.39 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.01 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
71.49 |
0.22 |
/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1446553672 |
| 86.42 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
71.71 |
0.22 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1038632170 |
| 86.46 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
71.93 |
0.22 |
/workspace/coverage/default/0.chip_sw_all_escalation_resets.1718102369 |
| 86.49 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
72.15 |
0.22 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.3366787717 |
| 86.53 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
72.37 |
0.22 |
/workspace/coverage/default/10.chip_sw_all_escalation_resets.1083244226 |
| 86.57 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
72.59 |
0.22 |
/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.3591242781 |
| 86.60 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
72.81 |
0.22 |
/workspace/coverage/default/11.chip_sw_all_escalation_resets.4081454256 |
| 86.64 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
73.03 |
0.22 |
/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1013465311 |
| 86.68 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
73.25 |
0.22 |
/workspace/coverage/default/12.chip_sw_all_escalation_resets.4184940324 |
| 86.71 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
73.46 |
0.22 |
/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.3663418730 |
| 86.75 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
73.68 |
0.22 |
/workspace/coverage/default/13.chip_sw_all_escalation_resets.418181410 |
| 86.79 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
73.90 |
0.22 |
/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.3798508375 |
| 86.82 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
74.12 |
0.22 |
/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.2408170113 |
| 86.86 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
74.34 |
0.22 |
/workspace/coverage/default/15.chip_sw_all_escalation_resets.2390722901 |
| 86.90 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
74.56 |
0.22 |
/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2728611738 |
| 86.93 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
74.78 |
0.22 |
/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.3611344018 |
| 86.97 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
75.00 |
0.22 |
/workspace/coverage/default/18.chip_sw_all_escalation_resets.2665085078 |
| 87.01 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
75.22 |
0.22 |
/workspace/coverage/default/19.chip_sw_all_escalation_resets.879337448 |
| 87.04 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
75.44 |
0.22 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2257177447 |
| 87.08 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
75.66 |
0.22 |
/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1282655884 |
| 87.12 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
75.88 |
0.22 |
/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.1788210959 |
| 87.15 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
76.10 |
0.22 |
/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3564325235 |
| 87.19 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
76.32 |
0.22 |
/workspace/coverage/default/22.chip_sw_all_escalation_resets.1657209355 |
| 87.23 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
76.54 |
0.22 |
/workspace/coverage/default/23.chip_sw_all_escalation_resets.1325803081 |
| 87.26 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
76.75 |
0.22 |
/workspace/coverage/default/26.chip_sw_all_escalation_resets.238416414 |
| 87.30 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
76.97 |
0.22 |
/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.754233516 |
| 87.34 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
77.19 |
0.22 |
/workspace/coverage/default/29.chip_sw_all_escalation_resets.3467393172 |
| 87.37 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
77.41 |
0.22 |
/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.565784158 |
| 87.41 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
77.63 |
0.22 |
/workspace/coverage/default/3.chip_sw_all_escalation_resets.3648423316 |
| 87.45 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
77.85 |
0.22 |
/workspace/coverage/default/30.chip_sw_all_escalation_resets.3841192605 |
| 87.48 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
78.07 |
0.22 |
/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2455434632 |
| 87.52 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
78.29 |
0.22 |
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.3426723777 |
| 87.55 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
78.51 |
0.22 |
/workspace/coverage/default/35.chip_sw_all_escalation_resets.3055006983 |
| 87.59 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
78.73 |
0.22 |
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.3138408589 |
| 87.63 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
78.95 |
0.22 |
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.2316022514 |
| 87.66 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
79.17 |
0.22 |
/workspace/coverage/default/38.chip_sw_all_escalation_resets.3826039707 |
| 87.70 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
79.39 |
0.22 |
/workspace/coverage/default/4.chip_sw_all_escalation_resets.2773624177 |
| 87.74 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
79.61 |
0.22 |
/workspace/coverage/default/40.chip_sw_all_escalation_resets.23351550 |
| 87.77 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
79.82 |
0.22 |
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.1765219331 |
| 87.81 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
80.04 |
0.22 |
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1692737982 |
| 87.85 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
80.26 |
0.22 |
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.2090901197 |
| 87.88 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
80.48 |
0.22 |
/workspace/coverage/default/49.chip_sw_all_escalation_resets.1105076371 |
| 87.92 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
80.70 |
0.22 |
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.3889632380 |
| 87.96 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
80.92 |
0.22 |
/workspace/coverage/default/50.chip_sw_all_escalation_resets.1719210284 |
| 87.99 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
81.14 |
0.22 |
/workspace/coverage/default/54.chip_sw_all_escalation_resets.2348297552 |
| 88.03 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
81.36 |
0.22 |
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.180052113 |
| 88.07 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
81.58 |
0.22 |
/workspace/coverage/default/55.chip_sw_all_escalation_resets.1195355372 |
| 88.10 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
81.80 |
0.22 |
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3798564875 |
| 88.14 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
82.02 |
0.22 |
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.1353207841 |
| 88.18 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
82.24 |
0.22 |
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1335109125 |
| 88.21 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
82.46 |
0.22 |
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1611693046 |
| 88.25 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
82.68 |
0.22 |
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.4220203339 |
| 88.29 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
82.89 |
0.22 |
/workspace/coverage/default/70.chip_sw_all_escalation_resets.27579287 |
| 88.32 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
83.11 |
0.22 |
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1554299922 |
| 88.36 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
83.33 |
0.22 |
/workspace/coverage/default/77.chip_sw_all_escalation_resets.3188747787 |
| 88.40 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
83.55 |
0.22 |
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.3753293791 |
| 88.43 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
83.77 |
0.22 |
/workspace/coverage/default/80.chip_sw_all_escalation_resets.4047681832 |
| 88.47 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
83.99 |
0.22 |
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2854141596 |
| 88.50 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
84.21 |
0.22 |
/workspace/coverage/default/86.chip_sw_all_escalation_resets.4192310673 |
| 88.54 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
84.43 |
0.22 |
/workspace/coverage/default/88.chip_sw_all_escalation_resets.1547044775 |
| 88.58 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
84.65 |
0.22 |
/workspace/coverage/default/94.chip_sw_all_escalation_resets.2658064860 |
| 88.61 |
0.04 |
89.47 |
0.00 |
79.61 |
0.00 |
88.68 |
0.00 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
84.87 |
0.22 |
/workspace/coverage/default/95.chip_sw_all_escalation_resets.1628375849 |
| 88.65 |
0.03 |
89.47 |
0.00 |
79.61 |
0.00 |
88.88 |
0.20 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3587252444 |
| 88.68 |
0.03 |
89.65 |
0.18 |
79.63 |
0.02 |
88.89 |
0.01 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.4035671854 |
| 88.71 |
0.03 |
89.65 |
0.00 |
79.63 |
0.00 |
89.08 |
0.19 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.632787605 |
| 88.74 |
0.03 |
89.65 |
0.00 |
79.63 |
0.00 |
89.27 |
0.19 |
|
|
91.85 |
0.00 |
97.20 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1656592668 |
| 88.77 |
0.03 |
89.65 |
0.00 |
79.63 |
0.00 |
89.27 |
0.00 |
|
|
91.85 |
0.00 |
97.38 |
0.17 |
84.87 |
0.00 |
/workspace/coverage/default/2.chip_sw_data_integrity_escalation.489656870 |
| 88.80 |
0.03 |
89.65 |
0.00 |
79.79 |
0.16 |
89.27 |
0.00 |
|
|
91.85 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.2195111523 |
| 88.83 |
0.03 |
89.71 |
0.07 |
79.85 |
0.06 |
89.27 |
0.01 |
|
|
91.87 |
0.02 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/2.chip_sw_sleep_pin_wake.612660760 |
| 88.85 |
0.03 |
89.79 |
0.07 |
79.85 |
0.00 |
89.35 |
0.07 |
|
|
91.88 |
0.01 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/3.chip_tap_straps_rma.2094256716 |
| 88.88 |
0.02 |
89.81 |
0.02 |
79.92 |
0.07 |
89.35 |
0.00 |
|
|
91.93 |
0.05 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.982325706 |
| 88.90 |
0.02 |
89.88 |
0.08 |
79.94 |
0.01 |
89.36 |
0.01 |
|
|
91.96 |
0.03 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3811340188 |
| 88.92 |
0.02 |
89.92 |
0.03 |
79.98 |
0.04 |
89.39 |
0.03 |
|
|
91.98 |
0.02 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.2550399921 |
| 88.94 |
0.02 |
89.92 |
0.00 |
80.05 |
0.08 |
89.43 |
0.04 |
|
|
91.98 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/2.chip_sw_gpio.512990613 |
| 88.96 |
0.02 |
89.93 |
0.01 |
80.09 |
0.03 |
89.48 |
0.06 |
|
|
92.00 |
0.02 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_usbdev_pincfg.3984335554 |
| 88.97 |
0.02 |
90.02 |
0.09 |
80.10 |
0.01 |
89.49 |
0.01 |
|
|
92.00 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4175511927 |
| 88.99 |
0.02 |
90.02 |
0.00 |
80.10 |
0.00 |
89.60 |
0.11 |
|
|
92.00 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1208031269 |
| 89.01 |
0.02 |
90.04 |
0.02 |
80.14 |
0.04 |
89.61 |
0.02 |
|
|
92.02 |
0.02 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.2157316270 |
| 89.03 |
0.02 |
90.13 |
0.09 |
80.14 |
0.00 |
89.63 |
0.01 |
|
|
92.02 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.3901472577 |
| 89.04 |
0.02 |
90.13 |
0.00 |
80.19 |
0.05 |
89.63 |
0.00 |
|
|
92.06 |
0.04 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/1.chip_sw_sleep_pin_retention.720153376 |
| 89.06 |
0.01 |
90.13 |
0.00 |
80.27 |
0.07 |
89.63 |
0.00 |
|
|
92.06 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/1.chip_plic_all_irqs_20.3057434156 |
| 89.07 |
0.01 |
90.15 |
0.02 |
80.28 |
0.02 |
89.64 |
0.01 |
|
|
92.09 |
0.02 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/21.chip_sw_all_escalation_resets.1629740174 |
| 89.08 |
0.01 |
90.15 |
0.00 |
80.28 |
0.00 |
89.70 |
0.07 |
|
|
92.09 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3013127631 |
| 89.09 |
0.01 |
90.15 |
0.00 |
80.28 |
0.00 |
89.76 |
0.06 |
|
|
92.09 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.649275564 |
| 89.10 |
0.01 |
90.15 |
0.00 |
80.28 |
0.00 |
89.82 |
0.05 |
|
|
92.09 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_jtag_mem_access.4126876066 |
| 89.11 |
0.01 |
90.18 |
0.02 |
80.30 |
0.01 |
89.82 |
0.00 |
|
|
92.11 |
0.02 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.102381688 |
| 89.12 |
0.01 |
90.18 |
0.00 |
80.30 |
0.00 |
89.87 |
0.05 |
|
|
92.11 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2670850319 |
| 89.12 |
0.01 |
90.18 |
0.00 |
80.30 |
0.00 |
89.92 |
0.05 |
|
|
92.11 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.1812927884 |
| 89.13 |
0.01 |
90.18 |
0.00 |
80.32 |
0.02 |
89.94 |
0.02 |
|
|
92.11 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.1407528743 |
| 89.14 |
0.01 |
90.18 |
0.00 |
80.36 |
0.04 |
89.94 |
0.00 |
|
|
92.11 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/2.chip_plic_all_irqs_20.3393904439 |
| 89.14 |
0.01 |
90.21 |
0.03 |
80.36 |
0.01 |
89.94 |
0.00 |
|
|
92.11 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_spi_device_tpm.2052638164 |
| 89.15 |
0.01 |
90.21 |
0.00 |
80.36 |
0.00 |
89.97 |
0.04 |
|
|
92.11 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1320534471 |
| 89.16 |
0.01 |
90.21 |
0.00 |
80.40 |
0.03 |
89.97 |
0.00 |
|
|
92.11 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_plic_all_irqs_0.1801148548 |
| 89.16 |
0.01 |
90.21 |
0.00 |
80.42 |
0.03 |
89.97 |
0.00 |
|
|
92.11 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx.2842569389 |
| 89.16 |
0.01 |
90.21 |
0.00 |
80.45 |
0.02 |
89.97 |
0.00 |
|
|
92.11 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.3725381044 |
| 89.17 |
0.01 |
90.21 |
0.00 |
80.45 |
0.00 |
89.99 |
0.02 |
|
|
92.11 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.965712707 |
| 89.17 |
0.01 |
90.21 |
0.00 |
80.45 |
0.00 |
90.02 |
0.02 |
|
|
92.11 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/1.chip_sw_flash_rma_unlocked.1153198464 |
| 89.18 |
0.01 |
90.21 |
0.01 |
80.46 |
0.01 |
90.02 |
0.01 |
|
|
92.11 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.3348405141 |
| 89.18 |
0.01 |
90.22 |
0.01 |
80.46 |
0.00 |
90.04 |
0.02 |
|
|
92.11 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.2083080114 |
| 89.18 |
0.01 |
90.22 |
0.00 |
80.46 |
0.00 |
90.06 |
0.02 |
|
|
92.11 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_kmac_app_rom.1200771673 |
| 89.19 |
0.01 |
90.22 |
0.00 |
80.46 |
0.00 |
90.08 |
0.02 |
|
|
92.11 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.2283572063 |
| 89.19 |
0.01 |
90.22 |
0.00 |
80.48 |
0.02 |
90.08 |
0.00 |
|
|
92.11 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.3045931235 |
| 89.19 |
0.01 |
90.22 |
0.00 |
80.48 |
0.00 |
90.09 |
0.01 |
|
|
92.11 |
0.01 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.4286083646 |
| 89.19 |
0.01 |
90.23 |
0.01 |
80.48 |
0.01 |
90.09 |
0.01 |
|
|
92.11 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_power_sleep_load.1589897727 |
| 89.20 |
0.01 |
90.23 |
0.00 |
80.48 |
0.00 |
90.11 |
0.02 |
|
|
92.11 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.3574532173 |
| 89.20 |
0.01 |
90.23 |
0.00 |
80.48 |
0.00 |
90.13 |
0.02 |
|
|
92.11 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_edn_boot_mode.3294143354 |
| 89.20 |
0.01 |
90.23 |
0.00 |
80.50 |
0.01 |
90.13 |
0.00 |
|
|
92.11 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1088464296 |
| 89.20 |
0.01 |
90.23 |
0.00 |
80.51 |
0.01 |
90.13 |
0.00 |
|
|
92.11 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/1.chip_plic_all_irqs_10.3138350441 |
| 89.21 |
0.01 |
90.23 |
0.00 |
80.52 |
0.01 |
90.13 |
0.00 |
|
|
92.11 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3995343993 |
| 89.21 |
0.01 |
90.23 |
0.00 |
80.53 |
0.01 |
90.13 |
0.00 |
|
|
92.11 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.770211619 |
| 89.21 |
0.01 |
90.23 |
0.00 |
80.54 |
0.01 |
90.13 |
0.00 |
|
|
92.11 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/1.chip_sw_gpio.1523681266 |
| 89.21 |
0.01 |
90.23 |
0.00 |
80.56 |
0.01 |
90.13 |
0.00 |
|
|
92.11 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.2920711643 |
| 89.21 |
0.01 |
90.23 |
0.00 |
80.56 |
0.00 |
90.14 |
0.01 |
|
|
92.11 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2097497774 |
| 89.21 |
0.01 |
90.23 |
0.00 |
80.56 |
0.00 |
90.15 |
0.01 |
|
|
92.11 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_flash_init.1155879664 |
| 89.22 |
0.01 |
90.23 |
0.00 |
80.56 |
0.00 |
90.15 |
0.01 |
|
|
92.11 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3226454316 |
| 89.22 |
0.01 |
90.23 |
0.00 |
80.56 |
0.00 |
90.16 |
0.01 |
|
|
92.11 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/1.chip_sw_ast_clk_outputs.3644665539 |
| 89.22 |
0.01 |
90.23 |
0.00 |
80.56 |
0.01 |
90.17 |
0.01 |
|
|
92.11 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.1119822589 |
| 89.22 |
0.01 |
90.23 |
0.00 |
80.56 |
0.00 |
90.17 |
0.00 |
|
|
92.12 |
0.01 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/1.chip_tap_straps_dev.1932411994 |
| 89.22 |
0.01 |
90.23 |
0.00 |
80.57 |
0.01 |
90.17 |
0.00 |
|
|
92.12 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_entropy_src_csrng.1672116891 |
| 89.22 |
0.01 |
90.23 |
0.00 |
80.57 |
0.01 |
90.17 |
0.00 |
|
|
92.12 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.203845627 |
| 89.22 |
0.01 |
90.23 |
0.00 |
80.58 |
0.01 |
90.17 |
0.00 |
|
|
92.12 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2049474400 |
| 89.22 |
0.01 |
90.23 |
0.00 |
80.59 |
0.01 |
90.17 |
0.00 |
|
|
92.12 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.866092070 |
| 89.23 |
0.01 |
90.23 |
0.00 |
80.59 |
0.00 |
90.18 |
0.01 |
|
|
92.12 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.2571193348 |
| 89.23 |
0.01 |
90.23 |
0.00 |
80.59 |
0.00 |
90.18 |
0.01 |
|
|
92.12 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.rom_raw_unlock.2015289278 |
| 89.23 |
0.01 |
90.23 |
0.00 |
80.59 |
0.00 |
90.19 |
0.01 |
|
|
92.12 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3474491393 |
| 89.23 |
0.01 |
90.23 |
0.00 |
80.59 |
0.00 |
90.19 |
0.01 |
|
|
92.12 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3766629717 |
| 89.23 |
0.01 |
90.23 |
0.00 |
80.59 |
0.00 |
90.20 |
0.01 |
|
|
92.12 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.276585703 |
| 89.23 |
0.01 |
90.23 |
0.00 |
80.59 |
0.00 |
90.20 |
0.01 |
|
|
92.12 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.854188635 |
| 89.23 |
0.01 |
90.23 |
0.00 |
80.59 |
0.00 |
90.21 |
0.01 |
|
|
92.12 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3729832923 |
| 89.23 |
0.01 |
90.23 |
0.00 |
80.59 |
0.00 |
90.21 |
0.01 |
|
|
92.12 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.3922422592 |
| 89.23 |
0.01 |
90.23 |
0.00 |
80.59 |
0.00 |
90.22 |
0.01 |
|
|
92.12 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2458463673 |
| 89.23 |
0.01 |
90.23 |
0.00 |
80.59 |
0.01 |
90.22 |
0.00 |
|
|
92.12 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_gpio.1298795331 |
| 89.23 |
0.01 |
90.23 |
0.00 |
80.59 |
0.01 |
90.22 |
0.00 |
|
|
92.12 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.2831222080 |
| 89.23 |
0.01 |
90.23 |
0.00 |
80.59 |
0.00 |
90.22 |
0.01 |
|
|
92.12 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_tap_straps_rma.2649074299 |
| 89.23 |
0.01 |
90.23 |
0.00 |
80.59 |
0.00 |
90.22 |
0.01 |
|
|
92.12 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2060847507 |
| 89.24 |
0.01 |
90.23 |
0.00 |
80.59 |
0.00 |
90.22 |
0.01 |
|
|
92.12 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.570082079 |
| 89.24 |
0.01 |
90.23 |
0.00 |
80.59 |
0.00 |
90.23 |
0.01 |
|
|
92.12 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.2933214722 |
| 89.24 |
0.01 |
90.23 |
0.00 |
80.59 |
0.00 |
90.23 |
0.01 |
|
|
92.12 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.1890598971 |
| 89.24 |
0.01 |
90.23 |
0.00 |
80.59 |
0.00 |
90.23 |
0.01 |
|
|
92.12 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1965015088 |
| 89.24 |
0.01 |
90.23 |
0.00 |
80.59 |
0.00 |
90.23 |
0.01 |
|
|
92.12 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.rom_e2e_jtag_debug_rma.3369353042 |
| 89.24 |
0.01 |
90.23 |
0.00 |
80.59 |
0.00 |
90.24 |
0.01 |
|
|
92.12 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.598974442 |
| 89.24 |
0.01 |
90.23 |
0.00 |
80.59 |
0.00 |
90.24 |
0.01 |
|
|
92.12 |
0.00 |
97.38 |
0.00 |
84.87 |
0.00 |
/workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.950715686 |
| Name |
| /workspace/coverage/default/0.chip_sival_flash_info_access.1573041624 |
| /workspace/coverage/default/0.chip_sw_aes_enc.44646296 |
| /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.1212780923 |
| /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.3098295951 |
| /workspace/coverage/default/0.chip_sw_aes_entropy.2399724772 |
| /workspace/coverage/default/0.chip_sw_aes_idle.4200599791 |
| /workspace/coverage/default/0.chip_sw_aes_masking_off.95380566 |
| /workspace/coverage/default/0.chip_sw_aes_smoketest.2394746523 |
| /workspace/coverage/default/0.chip_sw_alert_handler_entropy.3560239110 |
| /workspace/coverage/default/0.chip_sw_alert_handler_escalation.161993558 |
| /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.4183811936 |
| /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.1410536706 |
| /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2266869373 |
| /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.564084436 |
| /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.1856228996 |
| /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3056946131 |
| /workspace/coverage/default/0.chip_sw_alert_test.3376797128 |
| /workspace/coverage/default/0.chip_sw_aon_timer_irq.1715105522 |
| /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.559505109 |
| /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.1184792997 |
| /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.1255225295 |
| /workspace/coverage/default/0.chip_sw_ast_clk_outputs.3445558091 |
| /workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.1837438340 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1957175184 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.4200480608 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3823240907 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.809047820 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.130730981 |
| /workspace/coverage/default/0.chip_sw_clkmgr_jitter.630894176 |
| /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.3575479073 |
| /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.1931872755 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.2665282106 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.78584749 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3640710431 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.189711200 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.3072063258 |
| /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.3446889482 |
| /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.1504630977 |
| /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.3711854319 |
| /workspace/coverage/default/0.chip_sw_coremark.581329381 |
| /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.2513021414 |
| /workspace/coverage/default/0.chip_sw_csrng_kat_test.3448821981 |
| /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.1432744044 |
| /workspace/coverage/default/0.chip_sw_csrng_smoketest.2419711187 |
| /workspace/coverage/default/0.chip_sw_data_integrity_escalation.3327569344 |
| /workspace/coverage/default/0.chip_sw_edn_auto_mode.1088816154 |
| /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.2611641500 |
| /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.3213308099 |
| /workspace/coverage/default/0.chip_sw_edn_kat.3087837545 |
| /workspace/coverage/default/0.chip_sw_edn_sw_mode.3100783332 |
| /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.723902705 |
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| /workspace/coverage/default/61.chip_sw_all_escalation_resets.1527367797 |
| /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3154814865 |
| /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2733192291 |
| /workspace/coverage/default/63.chip_sw_all_escalation_resets.2206773414 |
| /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2890880863 |
| /workspace/coverage/default/64.chip_sw_all_escalation_resets.3541497534 |
| /workspace/coverage/default/65.chip_sw_all_escalation_resets.3937164569 |
| /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.298876867 |
| /workspace/coverage/default/66.chip_sw_all_escalation_resets.3759362314 |
| /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3887476618 |
| /workspace/coverage/default/67.chip_sw_all_escalation_resets.3830567773 |
| /workspace/coverage/default/68.chip_sw_all_escalation_resets.2285007467 |
| /workspace/coverage/default/69.chip_sw_all_escalation_resets.2734596409 |
| /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2422575415 |
| /workspace/coverage/default/7.chip_sw_all_escalation_resets.4068376323 |
| /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.3332316368 |
| /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.1876520467 |
| /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.1505666743 |
| /workspace/coverage/default/71.chip_sw_all_escalation_resets.2345179013 |
| /workspace/coverage/default/72.chip_sw_all_escalation_resets.703630756 |
| /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3565380048 |
| /workspace/coverage/default/74.chip_sw_all_escalation_resets.847565451 |
| /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.683663243 |
| /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.42424960 |
| /workspace/coverage/default/76.chip_sw_all_escalation_resets.153494329 |
| /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2075671621 |
| /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2779729903 |
| /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1631280959 |
| /workspace/coverage/default/8.chip_sw_all_escalation_resets.1006309508 |
| /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.287720536 |
| /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3056735370 |
| /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1395346985 |
| /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2138717311 |
| /workspace/coverage/default/81.chip_sw_all_escalation_resets.2628164027 |
| /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2784488852 |
| /workspace/coverage/default/82.chip_sw_all_escalation_resets.3710755714 |
| /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3558211767 |
| /workspace/coverage/default/83.chip_sw_all_escalation_resets.2337669764 |
| /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.1618292891 |
| /workspace/coverage/default/84.chip_sw_all_escalation_resets.456520590 |
| /workspace/coverage/default/85.chip_sw_all_escalation_resets.1542991893 |
| /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.829383373 |
| /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.17336207 |
| /workspace/coverage/default/87.chip_sw_all_escalation_resets.1482360368 |
| /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2912368270 |
| /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3437834054 |
| /workspace/coverage/default/89.chip_sw_all_escalation_resets.544299579 |
| /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2021709058 |
| /workspace/coverage/default/9.chip_sw_all_escalation_resets.2332578768 |
| /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.2414245461 |
| /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.1196772174 |
| /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1641002274 |
| /workspace/coverage/default/90.chip_sw_all_escalation_resets.2810718304 |
| /workspace/coverage/default/91.chip_sw_all_escalation_resets.188974983 |
| /workspace/coverage/default/92.chip_sw_all_escalation_resets.3915428061 |
| /workspace/coverage/default/93.chip_sw_all_escalation_resets.4113621345 |
| /workspace/coverage/default/96.chip_sw_all_escalation_resets.2523873452 |
| /workspace/coverage/default/97.chip_sw_all_escalation_resets.1853796734 |
| /workspace/coverage/default/98.chip_sw_all_escalation_resets.1236007686 |
| /workspace/coverage/default/99.chip_sw_all_escalation_resets.2115158928 |
| /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.3632494374 |
| /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.2245265714 |
| /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.2129899363 |
| /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.1954381189 |
| /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.506914179 |
| /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.545822328 |
| /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.1177379512 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T1 |
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1382428357 |
|
|
Aug 04 08:00:17 PM PDT 24 |
Aug 04 08:07:12 PM PDT 24 |
3208993800 ps |
| T2 |
/workspace/coverage/default/0.chip_sw_all_escalation_resets.1718102369 |
|
|
Aug 04 07:12:52 PM PDT 24 |
Aug 04 07:22:16 PM PDT 24 |
4281230752 ps |
| T3 |
/workspace/coverage/default/44.chip_sw_all_escalation_resets.92937803 |
|
|
Aug 04 07:58:32 PM PDT 24 |
Aug 04 08:09:35 PM PDT 24 |
5126576584 ps |
| T32 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.3711260549 |
|
|
Aug 04 07:15:56 PM PDT 24 |
Aug 04 07:52:49 PM PDT 24 |
11164457166 ps |
| T113 |
/workspace/coverage/default/63.chip_sw_all_escalation_resets.2206773414 |
|
|
Aug 04 07:58:40 PM PDT 24 |
Aug 04 08:10:16 PM PDT 24 |
5866246000 ps |
| T37 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1680021299 |
|
|
Aug 04 07:28:48 PM PDT 24 |
Aug 04 07:36:52 PM PDT 24 |
5437453014 ps |
| T63 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.4125137202 |
|
|
Aug 04 07:46:03 PM PDT 24 |
Aug 04 08:44:03 PM PDT 24 |
24739930168 ps |
| T60 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2526683601 |
|
|
Aug 04 07:16:06 PM PDT 24 |
Aug 04 07:37:50 PM PDT 24 |
15536226281 ps |
| T125 |
/workspace/coverage/default/73.chip_sw_all_escalation_resets.1965330380 |
|
|
Aug 04 08:00:13 PM PDT 24 |
Aug 04 08:09:18 PM PDT 24 |
4680138672 ps |
| T61 |
/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.1684578694 |
|
|
Aug 04 07:38:40 PM PDT 24 |
Aug 04 07:45:54 PM PDT 24 |
4877151707 ps |
| T119 |
/workspace/coverage/default/2.chip_tap_straps_prod.2158670077 |
|
|
Aug 04 07:45:45 PM PDT 24 |
Aug 04 08:21:24 PM PDT 24 |
17467875852 ps |
| T171 |
/workspace/coverage/default/1.chip_sw_csrng_smoketest.910276136 |
|
|
Aug 04 07:34:04 PM PDT 24 |
Aug 04 07:37:56 PM PDT 24 |
2487785020 ps |
| T213 |
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2886269540 |
|
|
Aug 04 07:57:51 PM PDT 24 |
Aug 04 08:03:45 PM PDT 24 |
3602315424 ps |
| T13 |
/workspace/coverage/default/2.chip_sw_gpio_smoketest.219251301 |
|
|
Aug 04 07:48:25 PM PDT 24 |
Aug 04 07:54:00 PM PDT 24 |
2561944447 ps |
| T4 |
/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.3902223088 |
|
|
Aug 04 07:15:27 PM PDT 24 |
Aug 04 10:11:39 PM PDT 24 |
58323812222 ps |
| T157 |
/workspace/coverage/default/78.chip_sw_all_escalation_resets.3984325915 |
|
|
Aug 04 08:00:40 PM PDT 24 |
Aug 04 08:10:31 PM PDT 24 |
6139339192 ps |
| T240 |
/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.3560481276 |
|
|
Aug 04 07:16:08 PM PDT 24 |
Aug 04 07:27:30 PM PDT 24 |
4630294360 ps |
| T221 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.3956392936 |
|
|
Aug 04 07:47:32 PM PDT 24 |
Aug 04 07:51:10 PM PDT 24 |
2771581714 ps |
| T5 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.1894993273 |
|
|
Aug 04 07:14:55 PM PDT 24 |
Aug 04 08:55:19 PM PDT 24 |
47967809912 ps |
| T95 |
/workspace/coverage/default/39.chip_sw_all_escalation_resets.3131042909 |
|
|
Aug 04 07:55:37 PM PDT 24 |
Aug 04 08:04:36 PM PDT 24 |
6065092872 ps |
| T199 |
/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.225562412 |
|
|
Aug 04 07:54:25 PM PDT 24 |
Aug 04 08:02:47 PM PDT 24 |
4048274340 ps |
| T316 |
/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.767642611 |
|
|
Aug 04 07:36:50 PM PDT 24 |
Aug 04 08:01:29 PM PDT 24 |
8994203020 ps |
| T317 |
/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1446553672 |
|
|
Aug 04 07:54:57 PM PDT 24 |
Aug 04 08:02:43 PM PDT 24 |
3582665000 ps |
| T272 |
/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.942940577 |
|
|
Aug 04 07:35:14 PM PDT 24 |
Aug 04 07:39:42 PM PDT 24 |
2625365340 ps |
| T212 |
/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.367998010 |
|
|
Aug 04 07:28:46 PM PDT 24 |
Aug 04 07:39:45 PM PDT 24 |
5774839040 ps |
| T56 |
/workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.833432390 |
|
|
Aug 04 07:13:53 PM PDT 24 |
Aug 04 07:19:27 PM PDT 24 |
3484255680 ps |
| T141 |
/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.1959286420 |
|
|
Aug 04 07:31:09 PM PDT 24 |
Aug 04 07:38:23 PM PDT 24 |
3865766728 ps |
| T14 |
/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.337384203 |
|
|
Aug 04 07:49:22 PM PDT 24 |
Aug 04 08:18:01 PM PDT 24 |
8471116056 ps |
| T62 |
/workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3056946131 |
|
|
Aug 04 07:15:38 PM PDT 24 |
Aug 04 10:46:40 PM PDT 24 |
255036361098 ps |
| T64 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.3098295951 |
|
|
Aug 04 07:17:42 PM PDT 24 |
Aug 04 07:22:19 PM PDT 24 |
2848250482 ps |
| T142 |
/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.754233516 |
|
|
Aug 04 07:54:38 PM PDT 24 |
Aug 04 08:03:02 PM PDT 24 |
4457950560 ps |
| T6 |
/workspace/coverage/default/0.chip_jtag_csr_rw.2100078205 |
|
|
Aug 04 07:08:40 PM PDT 24 |
Aug 04 07:28:14 PM PDT 24 |
12815059400 ps |
| T143 |
/workspace/coverage/default/62.chip_sw_all_escalation_resets.790411554 |
|
|
Aug 04 07:57:41 PM PDT 24 |
Aug 04 08:07:35 PM PDT 24 |
4816911288 ps |
| T112 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.397898594 |
|
|
Aug 04 07:28:24 PM PDT 24 |
Aug 04 07:30:28 PM PDT 24 |
2486652756 ps |
| T144 |
/workspace/coverage/default/75.chip_sw_all_escalation_resets.1911775280 |
|
|
Aug 04 07:59:22 PM PDT 24 |
Aug 04 08:09:09 PM PDT 24 |
5227288200 ps |
| T334 |
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.1071221779 |
|
|
Aug 04 07:58:23 PM PDT 24 |
Aug 04 08:03:42 PM PDT 24 |
3656659236 ps |
| T54 |
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.664302519 |
|
|
Aug 04 07:51:30 PM PDT 24 |
Aug 04 08:04:26 PM PDT 24 |
10227750955 ps |
| T365 |
/workspace/coverage/default/23.chip_sw_all_escalation_resets.1325803081 |
|
|
Aug 04 07:54:09 PM PDT 24 |
Aug 04 08:02:32 PM PDT 24 |
4005486422 ps |
| T158 |
/workspace/coverage/default/46.chip_sw_all_escalation_resets.1800877243 |
|
|
Aug 04 07:56:44 PM PDT 24 |
Aug 04 08:09:07 PM PDT 24 |
6637107512 ps |
| T92 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.3357943441 |
|
|
Aug 04 07:37:41 PM PDT 24 |
Aug 04 07:49:53 PM PDT 24 |
4725662424 ps |
| T403 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.2766669894 |
|
|
Aug 04 07:23:44 PM PDT 24 |
Aug 04 07:28:42 PM PDT 24 |
3757579728 ps |
| T74 |
/workspace/coverage/default/0.chip_sw_otbn_randomness.689074957 |
|
|
Aug 04 07:14:22 PM PDT 24 |
Aug 04 07:28:32 PM PDT 24 |
5825926604 ps |
| T387 |
/workspace/coverage/default/99.chip_sw_all_escalation_resets.2115158928 |
|
|
Aug 04 08:01:44 PM PDT 24 |
Aug 04 08:10:38 PM PDT 24 |
4555641748 ps |
| T179 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.2830524598 |
|
|
Aug 04 07:32:43 PM PDT 24 |
Aug 04 07:44:37 PM PDT 24 |
5807748920 ps |
| T49 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.3372471740 |
|
|
Aug 04 07:51:43 PM PDT 24 |
Aug 04 08:44:54 PM PDT 24 |
15368204430 ps |
| T164 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.1588855739 |
|
|
Aug 04 07:15:32 PM PDT 24 |
Aug 04 07:19:46 PM PDT 24 |
3090400290 ps |
| T300 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.772265886 |
|
|
Aug 04 07:27:49 PM PDT 24 |
Aug 04 07:35:47 PM PDT 24 |
4433539164 ps |
| T96 |
/workspace/coverage/default/1.chip_sw_alert_handler_entropy.174400602 |
|
|
Aug 04 07:29:22 PM PDT 24 |
Aug 04 07:35:59 PM PDT 24 |
3893782787 ps |
| T301 |
/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.1870124338 |
|
|
Aug 04 07:48:28 PM PDT 24 |
Aug 04 07:57:13 PM PDT 24 |
6790153432 ps |
| T302 |
/workspace/coverage/default/67.chip_sw_all_escalation_resets.3830567773 |
|
|
Aug 04 07:58:54 PM PDT 24 |
Aug 04 08:09:23 PM PDT 24 |
5787822116 ps |
| T303 |
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1868814446 |
|
|
Aug 04 07:55:17 PM PDT 24 |
Aug 04 08:02:24 PM PDT 24 |
4042483400 ps |
| T304 |
/workspace/coverage/default/1.chip_sw_csrng_kat_test.5736825 |
|
|
Aug 04 07:31:19 PM PDT 24 |
Aug 04 07:35:58 PM PDT 24 |
3343237268 ps |
| T305 |
/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.3232813586 |
|
|
Aug 04 07:51:49 PM PDT 24 |
Aug 04 08:24:17 PM PDT 24 |
8041275176 ps |
| T411 |
/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1013465311 |
|
|
Aug 04 07:53:24 PM PDT 24 |
Aug 04 07:59:10 PM PDT 24 |
3502197464 ps |
| T274 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.2083080114 |
|
|
Aug 04 07:39:05 PM PDT 24 |
Aug 04 07:55:55 PM PDT 24 |
7586164580 ps |
| T259 |
/workspace/coverage/default/1.chip_sw_flash_crash_alert.3404533601 |
|
|
Aug 04 07:33:26 PM PDT 24 |
Aug 04 07:44:18 PM PDT 24 |
5083941792 ps |
| T175 |
/workspace/coverage/default/2.chip_sw_alert_handler_escalation.756784426 |
|
|
Aug 04 07:40:06 PM PDT 24 |
Aug 04 07:50:20 PM PDT 24 |
5463876120 ps |
| T50 |
/workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.1079417277 |
|
|
Aug 04 07:53:55 PM PDT 24 |
Aug 04 08:59:49 PM PDT 24 |
15271559980 ps |
| T320 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.30023756 |
|
|
Aug 04 07:48:50 PM PDT 24 |
Aug 04 07:57:21 PM PDT 24 |
3619731040 ps |
| T71 |
/workspace/coverage/default/0.chip_sw_edn_auto_mode.1088816154 |
|
|
Aug 04 07:15:02 PM PDT 24 |
Aug 04 07:31:21 PM PDT 24 |
4215494516 ps |
| T523 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.2741152920 |
|
|
Aug 04 07:13:42 PM PDT 24 |
Aug 04 07:18:49 PM PDT 24 |
4673218232 ps |
| T97 |
/workspace/coverage/default/2.chip_sw_alert_test.1882210423 |
|
|
Aug 04 07:42:03 PM PDT 24 |
Aug 04 07:46:08 PM PDT 24 |
2655435360 ps |
| T55 |
/workspace/coverage/default/12.chip_sw_lc_ctrl_transition.2929547706 |
|
|
Aug 04 07:52:58 PM PDT 24 |
Aug 04 07:59:21 PM PDT 24 |
4705302109 ps |
| T161 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.4292538508 |
|
|
Aug 04 07:29:30 PM PDT 24 |
Aug 04 07:34:26 PM PDT 24 |
3384605516 ps |
| T204 |
/workspace/coverage/default/1.chip_sival_flash_info_access.3881286939 |
|
|
Aug 04 07:21:39 PM PDT 24 |
Aug 04 07:25:52 PM PDT 24 |
3908084400 ps |
| T233 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.2292541320 |
|
|
Aug 04 07:31:52 PM PDT 24 |
Aug 04 07:40:19 PM PDT 24 |
5340514212 ps |
| T93 |
/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.3720621415 |
|
|
Aug 04 07:54:01 PM PDT 24 |
Aug 04 08:39:40 PM PDT 24 |
13206576800 ps |
| T15 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.2157316270 |
|
|
Aug 04 07:35:18 PM PDT 24 |
Aug 04 11:15:56 PM PDT 24 |
78169487027 ps |
| T524 |
/workspace/coverage/default/2.chip_sw_rstmgr_smoketest.397547606 |
|
|
Aug 04 07:49:05 PM PDT 24 |
Aug 04 07:52:06 PM PDT 24 |
2924495220 ps |
| T255 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1055512167 |
|
|
Aug 04 07:36:33 PM PDT 24 |
Aug 04 07:48:48 PM PDT 24 |
5413113614 ps |
| T214 |
/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.3100733597 |
|
|
Aug 04 07:36:24 PM PDT 24 |
Aug 04 09:00:23 PM PDT 24 |
43595931448 ps |
| T256 |
/workspace/coverage/default/0.chip_sival_flash_info_access.1573041624 |
|
|
Aug 04 07:14:17 PM PDT 24 |
Aug 04 07:18:56 PM PDT 24 |
2787346500 ps |
| T388 |
/workspace/coverage/default/43.chip_sw_all_escalation_resets.3199766553 |
|
|
Aug 04 07:55:31 PM PDT 24 |
Aug 04 08:07:09 PM PDT 24 |
4477497372 ps |
| T51 |
/workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.2582529772 |
|
|
Aug 04 07:38:15 PM PDT 24 |
Aug 04 08:34:29 PM PDT 24 |
14919943720 ps |
| T445 |
/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.113138327 |
|
|
Aug 04 07:55:54 PM PDT 24 |
Aug 04 08:02:04 PM PDT 24 |
4051692800 ps |
| T369 |
/workspace/coverage/default/22.chip_sw_all_escalation_resets.1657209355 |
|
|
Aug 04 07:54:13 PM PDT 24 |
Aug 04 08:03:44 PM PDT 24 |
5845400680 ps |
| T166 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.3346279023 |
|
|
Aug 04 07:17:00 PM PDT 24 |
Aug 04 07:48:57 PM PDT 24 |
9937621000 ps |
| T203 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.735659535 |
|
|
Aug 04 07:37:53 PM PDT 24 |
Aug 04 08:58:45 PM PDT 24 |
46603770550 ps |
| T242 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.1480211564 |
|
|
Aug 04 07:39:56 PM PDT 24 |
Aug 04 07:45:48 PM PDT 24 |
3150070559 ps |
| T114 |
/workspace/coverage/default/0.rom_e2e_jtag_inject_rma.2062866733 |
|
|
Aug 04 07:21:00 PM PDT 24 |
Aug 04 08:11:06 PM PDT 24 |
32404395185 ps |
| T16 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2620044059 |
|
|
Aug 04 07:33:18 PM PDT 24 |
Aug 04 07:39:51 PM PDT 24 |
7373910368 ps |
| T84 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.889460817 |
|
|
Aug 04 07:44:37 PM PDT 24 |
Aug 04 07:52:19 PM PDT 24 |
5662495766 ps |
| T410 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.3589796873 |
|
|
Aug 04 07:14:50 PM PDT 24 |
Aug 04 07:33:17 PM PDT 24 |
5662312346 ps |
| T21 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.2000721905 |
|
|
Aug 04 07:14:37 PM PDT 24 |
Aug 04 08:11:11 PM PDT 24 |
19997766932 ps |
| T326 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.3896953971 |
|
|
Aug 04 07:38:47 PM PDT 24 |
Aug 04 07:51:07 PM PDT 24 |
7797030978 ps |
| T46 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.3901472577 |
|
|
Aug 04 07:25:01 PM PDT 24 |
Aug 04 08:33:16 PM PDT 24 |
14851465428 ps |
| T322 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.2337820498 |
|
|
Aug 04 07:13:21 PM PDT 24 |
Aug 04 07:21:27 PM PDT 24 |
3496379696 ps |
| T284 |
/workspace/coverage/default/2.rom_volatile_raw_unlock.2855862458 |
|
|
Aug 04 07:47:51 PM PDT 24 |
Aug 04 07:49:42 PM PDT 24 |
2258653433 ps |
| T401 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.1249231448 |
|
|
Aug 04 07:25:23 PM PDT 24 |
Aug 04 08:36:43 PM PDT 24 |
15827431699 ps |
| T327 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3340600313 |
|
|
Aug 04 07:39:02 PM PDT 24 |
Aug 04 08:24:47 PM PDT 24 |
35182590472 ps |
| T525 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.783638399 |
|
|
Aug 04 07:45:44 PM PDT 24 |
Aug 04 07:51:24 PM PDT 24 |
2726639800 ps |
| T115 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.1597049975 |
|
|
Aug 04 07:33:36 PM PDT 24 |
Aug 04 07:41:28 PM PDT 24 |
5689164120 ps |
| T153 |
/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.1340907104 |
|
|
Aug 04 07:42:33 PM PDT 24 |
Aug 04 07:54:20 PM PDT 24 |
8307595822 ps |
| T65 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1773833528 |
|
|
Aug 04 07:33:40 PM PDT 24 |
Aug 04 07:56:25 PM PDT 24 |
8355738316 ps |
| T405 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.1119822589 |
|
|
Aug 04 07:21:43 PM PDT 24 |
Aug 04 08:10:12 PM PDT 24 |
10998766100 ps |
| T402 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.2055225943 |
|
|
Aug 04 07:51:50 PM PDT 24 |
Aug 04 08:53:32 PM PDT 24 |
14959293817 ps |
| T324 |
/workspace/coverage/default/2.chip_sw_aon_timer_irq.852714928 |
|
|
Aug 04 07:39:20 PM PDT 24 |
Aug 04 07:46:30 PM PDT 24 |
4303369080 ps |
| T195 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.4257214675 |
|
|
Aug 04 07:40:26 PM PDT 24 |
Aug 04 08:38:43 PM PDT 24 |
17605510700 ps |
| T526 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.924712862 |
|
|
Aug 04 07:33:34 PM PDT 24 |
Aug 04 07:55:38 PM PDT 24 |
5676759750 ps |
| T149 |
/workspace/coverage/default/98.chip_sw_all_escalation_resets.1236007686 |
|
|
Aug 04 08:01:22 PM PDT 24 |
Aug 04 08:09:09 PM PDT 24 |
5010719296 ps |
| T275 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.2232284293 |
|
|
Aug 04 07:39:56 PM PDT 24 |
Aug 04 07:57:15 PM PDT 24 |
6076166500 ps |
| T10 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through.3554111649 |
|
|
Aug 04 07:37:49 PM PDT 24 |
Aug 04 07:52:47 PM PDT 24 |
7201348452 ps |
| T527 |
/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.3426700130 |
|
|
Aug 04 07:47:24 PM PDT 24 |
Aug 04 07:52:56 PM PDT 24 |
3700793704 ps |
| T528 |
/workspace/coverage/default/11.chip_sw_lc_ctrl_transition.330874615 |
|
|
Aug 04 07:51:39 PM PDT 24 |
Aug 04 08:03:03 PM PDT 24 |
10949290177 ps |
| T17 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.506069404 |
|
|
Aug 04 07:44:50 PM PDT 24 |
Aug 04 08:09:23 PM PDT 24 |
23416759500 ps |
| T529 |
/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.1228088986 |
|
|
Aug 04 07:34:27 PM PDT 24 |
Aug 04 07:38:30 PM PDT 24 |
3473754808 ps |
| T47 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.611236991 |
|
|
Aug 04 07:24:45 PM PDT 24 |
Aug 04 08:52:29 PM PDT 24 |
22589136855 ps |
| T52 |
/workspace/coverage/default/2.chip_jtag_csr_rw.2538820230 |
|
|
Aug 04 07:37:40 PM PDT 24 |
Aug 04 07:59:11 PM PDT 24 |
12759614764 ps |
| T416 |
/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.3798508375 |
|
|
Aug 04 07:54:04 PM PDT 24 |
Aug 04 08:01:24 PM PDT 24 |
3851088320 ps |
| T98 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.3491418503 |
|
|
Aug 04 07:28:52 PM PDT 24 |
Aug 04 08:01:43 PM PDT 24 |
8208044140 ps |
| T260 |
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.504143099 |
|
|
Aug 04 07:49:57 PM PDT 24 |
Aug 04 08:01:50 PM PDT 24 |
5712441164 ps |
| T53 |
/workspace/coverage/default/0.chip_jtag_mem_access.4126876066 |
|
|
Aug 04 07:08:47 PM PDT 24 |
Aug 04 07:32:42 PM PDT 24 |
13305945404 ps |
| T67 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.4153670258 |
|
|
Aug 04 07:31:46 PM PDT 24 |
Aug 04 07:41:49 PM PDT 24 |
4239083272 ps |
| T348 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx.2842569389 |
|
|
Aug 04 07:13:39 PM PDT 24 |
Aug 04 07:24:49 PM PDT 24 |
4453051742 ps |
| T99 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.1111106889 |
|
|
Aug 04 07:41:23 PM PDT 24 |
Aug 04 08:07:06 PM PDT 24 |
13440193142 ps |
| T417 |
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2854141596 |
|
|
Aug 04 08:00:30 PM PDT 24 |
Aug 04 08:08:26 PM PDT 24 |
3520225200 ps |
| T418 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.4202889745 |
|
|
Aug 04 07:32:34 PM PDT 24 |
Aug 04 07:54:16 PM PDT 24 |
7138471729 ps |
| T530 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.870398285 |
|
|
Aug 04 07:38:37 PM PDT 24 |
Aug 04 08:00:28 PM PDT 24 |
5796875363 ps |
| T168 |
/workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.48115269 |
|
|
Aug 04 07:52:23 PM PDT 24 |
Aug 04 08:53:46 PM PDT 24 |
16370699432 ps |
| T57 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.266162179 |
|
|
Aug 04 07:17:53 PM PDT 24 |
Aug 04 07:22:00 PM PDT 24 |
3259675387 ps |
| T68 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3013127631 |
|
|
Aug 04 07:17:01 PM PDT 24 |
Aug 04 07:24:36 PM PDT 24 |
4050090906 ps |
| T531 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2670850319 |
|
|
Aug 04 07:17:21 PM PDT 24 |
Aug 04 07:32:14 PM PDT 24 |
11291124025 ps |
| T362 |
/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3564325235 |
|
|
Aug 04 07:53:48 PM PDT 24 |
Aug 04 07:59:24 PM PDT 24 |
3142411848 ps |
| T69 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.671957225 |
|
|
Aug 04 07:45:51 PM PDT 24 |
Aug 04 07:58:00 PM PDT 24 |
3500200470 ps |
| T159 |
/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.2550399921 |
|
|
Aug 04 07:38:00 PM PDT 24 |
Aug 04 08:07:55 PM PDT 24 |
15652642872 ps |
| T408 |
/workspace/coverage/default/2.chip_sw_edn_sw_mode.149742357 |
|
|
Aug 04 07:42:06 PM PDT 24 |
Aug 04 08:11:47 PM PDT 24 |
8501785428 ps |
| T78 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1874775843 |
|
|
Aug 04 07:30:46 PM PDT 24 |
Aug 04 07:39:44 PM PDT 24 |
6707635480 ps |
| T120 |
/workspace/coverage/default/0.chip_tap_straps_dev.3366300527 |
|
|
Aug 04 07:16:02 PM PDT 24 |
Aug 04 07:37:09 PM PDT 24 |
12913073075 ps |
| T269 |
/workspace/coverage/default/2.chip_sw_plic_sw_irq.4147909295 |
|
|
Aug 04 07:43:10 PM PDT 24 |
Aug 04 07:47:41 PM PDT 24 |
3235002348 ps |
| T162 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.2223432673 |
|
|
Aug 04 07:33:51 PM PDT 24 |
Aug 04 07:38:20 PM PDT 24 |
2531036281 ps |
| T435 |
/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.168352503 |
|
|
Aug 04 07:53:52 PM PDT 24 |
Aug 04 07:59:41 PM PDT 24 |
3708118664 ps |
| T163 |
/workspace/coverage/default/2.rom_e2e_self_hash.1836143653 |
|
|
Aug 04 07:53:40 PM PDT 24 |
Aug 04 09:34:28 PM PDT 24 |
27359088968 ps |
| T321 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.75031075 |
|
|
Aug 04 07:48:04 PM PDT 24 |
Aug 04 07:57:28 PM PDT 24 |
4326266182 ps |
| T22 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.1192521002 |
|
|
Aug 04 07:40:38 PM PDT 24 |
Aug 04 07:46:58 PM PDT 24 |
3251308456 ps |
| T165 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.168022216 |
|
|
Aug 04 07:16:13 PM PDT 24 |
Aug 04 07:20:35 PM PDT 24 |
3350600990 ps |
| T389 |
/workspace/coverage/default/3.chip_sw_all_escalation_resets.3648423316 |
|
|
Aug 04 07:50:04 PM PDT 24 |
Aug 04 08:01:58 PM PDT 24 |
5432054998 ps |
| T441 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3278174976 |
|
|
Aug 04 07:16:02 PM PDT 24 |
Aug 04 08:15:27 PM PDT 24 |
32674267924 ps |
| T532 |
/workspace/coverage/default/1.rom_e2e_asm_init_rma.1492138228 |
|
|
Aug 04 07:38:25 PM PDT 24 |
Aug 04 08:48:03 PM PDT 24 |
15038553334 ps |
| T167 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.78584749 |
|
|
Aug 04 07:16:57 PM PDT 24 |
Aug 04 07:21:54 PM PDT 24 |
3825029688 ps |
| T18 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3131628151 |
|
|
Aug 04 07:46:38 PM PDT 24 |
Aug 04 07:52:42 PM PDT 24 |
7761272568 ps |
| T11 |
/workspace/coverage/default/0.chip_sw_power_virus.1689778779 |
|
|
Aug 04 07:22:09 PM PDT 24 |
Aug 04 07:47:49 PM PDT 24 |
5888117108 ps |
| T533 |
/workspace/coverage/default/2.chip_sw_example_manufacturer.2394244762 |
|
|
Aug 04 07:36:09 PM PDT 24 |
Aug 04 07:39:54 PM PDT 24 |
3547947400 ps |
| T19 |
/workspace/coverage/default/0.chip_sw_usbdev_config_host.2122276270 |
|
|
Aug 04 07:13:56 PM PDT 24 |
Aug 04 07:45:26 PM PDT 24 |
8006474478 ps |
| T392 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3374283199 |
|
|
Aug 04 07:14:49 PM PDT 24 |
Aug 04 07:35:45 PM PDT 24 |
12208171973 ps |
| T534 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.193626481 |
|
|
Aug 04 07:27:08 PM PDT 24 |
Aug 04 07:46:55 PM PDT 24 |
10489676290 ps |
| T448 |
/workspace/coverage/default/76.chip_sw_all_escalation_resets.153494329 |
|
|
Aug 04 08:00:51 PM PDT 24 |
Aug 04 08:11:54 PM PDT 24 |
6334736048 ps |
| T205 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.1820649893 |
|
|
Aug 04 07:15:42 PM PDT 24 |
Aug 04 07:30:32 PM PDT 24 |
7908191688 ps |
| T440 |
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3565380048 |
|
|
Aug 04 07:58:48 PM PDT 24 |
Aug 04 08:04:25 PM PDT 24 |
4104717912 ps |
| T397 |
/workspace/coverage/default/21.chip_sw_all_escalation_resets.1629740174 |
|
|
Aug 04 07:54:19 PM PDT 24 |
Aug 04 08:05:52 PM PDT 24 |
4663326560 ps |
| T535 |
/workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.2369988242 |
|
|
Aug 04 07:23:50 PM PDT 24 |
Aug 04 08:26:52 PM PDT 24 |
14726829262 ps |
| T20 |
/workspace/coverage/default/0.chip_sw_usbdev_pincfg.3984335554 |
|
|
Aug 04 07:13:07 PM PDT 24 |
Aug 04 09:19:36 PM PDT 24 |
31683455136 ps |
| T176 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.1093798926 |
|
|
Aug 04 07:38:21 PM PDT 24 |
Aug 04 07:58:25 PM PDT 24 |
6968141536 ps |
| T227 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.1190944590 |
|
|
Aug 04 07:23:04 PM PDT 24 |
Aug 04 07:34:34 PM PDT 24 |
5068062226 ps |
| T536 |
/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.507049966 |
|
|
Aug 04 07:47:31 PM PDT 24 |
Aug 04 07:50:15 PM PDT 24 |
2283968660 ps |
| T75 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.2516859099 |
|
|
Aug 04 07:32:22 PM PDT 24 |
Aug 04 08:00:25 PM PDT 24 |
9658487931 ps |
| T419 |
/workspace/coverage/default/74.chip_sw_all_escalation_resets.847565451 |
|
|
Aug 04 08:00:03 PM PDT 24 |
Aug 04 08:11:14 PM PDT 24 |
5535750200 ps |
| T537 |
/workspace/coverage/default/1.rom_e2e_asm_init_dev.39514865 |
|
|
Aug 04 07:37:34 PM PDT 24 |
Aug 04 08:41:04 PM PDT 24 |
15571191170 ps |
| T58 |
/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3226454316 |
|
|
Aug 04 07:14:31 PM PDT 24 |
Aug 04 07:20:19 PM PDT 24 |
9222133246 ps |
| T196 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.4129893297 |
|
|
Aug 04 07:30:02 PM PDT 24 |
Aug 04 08:37:42 PM PDT 24 |
17683734328 ps |
| T222 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.1767138802 |
|
|
Aug 04 07:33:25 PM PDT 24 |
Aug 04 07:38:27 PM PDT 24 |
2968856842 ps |
| T216 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.632787605 |
|
|
Aug 04 07:13:54 PM PDT 24 |
Aug 04 07:18:02 PM PDT 24 |
3222303063 ps |
| T261 |
/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.1720614896 |
|
|
Aug 04 07:13:16 PM PDT 24 |
Aug 04 07:21:10 PM PDT 24 |
3815968058 ps |
| T124 |
/workspace/coverage/default/0.chip_sw_alert_handler_entropy.3560239110 |
|
|
Aug 04 07:14:17 PM PDT 24 |
Aug 04 07:20:32 PM PDT 24 |
3760871053 ps |
| T139 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1088464296 |
|
|
Aug 04 07:16:35 PM PDT 24 |
Aug 04 07:48:29 PM PDT 24 |
25060107568 ps |
| T48 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.3974993278 |
|
|
Aug 04 07:23:35 PM PDT 24 |
Aug 04 08:23:43 PM PDT 24 |
14310674727 ps |
| T538 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.436557506 |
|
|
Aug 04 07:26:36 PM PDT 24 |
Aug 04 08:47:32 PM PDT 24 |
15859587700 ps |
| T508 |
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.1631280959 |
|
|
Aug 04 07:51:37 PM PDT 24 |
Aug 04 07:57:01 PM PDT 24 |
3344238700 ps |
| T368 |
/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.1246675928 |
|
|
Aug 04 07:39:53 PM PDT 24 |
Aug 04 08:06:36 PM PDT 24 |
10070153569 ps |
| T323 |
/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.2944967485 |
|
|
Aug 04 07:21:19 PM PDT 24 |
Aug 04 07:43:16 PM PDT 24 |
9376836970 ps |
| T363 |
/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.3284551212 |
|
|
Aug 04 07:52:20 PM PDT 24 |
Aug 04 08:01:22 PM PDT 24 |
4816584776 ps |
| T23 |
/workspace/coverage/default/0.chip_sw_usbdev_stream.2897519273 |
|
|
Aug 04 07:14:09 PM PDT 24 |
Aug 04 08:35:55 PM PDT 24 |
18302598694 ps |
| T107 |
/workspace/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.3147597557 |
|
|
Aug 04 07:37:23 PM PDT 24 |
Aug 04 07:42:34 PM PDT 24 |
3467692322 ps |
| T391 |
/workspace/coverage/default/95.chip_sw_all_escalation_resets.1628375849 |
|
|
Aug 04 08:02:02 PM PDT 24 |
Aug 04 08:11:30 PM PDT 24 |
5260181216 ps |
| T539 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.4142033641 |
|
|
Aug 04 07:22:39 PM PDT 24 |
Aug 04 08:43:52 PM PDT 24 |
17566749709 ps |
| T390 |
/workspace/coverage/default/49.chip_sw_all_escalation_resets.1105076371 |
|
|
Aug 04 07:56:51 PM PDT 24 |
Aug 04 08:07:03 PM PDT 24 |
6017782096 ps |
| T540 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.4252463826 |
|
|
Aug 04 07:36:33 PM PDT 24 |
Aug 04 07:53:05 PM PDT 24 |
6415469217 ps |
| T541 |
/workspace/coverage/default/1.chip_sw_example_manufacturer.3542755065 |
|
|
Aug 04 07:20:53 PM PDT 24 |
Aug 04 07:24:59 PM PDT 24 |
2748146540 ps |
| T542 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod.1380221843 |
|
|
Aug 04 07:52:17 PM PDT 24 |
Aug 04 08:45:20 PM PDT 24 |
15194754709 ps |
| T177 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.2705329698 |
|
|
Aug 04 07:24:33 PM PDT 24 |
Aug 04 07:49:54 PM PDT 24 |
8603072778 ps |
| T543 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.3150647687 |
|
|
Aug 04 07:24:59 PM PDT 24 |
Aug 04 07:33:42 PM PDT 24 |
4908937400 ps |
| T544 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.4222343706 |
|
|
Aug 04 07:39:40 PM PDT 24 |
Aug 04 07:51:52 PM PDT 24 |
4444617468 ps |
| T337 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.2414122229 |
|
|
Aug 04 07:29:42 PM PDT 24 |
Aug 04 07:43:50 PM PDT 24 |
6557715736 ps |
| T442 |
/workspace/coverage/default/2.chip_sw_ast_clk_outputs.608741286 |
|
|
Aug 04 07:46:38 PM PDT 24 |
Aug 04 08:05:32 PM PDT 24 |
7392304000 ps |
| T515 |
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1026779345 |
|
|
Aug 04 07:57:02 PM PDT 24 |
Aug 04 08:03:23 PM PDT 24 |
3715007896 ps |
| T545 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.4214936934 |
|
|
Aug 04 07:38:03 PM PDT 24 |
Aug 04 07:43:54 PM PDT 24 |
4520005420 ps |
| T370 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.4276752356 |
|
|
Aug 04 07:21:16 PM PDT 24 |
Aug 04 07:25:25 PM PDT 24 |
2743535072 ps |
| T349 |
/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.2735239322 |
|
|
Aug 04 07:51:58 PM PDT 24 |
Aug 04 08:03:10 PM PDT 24 |
4357535150 ps |
| T546 |
/workspace/coverage/default/0.chip_sw_usbdev_vbus.3534931355 |
|
|
Aug 04 07:15:49 PM PDT 24 |
Aug 04 07:19:42 PM PDT 24 |
3055908714 ps |
| T547 |
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.3715429621 |
|
|
Aug 04 07:49:38 PM PDT 24 |
Aug 04 08:06:15 PM PDT 24 |
13945406584 ps |
| T268 |
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.2986815449 |
|
|
Aug 04 07:50:58 PM PDT 24 |
Aug 04 08:03:29 PM PDT 24 |
5317257320 ps |
| T150 |
/workspace/coverage/default/1.chip_jtag_mem_access.3191298987 |
|
|
Aug 04 07:24:34 PM PDT 24 |
Aug 04 07:51:18 PM PDT 24 |
13377419755 ps |
| T228 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.3380816033 |
|
|
Aug 04 07:14:24 PM PDT 24 |
Aug 04 07:28:59 PM PDT 24 |
5805699630 ps |
| T257 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.982325706 |
|
|
Aug 04 07:15:51 PM PDT 24 |
Aug 04 07:25:48 PM PDT 24 |
4434560997 ps |
| T548 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.1923561561 |
|
|
Aug 04 07:48:06 PM PDT 24 |
Aug 04 08:00:32 PM PDT 24 |
4572791800 ps |
| T549 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.1311362740 |
|
|
Aug 04 07:50:14 PM PDT 24 |
Aug 04 08:00:15 PM PDT 24 |
4202677764 ps |
| T550 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.199940104 |
|
|
Aug 04 07:47:45 PM PDT 24 |
Aug 04 07:51:34 PM PDT 24 |
3251773510 ps |
| T551 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access.416145614 |
|
|
Aug 04 07:14:06 PM PDT 24 |
Aug 04 07:28:44 PM PDT 24 |
5145195750 ps |
| T371 |
/workspace/coverage/default/34.chip_sw_all_escalation_resets.154863833 |
|
|
Aug 04 07:55:29 PM PDT 24 |
Aug 04 08:06:40 PM PDT 24 |
5801472920 ps |
| T339 |
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.386062011 |
|
|
Aug 04 07:58:38 PM PDT 24 |
Aug 04 08:06:52 PM PDT 24 |
4433739160 ps |
| T265 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.2451232155 |
|
|
Aug 04 07:21:55 PM PDT 24 |
Aug 04 08:54:38 PM PDT 24 |
23764678460 ps |
| T40 |
/workspace/coverage/default/0.chip_sw_spi_device_tpm.2052638164 |
|
|
Aug 04 07:15:18 PM PDT 24 |
Aug 04 07:21:47 PM PDT 24 |
3971083639 ps |
| T338 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.2814725978 |
|
|
Aug 04 07:44:58 PM PDT 24 |
Aug 04 07:55:19 PM PDT 24 |
4586415346 ps |
| T386 |
/workspace/coverage/default/33.chip_sw_all_escalation_resets.770428726 |
|
|
Aug 04 07:55:57 PM PDT 24 |
Aug 04 08:09:01 PM PDT 24 |
6049486624 ps |
| T194 |
/workspace/coverage/default/0.chip_sw_hmac_enc.736219602 |
|
|
Aug 04 07:15:39 PM PDT 24 |
Aug 04 07:21:14 PM PDT 24 |
3273733528 ps |
| T154 |
/workspace/coverage/default/81.chip_sw_all_escalation_resets.2628164027 |
|
|
Aug 04 08:00:07 PM PDT 24 |
Aug 04 08:09:26 PM PDT 24 |
5009779580 ps |
| T552 |
/workspace/coverage/default/1.chip_sw_ast_clk_outputs.3644665539 |
|
|
Aug 04 07:32:37 PM PDT 24 |
Aug 04 07:50:52 PM PDT 24 |
8636779740 ps |
| T262 |
/workspace/coverage/default/48.chip_sw_all_escalation_resets.2048276315 |
|
|
Aug 04 07:56:26 PM PDT 24 |
Aug 04 08:04:58 PM PDT 24 |
5330700016 ps |
| T553 |
/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.835819472 |
|
|
Aug 04 07:47:50 PM PDT 24 |
Aug 04 07:52:28 PM PDT 24 |
2981858260 ps |
| T554 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.3265216041 |
|
|
Aug 04 07:14:29 PM PDT 24 |
Aug 04 07:18:24 PM PDT 24 |
2301069673 ps |
| T555 |
/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.230931291 |
|
|
Aug 04 07:39:34 PM PDT 24 |
Aug 04 07:48:41 PM PDT 24 |
4594345728 ps |
| T556 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.2567021663 |
|
|
Aug 04 07:26:00 PM PDT 24 |
Aug 04 08:23:55 PM PDT 24 |
11510526910 ps |
| T557 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.1713205475 |
|
|
Aug 04 07:33:46 PM PDT 24 |
Aug 04 07:39:07 PM PDT 24 |
2535662720 ps |
| T81 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3811340188 |
|
|
Aug 04 07:43:27 PM PDT 24 |
Aug 04 08:01:55 PM PDT 24 |
7021313912 ps |
| T446 |
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1395346985 |
|
|
Aug 04 08:00:18 PM PDT 24 |
Aug 04 08:06:01 PM PDT 24 |
4163700704 ps |
| T558 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.2893867305 |
|
|
Aug 04 07:49:12 PM PDT 24 |
Aug 04 08:00:24 PM PDT 24 |
4962374680 ps |
| T258 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.1447736719 |
|
|
Aug 04 07:24:32 PM PDT 24 |
Aug 04 07:33:29 PM PDT 24 |
3977742520 ps |
| T559 |
/workspace/coverage/default/0.chip_sw_kmac_idle.1709875481 |
|
|
Aug 04 07:14:13 PM PDT 24 |
Aug 04 07:17:34 PM PDT 24 |
3005117072 ps |
| T560 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.3928186283 |
|
|
Aug 04 07:14:15 PM PDT 24 |
Aug 04 07:27:42 PM PDT 24 |
6588700446 ps |
| T443 |
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2890880863 |
|
|
Aug 04 07:58:43 PM PDT 24 |
Aug 04 08:06:47 PM PDT 24 |
4447270384 ps |
| T444 |
/workspace/coverage/default/35.chip_sw_all_escalation_resets.3055006983 |
|
|
Aug 04 07:55:34 PM PDT 24 |
Aug 04 08:05:24 PM PDT 24 |
5659078660 ps |
| T437 |
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.683663243 |
|
|
Aug 04 07:59:54 PM PDT 24 |
Aug 04 08:05:57 PM PDT 24 |
3507590230 ps |
| T498 |
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.2316022514 |
|
|
Aug 04 07:55:06 PM PDT 24 |
Aug 04 08:01:25 PM PDT 24 |
3660779284 ps |
| T38 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4175511927 |
|
|
Aug 04 07:14:36 PM PDT 24 |
Aug 04 07:23:04 PM PDT 24 |
6707414496 ps |
| T449 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1038632170 |
|
|
Aug 04 07:15:05 PM PDT 24 |
Aug 04 07:21:41 PM PDT 24 |
3677029272 ps |
| T407 |
/workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.2414245461 |
|
|
Aug 04 07:51:57 PM PDT 24 |
Aug 04 09:23:51 PM PDT 24 |
26573920336 ps |
| T76 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.276585703 |
|
|
Aug 04 07:19:00 PM PDT 24 |
Aug 04 11:58:44 PM PDT 24 |
120930561736 ps |
| T393 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2098410339 |
|
|
Aug 04 07:39:56 PM PDT 24 |
Aug 04 07:58:14 PM PDT 24 |
9651698196 ps |
| T458 |
/workspace/coverage/default/54.chip_sw_all_escalation_resets.2348297552 |
|
|
Aug 04 07:58:26 PM PDT 24 |
Aug 04 08:08:42 PM PDT 24 |
5804434674 ps |
| T230 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.2764520809 |
|
|
Aug 04 07:14:47 PM PDT 24 |
Aug 04 07:29:07 PM PDT 24 |
5810191688 ps |
| T561 |
/workspace/coverage/default/2.rom_e2e_asm_init_dev.2990762391 |
|
|
Aug 04 07:50:12 PM PDT 24 |
Aug 04 08:49:49 PM PDT 24 |
15404044399 ps |
| T108 |
/workspace/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.1545389407 |
|
|
Aug 04 07:23:58 PM PDT 24 |
Aug 04 07:29:16 PM PDT 24 |
3391875355 ps |
| T209 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.11726718 |
|
|
Aug 04 07:31:24 PM PDT 24 |
Aug 04 07:39:53 PM PDT 24 |
4336936600 ps |
| T126 |
/workspace/coverage/default/20.chip_sw_all_escalation_resets.3496768922 |
|
|
Aug 04 07:54:02 PM PDT 24 |
Aug 04 08:07:05 PM PDT 24 |
5090952680 ps |
| T131 |
/workspace/coverage/default/0.chip_sw_uart_smoketest.1236690520 |
|
|
Aug 04 07:20:33 PM PDT 24 |
Aug 04 07:25:02 PM PDT 24 |
3148701704 ps |
| T132 |
/workspace/coverage/default/1.chip_sw_sleep_pin_wake.4216427549 |
|
|
Aug 04 07:23:19 PM PDT 24 |
Aug 04 07:31:25 PM PDT 24 |
5999556000 ps |
| T133 |
/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.723902705 |
|
|
Aug 04 07:14:50 PM PDT 24 |
Aug 04 07:19:48 PM PDT 24 |
3010584280 ps |
| T134 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2649431543 |
|
|
Aug 04 07:31:12 PM PDT 24 |
Aug 04 07:41:49 PM PDT 24 |
4373105784 ps |
| T135 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.2667688767 |
|
|
Aug 04 07:17:41 PM PDT 24 |
Aug 04 08:24:51 PM PDT 24 |
19181798492 ps |
| T136 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access.620750756 |
|
|
Aug 04 07:27:13 PM PDT 24 |
Aug 04 07:44:07 PM PDT 24 |
5457186920 ps |
| T137 |
/workspace/coverage/default/3.chip_tap_straps_prod.2208912334 |
|
|
Aug 04 07:48:38 PM PDT 24 |
Aug 04 07:51:31 PM PDT 24 |
2361398909 ps |
| T138 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.1341237804 |
|
|
Aug 04 07:29:39 PM PDT 24 |
Aug 04 07:42:12 PM PDT 24 |
4636872901 ps |
| T110 |
/workspace/coverage/default/1.chip_jtag_csr_rw.240350244 |
|
|
Aug 04 07:24:40 PM PDT 24 |
Aug 04 07:48:59 PM PDT 24 |
13998385396 ps |
| T562 |
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.2299049140 |
|
|
Aug 04 07:51:41 PM PDT 24 |
Aug 04 08:02:52 PM PDT 24 |
4048262932 ps |
| T563 |
/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.260056300 |
|
|
Aug 04 07:22:53 PM PDT 24 |
Aug 04 08:21:24 PM PDT 24 |
10750494161 ps |
| T121 |
/workspace/coverage/default/1.chip_tap_straps_dev.1932411994 |
|
|
Aug 04 07:31:58 PM PDT 24 |
Aug 04 07:44:22 PM PDT 24 |
7210199885 ps |
| T24 |
/workspace/coverage/default/2.chip_sw_sleep_pin_retention.3270288894 |
|
|
Aug 04 07:36:11 PM PDT 24 |
Aug 04 07:42:12 PM PDT 24 |
3675466744 ps |
| T564 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.4106257036 |
|
|
Aug 04 07:49:46 PM PDT 24 |
Aug 04 08:13:41 PM PDT 24 |
8347695340 ps |
| T140 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.1271220895 |
|
|
Aug 04 07:31:41 PM PDT 24 |
Aug 04 07:59:56 PM PDT 24 |
21676271082 ps |
| T273 |
/workspace/coverage/default/1.chip_sw_rv_timer_irq.116955398 |
|
|
Aug 04 07:27:18 PM PDT 24 |
Aug 04 07:31:12 PM PDT 24 |
2617522652 ps |
| T447 |
/workspace/coverage/default/92.chip_sw_all_escalation_resets.3915428061 |
|
|
Aug 04 08:01:33 PM PDT 24 |
Aug 04 08:11:16 PM PDT 24 |
5728884040 ps |