Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	533026587	61379307	0	0
DepthKnown_A	533026587	532918287	0	0
RvalidKnown_A	533026587	532918287	0	0
WreadyKnown_A	533026587	532918287	0	0
gen_passthru_fifo.paramCheckPass	1026	1026	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	61379307	0	0
T1	137560	18862	0	0
T2	248642	32232	0	0
T3	281099	36633	0	0
T32	744770	105186	0	0
T37	160879	18304	0	0
T60	605720	63359	0	0
T61	171927	17828	0	0
T63	144054	43770	0	0
T113	260637	34113	0	0
T125	230926	22865	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	532918287	0	0
T1	137560	137509	0	0
T2	248642	248533	0	0
T3	281099	280993	0	0
T32	744770	744650	0	0
T37	160879	160770	0	0
T60	605720	605327	0	0
T61	171927	171531	0	0
T63	144054	144048	0	0
T113	260637	260524	0	0
T125	230926	230802	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	532918287	0	0
T1	137560	137509	0	0
T2	248642	248533	0	0
T3	281099	280993	0	0
T32	744770	744650	0	0
T37	160879	160770	0	0
T60	605720	605327	0	0
T61	171927	171531	0	0
T63	144054	144048	0	0
T113	260637	260524	0	0
T125	230926	230802	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	532918287	0	0
T1	137560	137509	0	0
T2	248642	248533	0	0
T3	281099	280993	0	0
T32	744770	744650	0	0
T37	160879	160770	0	0
T60	605720	605327	0	0
T61	171927	171531	0	0
T63	144054	144048	0	0
T113	260637	260524	0	0
T125	230926	230802	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1026	1026	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T32	1	1	0	0
T37	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T63	1	1	0	0
T113	1	1	0	0
T125	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	533026587	47572568	0	0
DepthKnown_A	533026587	532918287	0	0
RvalidKnown_A	533026587	532918287	0	0
WreadyKnown_A	533026587	532918287	0	0
gen_passthru_fifo.paramCheckPass	1026	1026	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	47572568	0	0
T1	137560	13563	0	0
T2	248642	22785	0	0
T3	281099	27189	0	0
T32	744770	98274	0	0
T37	160879	13319	0	0
T60	605720	45902	0	0
T61	171927	14362	0	0
T63	144054	39749	0	0
T113	260637	24543	0	0
T125	230926	16019	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	532918287	0	0
T1	137560	137509	0	0
T2	248642	248533	0	0
T3	281099	280993	0	0
T32	744770	744650	0	0
T37	160879	160770	0	0
T60	605720	605327	0	0
T61	171927	171531	0	0
T63	144054	144048	0	0
T113	260637	260524	0	0
T125	230926	230802	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	532918287	0	0
T1	137560	137509	0	0
T2	248642	248533	0	0
T3	281099	280993	0	0
T32	744770	744650	0	0
T37	160879	160770	0	0
T60	605720	605327	0	0
T61	171927	171531	0	0
T63	144054	144048	0	0
T113	260637	260524	0	0
T125	230926	230802	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	532918287	0	0
T1	137560	137509	0	0
T2	248642	248533	0	0
T3	281099	280993	0	0
T32	744770	744650	0	0
T37	160879	160770	0	0
T60	605720	605327	0	0
T61	171927	171531	0	0
T63	144054	144048	0	0
T113	260637	260524	0	0
T125	230926	230802	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1026	1026	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T32	1	1	0	0
T37	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T63	1	1	0	0
T113	1	1	0	0
T125	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	533026587	44459590	0	0
DepthKnown_A	533026587	532918287	0	0
RvalidKnown_A	533026587	532918287	0	0
WreadyKnown_A	533026587	532918287	0	0
gen_passthru_fifo.paramCheckPass	1026	1026	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	44459590	0	0
T1	137560	7566	0	0
T2	248642	16307	0	0
T3	281099	19522	0	0
T32	744770	93441	0	0
T37	160879	9857	0	0
T60	605720	26526	0	0
T61	171927	11100	0	0
T63	144054	33193	0	0
T113	260637	17533	0	0
T125	230926	10859	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	532918287	0	0
T1	137560	137509	0	0
T2	248642	248533	0	0
T3	281099	280993	0	0
T32	744770	744650	0	0
T37	160879	160770	0	0
T60	605720	605327	0	0
T61	171927	171531	0	0
T63	144054	144048	0	0
T113	260637	260524	0	0
T125	230926	230802	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	532918287	0	0
T1	137560	137509	0	0
T2	248642	248533	0	0
T3	281099	280993	0	0
T32	744770	744650	0	0
T37	160879	160770	0	0
T60	605720	605327	0	0
T61	171927	171531	0	0
T63	144054	144048	0	0
T113	260637	260524	0	0
T125	230926	230802	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	532918287	0	0
T1	137560	137509	0	0
T2	248642	248533	0	0
T3	281099	280993	0	0
T32	744770	744650	0	0
T37	160879	160770	0	0
T60	605720	605327	0	0
T61	171927	171531	0	0
T63	144054	144048	0	0
T113	260637	260524	0	0
T125	230926	230802	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1026	1026	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T32	1	1	0	0
T37	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T63	1	1	0	0
T113	1	1	0	0
T125	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	533026587	37649646	0	0
DepthKnown_A	533026587	532918287	0	0
RvalidKnown_A	533026587	532918287	0	0
WreadyKnown_A	533026587	532918287	0	0
gen_passthru_fifo.paramCheckPass	1026	1026	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	37649646	0	0
T1	137560	7282	0	0
T2	248642	15928	0	0
T3	281099	19142	0	0
T32	744770	93025	0	0
T37	160879	9508	0	0
T60	605720	25687	0	0
T61	171927	10870	0	0
T63	144054	33018	0	0
T113	260637	17144	0	0
T125	230926	10519	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	532918287	0	0
T1	137560	137509	0	0
T2	248642	248533	0	0
T3	281099	280993	0	0
T32	744770	744650	0	0
T37	160879	160770	0	0
T60	605720	605327	0	0
T61	171927	171531	0	0
T63	144054	144048	0	0
T113	260637	260524	0	0
T125	230926	230802	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	532918287	0	0
T1	137560	137509	0	0
T2	248642	248533	0	0
T3	281099	280993	0	0
T32	744770	744650	0	0
T37	160879	160770	0	0
T60	605720	605327	0	0
T61	171927	171531	0	0
T63	144054	144048	0	0
T113	260637	260524	0	0
T125	230926	230802	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	532918287	0	0
T1	137560	137509	0	0
T2	248642	248533	0	0
T3	281099	280993	0	0
T32	744770	744650	0	0
T37	160879	160770	0	0
T60	605720	605327	0	0
T61	171927	171531	0	0
T63	144054	144048	0	0
T113	260637	260524	0	0
T125	230926	230802	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1026	1026	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T32	1	1	0	0
T37	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T63	1	1	0	0
T113	1	1	0	0
T125	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	533026587	66614	0	0
DepthKnown_A	533026587	532918287	0	0
RvalidKnown_A	533026587	532918287	0	0
WreadyKnown_A	533026587	532918287	0	0
gen_passthru_fifo.paramCheckPass	1026	1026	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	66614	0	0
T1	137560	26	0	0
T2	248642	151	0	0
T3	281099	151	0	0
T32	744770	39	0	0
T37	160879	74	0	0
T60	605720	112	0	0
T61	171927	27	0	0
T63	144054	29	0	0
T113	260637	151	0	0
T125	230926	102	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	532918287	0	0
T1	137560	137509	0	0
T2	248642	248533	0	0
T3	281099	280993	0	0
T32	744770	744650	0	0
T37	160879	160770	0	0
T60	605720	605327	0	0
T61	171927	171531	0	0
T63	144054	144048	0	0
T113	260637	260524	0	0
T125	230926	230802	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	532918287	0	0
T1	137560	137509	0	0
T2	248642	248533	0	0
T3	281099	280993	0	0
T32	744770	744650	0	0
T37	160879	160770	0	0
T60	605720	605327	0	0
T61	171927	171531	0	0
T63	144054	144048	0	0
T113	260637	260524	0	0
T125	230926	230802	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	532918287	0	0
T1	137560	137509	0	0
T2	248642	248533	0	0
T3	281099	280993	0	0
T32	744770	744650	0	0
T37	160879	160770	0	0
T60	605720	605327	0	0
T61	171927	171531	0	0
T63	144054	144048	0	0
T113	260637	260524	0	0
T125	230926	230802	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1026	1026	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T32	1	1	0	0
T37	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T63	1	1	0	0
T113	1	1	0	0
T125	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	533026587	66613	0	0
DepthKnown_A	533026587	532918287	0	0
RvalidKnown_A	533026587	532918287	0	0
WreadyKnown_A	533026587	532918287	0	0
gen_passthru_fifo.paramCheckPass	1026	1026	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	66613	0	0
T1	137560	26	0	0
T2	248642	151	0	0
T3	281099	151	0	0
T32	744770	39	0	0
T37	160879	74	0	0
T60	605720	112	0	0
T61	171927	27	0	0
T63	144054	29	0	0
T113	260637	151	0	0
T125	230926	102	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	532918287	0	0
T1	137560	137509	0	0
T2	248642	248533	0	0
T3	281099	280993	0	0
T32	744770	744650	0	0
T37	160879	160770	0	0
T60	605720	605327	0	0
T61	171927	171531	0	0
T63	144054	144048	0	0
T113	260637	260524	0	0
T125	230926	230802	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	532918287	0	0
T1	137560	137509	0	0
T2	248642	248533	0	0
T3	281099	280993	0	0
T32	744770	744650	0	0
T37	160879	160770	0	0
T60	605720	605327	0	0
T61	171927	171531	0	0
T63	144054	144048	0	0
T113	260637	260524	0	0
T125	230926	230802	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	532918287	0	0
T1	137560	137509	0	0
T2	248642	248533	0	0
T3	281099	280993	0	0
T32	744770	744650	0	0
T37	160879	160770	0	0
T60	605720	605327	0	0
T61	171927	171531	0	0
T63	144054	144048	0	0
T113	260637	260524	0	0
T125	230926	230802	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1026	1026	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T32	1	1	0	0
T37	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T63	1	1	0	0
T113	1	1	0	0
T125	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	533026587	52894	0	0
DepthKnown_A	533026587	532918287	0	0
RvalidKnown_A	533026587	532918287	0	0
WreadyKnown_A	533026587	532918287	0	0
gen_passthru_fifo.paramCheckPass	1026	1026	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	52894	0	0
T1	137560	23	0	0
T2	248642	95	0	0
T3	281099	95	0	0
T32	744770	37	0	0
T37	160879	72	0	0
T60	605720	97	0	0
T61	171927	25	0	0
T63	144054	28	0	0
T113	260637	95	0	0
T125	230926	94	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	532918287	0	0
T1	137560	137509	0	0
T2	248642	248533	0	0
T3	281099	280993	0	0
T32	744770	744650	0	0
T37	160879	160770	0	0
T60	605720	605327	0	0
T61	171927	171531	0	0
T63	144054	144048	0	0
T113	260637	260524	0	0
T125	230926	230802	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	532918287	0	0
T1	137560	137509	0	0
T2	248642	248533	0	0
T3	281099	280993	0	0
T32	744770	744650	0	0
T37	160879	160770	0	0
T60	605720	605327	0	0
T61	171927	171531	0	0
T63	144054	144048	0	0
T113	260637	260524	0	0
T125	230926	230802	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	532918287	0	0
T1	137560	137509	0	0
T2	248642	248533	0	0
T3	281099	280993	0	0
T32	744770	744650	0	0
T37	160879	160770	0	0
T60	605720	605327	0	0
T61	171927	171531	0	0
T63	144054	144048	0	0
T113	260637	260524	0	0
T125	230926	230802	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1026	1026	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T32	1	1	0	0
T37	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T63	1	1	0	0
T113	1	1	0	0
T125	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	533026587	52893	0	0
DepthKnown_A	533026587	532918287	0	0
RvalidKnown_A	533026587	532918287	0	0
WreadyKnown_A	533026587	532918287	0	0
gen_passthru_fifo.paramCheckPass	1026	1026	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	52893	0	0
T1	137560	23	0	0
T2	248642	95	0	0
T3	281099	95	0	0
T32	744770	37	0	0
T37	160879	72	0	0
T60	605720	97	0	0
T61	171927	25	0	0
T63	144054	28	0	0
T113	260637	95	0	0
T125	230926	94	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	532918287	0	0
T1	137560	137509	0	0
T2	248642	248533	0	0
T3	281099	280993	0	0
T32	744770	744650	0	0
T37	160879	160770	0	0
T60	605720	605327	0	0
T61	171927	171531	0	0
T63	144054	144048	0	0
T113	260637	260524	0	0
T125	230926	230802	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	532918287	0	0
T1	137560	137509	0	0
T2	248642	248533	0	0
T3	281099	280993	0	0
T32	744770	744650	0	0
T37	160879	160770	0	0
T60	605720	605327	0	0
T61	171927	171531	0	0
T63	144054	144048	0	0
T113	260637	260524	0	0
T125	230926	230802	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	532918287	0	0
T1	137560	137509	0	0
T2	248642	248533	0	0
T3	281099	280993	0	0
T32	744770	744650	0	0
T37	160879	160770	0	0
T60	605720	605327	0	0
T61	171927	171531	0	0
T63	144054	144048	0	0
T113	260637	260524	0	0
T125	230926	230802	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1026	1026	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T32	1	1	0	0
T37	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T63	1	1	0	0
T113	1	1	0	0
T125	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	533026587	13720	0	0
DepthKnown_A	533026587	532918287	0	0
RvalidKnown_A	533026587	532918287	0	0
WreadyKnown_A	533026587	532918287	0	0
gen_passthru_fifo.paramCheckPass	1026	1026	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	13720	0	0
T1	137560	3	0	0
T2	248642	56	0	0
T3	281099	56	0	0
T32	744770	2	0	0
T37	160879	2	0	0
T60	605720	15	0	0
T61	171927	2	0	0
T63	144054	1	0	0
T113	260637	56	0	0
T125	230926	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	532918287	0	0
T1	137560	137509	0	0
T2	248642	248533	0	0
T3	281099	280993	0	0
T32	744770	744650	0	0
T37	160879	160770	0	0
T60	605720	605327	0	0
T61	171927	171531	0	0
T63	144054	144048	0	0
T113	260637	260524	0	0
T125	230926	230802	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	532918287	0	0
T1	137560	137509	0	0
T2	248642	248533	0	0
T3	281099	280993	0	0
T32	744770	744650	0	0
T37	160879	160770	0	0
T60	605720	605327	0	0
T61	171927	171531	0	0
T63	144054	144048	0	0
T113	260637	260524	0	0
T125	230926	230802	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	532918287	0	0
T1	137560	137509	0	0
T2	248642	248533	0	0
T3	281099	280993	0	0
T32	744770	744650	0	0
T37	160879	160770	0	0
T60	605720	605327	0	0
T61	171927	171531	0	0
T63	144054	144048	0	0
T113	260637	260524	0	0
T125	230926	230802	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1026	1026	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T32	1	1	0	0
T37	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T63	1	1	0	0
T113	1	1	0	0
T125	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	533026587	13720	0	0
DepthKnown_A	533026587	532918287	0	0
RvalidKnown_A	533026587	532918287	0	0
WreadyKnown_A	533026587	532918287	0	0
gen_passthru_fifo.paramCheckPass	1026	1026	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	13720	0	0
T1	137560	3	0	0
T2	248642	56	0	0
T3	281099	56	0	0
T32	744770	2	0	0
T37	160879	2	0	0
T60	605720	15	0	0
T61	171927	2	0	0
T63	144054	1	0	0
T113	260637	56	0	0
T125	230926	8	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	532918287	0	0
T1	137560	137509	0	0
T2	248642	248533	0	0
T3	281099	280993	0	0
T32	744770	744650	0	0
T37	160879	160770	0	0
T60	605720	605327	0	0
T61	171927	171531	0	0
T63	144054	144048	0	0
T113	260637	260524	0	0
T125	230926	230802	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	532918287	0	0
T1	137560	137509	0	0
T2	248642	248533	0	0
T3	281099	280993	0	0
T32	744770	744650	0	0
T37	160879	160770	0	0
T60	605720	605327	0	0
T61	171927	171531	0	0
T63	144054	144048	0	0
T113	260637	260524	0	0
T125	230926	230802	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	532918287	0	0
T1	137560	137509	0	0
T2	248642	248533	0	0
T3	281099	280993	0	0
T32	744770	744650	0	0
T37	160879	160770	0	0
T60	605720	605327	0	0
T61	171927	171531	0	0
T63	144054	144048	0	0
T113	260637	260524	0	0
T125	230926	230802	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1026	1026	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T32	1	1	0	0
T37	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T63	1	1	0	0
T113	1	1	0	0
T125	1	1	0	0