Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T221,T52,T222
0	1	Covered	T221,T222,T110
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T221,T222,T313
1	Covered	T221,T52,T222

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T221,T222,T313
1	Covered	T221,T52,T222

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T221,T222,T110
1	1	Covered	T221,T222,T313

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T221,T52,T222
1	0	Covered	T221,T222,T313
1	1	Covered	T221,T222,T110

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T221,T222,T110

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T221,T52,T222
0	Covered	T221,T222,T313

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T221,T52,T222
0	Covered	T221,T222,T313

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1066053174	1049213150	0	0
CheckNGreaterZero_A	2052	2052	0	0
GntImpliesReady_A	1066053174	8391	0	0
GntImpliesValid_A	1066053174	8391	0	0
GrantKnown_A	1066053174	1049213150	0	0
IdxKnown_A	1066053174	1049213150	0	0
IndexIsCorrect_A	1066053174	8391	0	0
NoReadyValidNoGrant_A	1066053174	0	0	0
Priority_A	1066053174	8391	0	0
ReadyAndValidImplyGrant_A	1066053174	8391	0	0
ReqAndReadyImplyGrant_A	1066053174	8391	0	0
ReqImpliesValid_A	1066053174	8391	0	0
ValidKnown_A	1066053174	1049213150	0	0
gen_data_port_assertion.DataFlow_A	1066053174	8391	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1066053174	1049213150	0	0
T1	275120	275018	0	0
T2	497284	497066	0	0
T3	562198	561986	0	0
T32	1489540	1489300	0	0
T37	321758	321540	0	0
T60	1211440	1210654	0	0
T61	343854	343062	0	0
T63	288108	288096	0	0
T113	521274	521048	0	0
T125	461852	461604	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2052	2052	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T32	2	2	0	0
T37	2	2	0	0
T60	2	2	0	0
T61	2	2	0	0
T63	2	2	0	0
T113	2	2	0	0
T125	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1066053174	8391	0	0
T5	844604	0	0	0
T56	232072	0	0	0
T95	457808	0	0	0
T141	308592	0	0	0
T199	314772	0	0	0
T212	442626	0	0	0
T221	154914	2797	0	0
T222	0	2797	0	0
T272	198306	0	0	0
T313	0	2797	0	0
T316	1321960	0	0	0
T317	305836	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1066053174	8391	0	0
T5	844604	0	0	0
T56	232072	0	0	0
T95	457808	0	0	0
T141	308592	0	0	0
T199	314772	0	0	0
T212	442626	0	0	0
T221	154914	2797	0	0
T222	0	2797	0	0
T272	198306	0	0	0
T313	0	2797	0	0
T316	1321960	0	0	0
T317	305836	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1066053174	1049213150	0	0
T1	275120	275018	0	0
T2	497284	497066	0	0
T3	562198	561986	0	0
T32	1489540	1489300	0	0
T37	321758	321540	0	0
T60	1211440	1210654	0	0
T61	343854	343062	0	0
T63	288108	288096	0	0
T113	521274	521048	0	0
T125	461852	461604	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1066053174	1049213150	0	0
T1	275120	275018	0	0
T2	497284	497066	0	0
T3	562198	561986	0	0
T32	1489540	1489300	0	0
T37	321758	321540	0	0
T60	1211440	1210654	0	0
T61	343854	343062	0	0
T63	288108	288096	0	0
T113	521274	521048	0	0
T125	461852	461604	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1066053174	8391	0	0
T5	844604	0	0	0
T56	232072	0	0	0
T95	457808	0	0	0
T141	308592	0	0	0
T199	314772	0	0	0
T212	442626	0	0	0
T221	154914	2797	0	0
T222	0	2797	0	0
T272	198306	0	0	0
T313	0	2797	0	0
T316	1321960	0	0	0
T317	305836	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1066053174	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1066053174	8391	0	0
T5	844604	0	0	0
T56	232072	0	0	0
T95	457808	0	0	0
T141	308592	0	0	0
T199	314772	0	0	0
T212	442626	0	0	0
T221	154914	2797	0	0
T222	0	2797	0	0
T272	198306	0	0	0
T313	0	2797	0	0
T316	1321960	0	0	0
T317	305836	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1066053174	8391	0	0
T5	844604	0	0	0
T56	232072	0	0	0
T95	457808	0	0	0
T141	308592	0	0	0
T199	314772	0	0	0
T212	442626	0	0	0
T221	154914	2797	0	0
T222	0	2797	0	0
T272	198306	0	0	0
T313	0	2797	0	0
T316	1321960	0	0	0
T317	305836	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1066053174	8391	0	0
T5	844604	0	0	0
T56	232072	0	0	0
T95	457808	0	0	0
T141	308592	0	0	0
T199	314772	0	0	0
T212	442626	0	0	0
T221	154914	2797	0	0
T222	0	2797	0	0
T272	198306	0	0	0
T313	0	2797	0	0
T316	1321960	0	0	0
T317	305836	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1066053174	8391	0	0
T5	844604	0	0	0
T56	232072	0	0	0
T95	457808	0	0	0
T141	308592	0	0	0
T199	314772	0	0	0
T212	442626	0	0	0
T221	154914	2797	0	0
T222	0	2797	0	0
T272	198306	0	0	0
T313	0	2797	0	0
T316	1321960	0	0	0
T317	305836	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1066053174	1049213150	0	0
T1	275120	275018	0	0
T2	497284	497066	0	0
T3	562198	561986	0	0
T32	1489540	1489300	0	0
T37	321758	321540	0	0
T60	1211440	1210654	0	0
T61	343854	343062	0	0
T63	288108	288096	0	0
T113	521274	521048	0	0
T125	461852	461604	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1066053174	8391	0	0
T5	844604	0	0	0
T56	232072	0	0	0
T95	457808	0	0	0
T141	308592	0	0	0
T199	314772	0	0	0
T212	442626	0	0	0
T221	154914	2797	0	0
T222	0	2797	0	0
T272	198306	0	0	0
T313	0	2797	0	0
T316	1321960	0	0	0
T317	305836	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T221,T52,T222
0	1	Covered	T221,T222,T313
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T221,T222,T313
1	Covered	T221,T52,T222

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T221,T222,T313
1	Covered	T221,T52,T222

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T221,T222,T313
1	1	Covered	T221,T222,T313

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T221,T52,T222
1	0	Covered	T221,T222,T313
1	1	Covered	T221,T222,T313

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T221,T222,T313

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T221,T52,T222
0	Covered	T221,T222,T313

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T221,T52,T222
0	Covered	T221,T222,T313

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	533026587	524606575	0	0
CheckNGreaterZero_A	1026	1026	0	0
GntImpliesReady_A	533026587	5202	0	0
GntImpliesValid_A	533026587	5202	0	0
GrantKnown_A	533026587	524606575	0	0
IdxKnown_A	533026587	524606575	0	0
IndexIsCorrect_A	533026587	5202	0	0
NoReadyValidNoGrant_A	533026587	0	0	0
Priority_A	533026587	5202	0	0
ReadyAndValidImplyGrant_A	533026587	5202	0	0
ReqAndReadyImplyGrant_A	533026587	5202	0	0
ReqImpliesValid_A	533026587	5202	0	0
ValidKnown_A	533026587	524606575	0	0
gen_data_port_assertion.DataFlow_A	533026587	5202	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	524606575	0	0
T1	137560	137509	0	0
T2	248642	248533	0	0
T3	281099	280993	0	0
T32	744770	744650	0	0
T37	160879	160770	0	0
T60	605720	605327	0	0
T61	171927	171531	0	0
T63	144054	144048	0	0
T113	260637	260524	0	0
T125	230926	230802	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1026	1026	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T32	1	1	0	0
T37	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T63	1	1	0	0
T113	1	1	0	0
T125	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	5202	0	0
T5	422302	0	0	0
T56	116036	0	0	0
T95	228904	0	0	0
T141	154296	0	0	0
T199	157386	0	0	0
T212	221313	0	0	0
T221	77457	1734	0	0
T222	0	1734	0	0
T272	99153	0	0	0
T313	0	1734	0	0
T316	660980	0	0	0
T317	152918	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	5202	0	0
T5	422302	0	0	0
T56	116036	0	0	0
T95	228904	0	0	0
T141	154296	0	0	0
T199	157386	0	0	0
T212	221313	0	0	0
T221	77457	1734	0	0
T222	0	1734	0	0
T272	99153	0	0	0
T313	0	1734	0	0
T316	660980	0	0	0
T317	152918	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	524606575	0	0
T1	137560	137509	0	0
T2	248642	248533	0	0
T3	281099	280993	0	0
T32	744770	744650	0	0
T37	160879	160770	0	0
T60	605720	605327	0	0
T61	171927	171531	0	0
T63	144054	144048	0	0
T113	260637	260524	0	0
T125	230926	230802	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	524606575	0	0
T1	137560	137509	0	0
T2	248642	248533	0	0
T3	281099	280993	0	0
T32	744770	744650	0	0
T37	160879	160770	0	0
T60	605720	605327	0	0
T61	171927	171531	0	0
T63	144054	144048	0	0
T113	260637	260524	0	0
T125	230926	230802	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	5202	0	0
T5	422302	0	0	0
T56	116036	0	0	0
T95	228904	0	0	0
T141	154296	0	0	0
T199	157386	0	0	0
T212	221313	0	0	0
T221	77457	1734	0	0
T222	0	1734	0	0
T272	99153	0	0	0
T313	0	1734	0	0
T316	660980	0	0	0
T317	152918	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	5202	0	0
T5	422302	0	0	0
T56	116036	0	0	0
T95	228904	0	0	0
T141	154296	0	0	0
T199	157386	0	0	0
T212	221313	0	0	0
T221	77457	1734	0	0
T222	0	1734	0	0
T272	99153	0	0	0
T313	0	1734	0	0
T316	660980	0	0	0
T317	152918	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	5202	0	0
T5	422302	0	0	0
T56	116036	0	0	0
T95	228904	0	0	0
T141	154296	0	0	0
T199	157386	0	0	0
T212	221313	0	0	0
T221	77457	1734	0	0
T222	0	1734	0	0
T272	99153	0	0	0
T313	0	1734	0	0
T316	660980	0	0	0
T317	152918	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	5202	0	0
T5	422302	0	0	0
T56	116036	0	0	0
T95	228904	0	0	0
T141	154296	0	0	0
T199	157386	0	0	0
T212	221313	0	0	0
T221	77457	1734	0	0
T222	0	1734	0	0
T272	99153	0	0	0
T313	0	1734	0	0
T316	660980	0	0	0
T317	152918	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	5202	0	0
T5	422302	0	0	0
T56	116036	0	0	0
T95	228904	0	0	0
T141	154296	0	0	0
T199	157386	0	0	0
T212	221313	0	0	0
T221	77457	1734	0	0
T222	0	1734	0	0
T272	99153	0	0	0
T313	0	1734	0	0
T316	660980	0	0	0
T317	152918	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	524606575	0	0
T1	137560	137509	0	0
T2	248642	248533	0	0
T3	281099	280993	0	0
T32	744770	744650	0	0
T37	160879	160770	0	0
T60	605720	605327	0	0
T61	171927	171531	0	0
T63	144054	144048	0	0
T113	260637	260524	0	0
T125	230926	230802	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	5202	0	0
T5	422302	0	0	0
T56	116036	0	0	0
T95	228904	0	0	0
T141	154296	0	0	0
T199	157386	0	0	0
T212	221313	0	0	0
T221	77457	1734	0	0
T222	0	1734	0	0
T272	99153	0	0	0
T313	0	1734	0	0
T316	660980	0	0	0
T317	152918	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T221,T52,T222
0	1	Covered	T221,T222,T110
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T221,T222,T313
1	Covered	T221,T52,T222

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T221,T222,T313
1	Covered	T221,T52,T222

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T221,T222,T110
1	1	Covered	T221,T222,T313

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T221,T52,T222
1	0	Covered	T221,T222,T313
1	1	Covered	T221,T222,T110

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T221,T222,T110

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T221,T52,T222
0	Covered	T221,T222,T313

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T221,T52,T222
0	Covered	T221,T222,T313

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	533026587	524606575	0	0
CheckNGreaterZero_A	1026	1026	0	0
GntImpliesReady_A	533026587	3189	0	0
GntImpliesValid_A	533026587	3189	0	0
GrantKnown_A	533026587	524606575	0	0
IdxKnown_A	533026587	524606575	0	0
IndexIsCorrect_A	533026587	3189	0	0
NoReadyValidNoGrant_A	533026587	0	0	0
Priority_A	533026587	3189	0	0
ReadyAndValidImplyGrant_A	533026587	3189	0	0
ReqAndReadyImplyGrant_A	533026587	3189	0	0
ReqImpliesValid_A	533026587	3189	0	0
ValidKnown_A	533026587	524606575	0	0
gen_data_port_assertion.DataFlow_A	533026587	3189	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	524606575	0	0
T1	137560	137509	0	0
T2	248642	248533	0	0
T3	281099	280993	0	0
T32	744770	744650	0	0
T37	160879	160770	0	0
T60	605720	605327	0	0
T61	171927	171531	0	0
T63	144054	144048	0	0
T113	260637	260524	0	0
T125	230926	230802	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1026	1026	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T32	1	1	0	0
T37	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T63	1	1	0	0
T113	1	1	0	0
T125	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	3189	0	0
T5	422302	0	0	0
T56	116036	0	0	0
T95	228904	0	0	0
T141	154296	0	0	0
T199	157386	0	0	0
T212	221313	0	0	0
T221	77457	1063	0	0
T222	0	1063	0	0
T272	99153	0	0	0
T313	0	1063	0	0
T316	660980	0	0	0
T317	152918	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	3189	0	0
T5	422302	0	0	0
T56	116036	0	0	0
T95	228904	0	0	0
T141	154296	0	0	0
T199	157386	0	0	0
T212	221313	0	0	0
T221	77457	1063	0	0
T222	0	1063	0	0
T272	99153	0	0	0
T313	0	1063	0	0
T316	660980	0	0	0
T317	152918	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	524606575	0	0
T1	137560	137509	0	0
T2	248642	248533	0	0
T3	281099	280993	0	0
T32	744770	744650	0	0
T37	160879	160770	0	0
T60	605720	605327	0	0
T61	171927	171531	0	0
T63	144054	144048	0	0
T113	260637	260524	0	0
T125	230926	230802	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	524606575	0	0
T1	137560	137509	0	0
T2	248642	248533	0	0
T3	281099	280993	0	0
T32	744770	744650	0	0
T37	160879	160770	0	0
T60	605720	605327	0	0
T61	171927	171531	0	0
T63	144054	144048	0	0
T113	260637	260524	0	0
T125	230926	230802	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	3189	0	0
T5	422302	0	0	0
T56	116036	0	0	0
T95	228904	0	0	0
T141	154296	0	0	0
T199	157386	0	0	0
T212	221313	0	0	0
T221	77457	1063	0	0
T222	0	1063	0	0
T272	99153	0	0	0
T313	0	1063	0	0
T316	660980	0	0	0
T317	152918	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	3189	0	0
T5	422302	0	0	0
T56	116036	0	0	0
T95	228904	0	0	0
T141	154296	0	0	0
T199	157386	0	0	0
T212	221313	0	0	0
T221	77457	1063	0	0
T222	0	1063	0	0
T272	99153	0	0	0
T313	0	1063	0	0
T316	660980	0	0	0
T317	152918	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	3189	0	0
T5	422302	0	0	0
T56	116036	0	0	0
T95	228904	0	0	0
T141	154296	0	0	0
T199	157386	0	0	0
T212	221313	0	0	0
T221	77457	1063	0	0
T222	0	1063	0	0
T272	99153	0	0	0
T313	0	1063	0	0
T316	660980	0	0	0
T317	152918	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	3189	0	0
T5	422302	0	0	0
T56	116036	0	0	0
T95	228904	0	0	0
T141	154296	0	0	0
T199	157386	0	0	0
T212	221313	0	0	0
T221	77457	1063	0	0
T222	0	1063	0	0
T272	99153	0	0	0
T313	0	1063	0	0
T316	660980	0	0	0
T317	152918	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	3189	0	0
T5	422302	0	0	0
T56	116036	0	0	0
T95	228904	0	0	0
T141	154296	0	0	0
T199	157386	0	0	0
T212	221313	0	0	0
T221	77457	1063	0	0
T222	0	1063	0	0
T272	99153	0	0	0
T313	0	1063	0	0
T316	660980	0	0	0
T317	152918	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	524606575	0	0
T1	137560	137509	0	0
T2	248642	248533	0	0
T3	281099	280993	0	0
T32	744770	744650	0	0
T37	160879	160770	0	0
T60	605720	605327	0	0
T61	171927	171531	0	0
T63	144054	144048	0	0
T113	260637	260524	0	0
T125	230926	230802	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	533026587	3189	0	0
T5	422302	0	0	0
T56	116036	0	0	0
T95	228904	0	0	0
T141	154296	0	0	0
T199	157386	0	0	0
T212	221313	0	0	0
T221	77457	1063	0	0
T222	0	1063	0	0
T272	99153	0	0	0
T313	0	1063	0	0
T316	660980	0	0	0
T317	152918	0	0	0