Unified Coverage Report :: Module :: prim_mubi4_sync

Module : prim_mubi4_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync	100.00						100.00

---

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.83	99.34	100.00			100.00	100.00	u_pinmux_strap_sampling

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : prim_mubi4_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1026	1026	0	0
OutputsKnown_A	133379522	132685183	0	0
gen_no_flops.OutputDelay_A	133379522	132685183	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1026	1026	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T32	1	1	0	0
T37	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T63	1	1	0	0
T113	1	1	0	0
T125	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133379522	132685183	0	0
T1	38167	37387	0	0
T2	60883	60417	0	0
T3	69064	68206	0	0
T32	199994	199526	0	0
T37	40888	40192	0	0
T60	150107	149388	0	0
T61	42546	42006	0	0
T63	550875	550437	0	0
T113	63624	63294	0	0
T125	56641	56159	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133379522	132685183	0	0
T1	38167	37387	0	0
T2	60883	60417	0	0
T3	69064	68206	0	0
T32	199994	199526	0	0
T37	40888	40192	0	0
T60	150107	149388	0	0
T61	42546	42006	0	0
T63	550875	550437	0	0
T113	63624	63294	0	0
T125	56641	56159	0	0

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_pinmux_strap_sampling.u_por_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1026	1026	0	0
OutputsKnown_A	133379522	132685183	0	0
gen_no_flops.OutputDelay_A	133379522	132685183	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1026	1026	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T32	1	1	0	0
T37	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T63	1	1	0	0
T113	1	1	0	0
T125	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133379522	132685183	0	0
T1	38167	37387	0	0
T2	60883	60417	0	0
T3	69064	68206	0	0
T32	199994	199526	0	0
T37	40888	40192	0	0
T60	150107	149388	0	0
T61	42546	42006	0	0
T63	550875	550437	0	0
T113	63624	63294	0	0
T125	56641	56159	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133379522	132685183	0	0
T1	38167	37387	0	0
T2	60883	60417	0	0
T3	69064	68206	0	0
T32	199994	199526	0	0
T37	40888	40192	0	0
T60	150107	149388	0	0
T61	42546	42006	0	0
T63	550875	550437	0	0
T113	63624	63294	0	0
T125	56641	56159	0	0