c8985d6745| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | chip_sw_example_tests | chip_sw_example_flash | 4.637m | 3.193ms | 3 | 3 | 100.00 |
| chip_sw_example_rom | 2.569m | 1.848ms | 3 | 3 | 100.00 | ||
| chip_sw_example_manufacturer | 4.095m | 2.748ms | 3 | 3 | 100.00 | ||
| chip_sw_example_concurrency | 4.745m | 2.844ms | 3 | 3 | 100.00 | ||
| V1 | csr_hw_reset | chip_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | chip_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | chip_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | chip_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | chip_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | chip_csr_aliasing | 0 | 5 | 0.00 | ||
| chip_csr_rw | 0 | 20 | 0.00 | ||||
| V1 | xbar_smoke | xbar_smoke | 0 | 100 | 0.00 | ||
| V1 | chip_sw_gpio_out | chip_sw_gpio | 7.565m | 3.900ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_in | chip_sw_gpio | 7.565m | 3.900ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_irq | chip_sw_gpio | 7.565m | 3.900ms | 3 | 3 | 100.00 |
| V1 | chip_sw_uart_tx_rx | chip_sw_uart_tx_rx | 11.151m | 4.453ms | 5 | 5 | 100.00 |
| V1 | chip_sw_uart_rx_overflow | chip_sw_uart_tx_rx | 11.151m | 4.453ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_idx1 | 10.994m | 4.141ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx2 | 12.193m | 4.726ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx3 | 12.431m | 4.573ms | 5 | 5 | 100.00 | ||
| V1 | chip_sw_uart_baud_rate | chip_sw_uart_rand_baudrate | 45.627m | 13.207ms | 20 | 20 | 100.00 |
| V1 | chip_sw_uart_tx_rx_alt_clk_freq | chip_sw_uart_tx_rx_alt_clk_freq | 27.005m | 8.314ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_alt_clk_freq_low_speed | 24.191m | 13.436ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 65 | 220 | 29.55 | |||
| V2 | chip_pin_mux | chip_padctrl_attributes | 5.428m | 4.872ms | 10 | 10 | 100.00 |
| V2 | chip_padctrl_attributes | chip_padctrl_attributes | 5.428m | 4.872ms | 10 | 10 | 100.00 |
| V2 | chip_sw_sleep_pin_mio_dio_val | chip_sw_sleep_pin_mio_dio_val | 4.892m | 3.061ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_wake | chip_sw_sleep_pin_wake | 8.095m | 6.000ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_retention | chip_sw_sleep_pin_retention | 6.014m | 3.675ms | 3 | 3 | 100.00 |
| V2 | chip_sw_tap_strap_sampling | chip_tap_straps_dev | 21.100m | 12.913ms | 5 | 5 | 100.00 |
| chip_tap_straps_testunlock0 | 15.331m | 8.443ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 1.405h | 60.000ms | 4 | 5 | 80.00 | ||
| chip_tap_straps_prod | 35.643m | 17.468ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_pattgen_ios | chip_sw_pattgen_ios | 4.734m | 3.208ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pwm_pulses | chip_sw_sleep_pwm_pulses | 25.389m | 8.532ms | 3 | 3 | 100.00 |
| V2 | chip_sw_data_integrity | chip_sw_data_integrity_escalation | 12.957m | 5.790ms | 6 | 6 | 100.00 |
| V2 | chip_sw_instruction_integrity | chip_sw_data_integrity_escalation | 12.957m | 5.790ms | 6 | 6 | 100.00 |
| V2 | chip_sw_ast_clk_outputs | chip_sw_ast_clk_outputs | 18.904m | 7.392ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_clk_rst_inputs | chip_sw_ast_clk_rst_inputs | 1.119h | 24.082ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_sys_clk_jitter | chip_sw_flash_ctrl_ops_jitter_en | 10.411m | 4.594ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 17.753m | 6.445ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.119h | 19.182ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 4.798m | 3.059ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 22.913m | 6.770ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 4.932m | 3.385ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 36.884m | 11.164ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.472m | 3.840ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 11.386m | 4.699ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 5.040m | 2.686ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_ast_usb_clk_calib | chip_sw_usb_ast_clk_calib | 5.007m | 2.384ms | 1 | 1 | 100.00 |
| V2 | chip_sw_sensor_ctrl_ast_alerts | chip_sw_sensor_ctrl_alert | 18.458m | 7.021ms | 5 | 5 | 100.00 |
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 7.667m | 5.635ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sensor_ctrl_ast_status | chip_sw_sensor_ctrl_status | 5.094m | 3.336ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 7.667m | 5.635ms | 3 | 3 | 100.00 |
| V2 | chip_sw_smoketest | chip_sw_flash_scrambling_smoketest | 5.126m | 2.873ms | 3 | 3 | 100.00 |
| chip_sw_aes_smoketest | 5.489m | 3.373ms | 3 | 3 | 100.00 | ||
| chip_sw_aon_timer_smoketest | 5.993m | 3.345ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_smoketest | 4.524m | 3.141ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_smoketest | 4.456m | 2.533ms | 3 | 3 | 100.00 | ||
| chip_sw_entropy_src_smoketest | 9.937m | 3.413ms | 3 | 3 | 100.00 | ||
| chip_sw_gpio_smoketest | 5.731m | 3.004ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_smoketest | 6.266m | 3.311ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_smoketest | 7.277m | 3.551ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_smoketest | 40.367m | 10.072ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 7.571m | 6.003ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_usbdev_smoketest | 8.768m | 6.200ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_plic_smoketest | 5.102m | 2.489ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_timer_smoketest | 4.459m | 2.625ms | 3 | 3 | 100.00 | ||
| chip_sw_rstmgr_smoketest | 3.860m | 2.205ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_smoketest | 4.271m | 2.895ms | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest | 5.851m | 2.945ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_smoketest | chip_sw_otp_ctrl_smoketest | 4.154m | 2.744ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_functests | rom_keymgr_functest | 10.582m | 4.551ms | 3 | 3 | 100.00 |
| V2 | chip_sw_boot | chip_sw_uart_tx_rx_bootstrap | 3.993h | 77.579ms | 3 | 3 | 100.00 |
| V2 | chip_sw_secure_boot | rom_e2e_smoke | 1.431h | 14.730ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_raw_unlock | rom_raw_unlock | 5.348m | 5.183ms | 3 | 3 | 100.00 |
| V2 | chip_sw_power_idle_load | chip_sw_power_idle_load | 12.902m | 4.670ms | 3 | 3 | 100.00 |
| V2 | chip_sw_power_sleep_load | chip_sw_power_sleep_load | 9.322m | 10.784ms | 3 | 3 | 100.00 |
| V2 | chip_sw_exit_test_unlocked_bootstrap | chip_sw_exit_test_unlocked_bootstrap | 3.142h | 57.269ms | 3 | 3 | 100.00 |
| V2 | chip_sw_inject_scramble_seed | chip_sw_inject_scramble_seed | 3.480h | 63.418ms | 3 | 3 | 100.00 |
| V2 | tl_d_oob_addr_access | chip_tl_errors | 0 | 30 | 0.00 | ||
| V2 | tl_d_illegal_access | chip_tl_errors | 0 | 30 | 0.00 | ||
| V2 | tl_d_outstanding_access | chip_csr_aliasing | 0 | 5 | 0.00 | ||
| chip_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| chip_csr_hw_reset | 0 | 5 | 0.00 | ||||
| chip_csr_rw | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | chip_csr_aliasing | 0 | 5 | 0.00 | ||
| chip_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| chip_csr_hw_reset | 0 | 5 | 0.00 | ||||
| chip_csr_rw | 0 | 20 | 0.00 | ||||
| V2 | xbar_base_random_sequence | xbar_random | 0 | 100 | 0.00 | ||
| V2 | xbar_random_delay | xbar_smoke_zero_delays | 0 | 100 | 0.00 | ||
| xbar_smoke_large_delays | 0 | 100 | 0.00 | ||||
| xbar_smoke_slow_rsp | 0 | 100 | 0.00 | ||||
| xbar_random_zero_delays | 0 | 100 | 0.00 | ||||
| xbar_random_large_delays | 0 | 100 | 0.00 | ||||
| xbar_random_slow_rsp | 0 | 100 | 0.00 | ||||
| V2 | xbar_unmapped_address | xbar_unmapped_addr | 0 | 100 | 0.00 | ||
| xbar_error_and_unmapped_addr | 0 | 100 | 0.00 | ||||
| V2 | xbar_error_cases | xbar_error_random | 0 | 100 | 0.00 | ||
| xbar_error_and_unmapped_addr | 0 | 100 | 0.00 | ||||
| V2 | xbar_all_access_same_device | xbar_access_same_device | 0 | 100 | 0.00 | ||
| xbar_access_same_device_slow_rsp | 0 | 100 | 0.00 | ||||
| V2 | xbar_all_hosts_use_same_source_id | xbar_same_source | 0 | 100 | 0.00 | ||
| V2 | xbar_stress_all | xbar_stress_all | 0 | 100 | 0.00 | ||
| xbar_stress_all_with_error | 0 | 100 | 0.00 | ||||
| V2 | xbar_stress_with_reset | xbar_stress_all_with_rand_reset | 0 | 100 | 0.00 | ||
| xbar_stress_all_with_reset_error | 0 | 100 | 0.00 | ||||
| V2 | rom_e2e_smoke | rom_e2e_smoke | 1.431h | 14.730ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_output | rom_e2e_shutdown_output | 1.171h | 31.317ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_exception_c | rom_e2e_shutdown_exception_c | 1.046h | 14.857ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_boot_policy_valid | rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 48.463m | 10.999ms | 1 | 1 | 100.00 |
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 1.416h | 15.265ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 1.098h | 15.180ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 1.144h | 15.108ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 57.723m | 14.602ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 57.905m | 11.511ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 1.349h | 15.860ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 1.067h | 15.178ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 1.090h | 15.069ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 1.017h | 15.440ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 1.401h | 17.938ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 1.692h | 24.000ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 1.545h | 23.765ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 2.038h | 24.356ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 1.664h | 23.870ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_sigverify_always | rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 1.353h | 17.567ms | 1 | 1 | 100.00 |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 1.545h | 22.916ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 1.666h | 23.827ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 1.570h | 23.118ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 1.462h | 22.589ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 50.432m | 10.758ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 1.162h | 14.812ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 1.137h | 14.851ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 1.096h | 14.280ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 1.002h | 14.311ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 57.676m | 10.523ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 1.128h | 14.816ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 1.155h | 15.387ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 1.042h | 14.520ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 56.348m | 14.410ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_asm_init | rom_e2e_asm_init_test_unlocked0 | 58.510m | 10.750ms | 3 | 3 | 100.00 |
| rom_e2e_asm_init_dev | 1.174h | 15.306ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_prod | 1.090h | 15.834ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_prod_end | 1.200h | 15.701ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_rma | 1.160h | 15.039ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_keymgr_init | rom_e2e_keymgr_init_rom_ext_meas | 1.131h | 14.659ms | 3 | 3 | 100.00 |
| rom_e2e_keymgr_init_rom_ext_no_meas | 1.070h | 15.536ms | 3 | 3 | 100.00 | ||
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 1.098h | 15.272ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_static_critical | rom_e2e_static_critical | 1.216h | 17.565ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_enc | chip_sw_aes_enc | 5.976m | 3.178ms | 3 | 3 | 100.00 |
| chip_sw_aes_enc_jitter_en | 4.798m | 3.059ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_aes_multi_block | chip_sw_aes_multi_block | 0 | 0 | -- | ||
| V2 | chip_sw_aes_interrupt_encryption | chip_sw_aes_interrupt_encryption | 0 | 0 | -- | ||
| V2 | chip_sw_aes_entropy | chip_sw_aes_entropy | 4.645m | 3.059ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_prng_reseed | chip_sw_aes_prng_reseed | 0 | 0 | -- | ||
| V2 | chip_sw_aes_force_prng_reseed | chip_sw_aes_force_prng_reseed | 0 | 0 | -- | ||
| V2 | chip_sw_aes_idle | chip_sw_aes_idle | 4.923m | 2.612ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_sideload | chip_sw_keymgr_sideload_aes | 39.442m | 12.120ms | 2 | 3 | 66.67 |
| V2 | chip_sw_adc_ctrl_debug_cable_irq | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 11.271m | 19.379ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 11.271m | 19.379ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wakeup_irq | chip_sw_aon_timer_irq | 7.158m | 4.303ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wakeup | chip_sw_pwrmgr_smoketest | 7.571m | 6.003ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bark_irq | chip_sw_aon_timer_irq | 7.158m | 4.303ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 11.832m | 7.770ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 11.832m | 7.770ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_sleep_pause | chip_sw_aon_timer_sleep_wdog_sleep_pause | 8.758m | 6.790ms | 5 | 5 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_lc_escalate | chip_sw_aon_timer_wdog_lc_escalate | 12.207m | 4.445ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_idle_trans | chip_sw_otbn_randomness | 16.310m | 5.534ms | 3 | 3 | 100.00 |
| chip_sw_aes_idle | 4.923m | 2.612ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_idle | 5.867m | 3.240ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_idle | 3.972m | 2.331ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_trans | chip_sw_clkmgr_off_aes_trans | 8.937m | 4.776ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_off_hmac_trans | 11.524m | 4.716ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_kmac_trans | 10.514m | 4.581ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_otbn_trans | 10.563m | 4.584ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_peri | chip_sw_clkmgr_off_peri | 26.107m | 13.921ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_div | chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 11.900m | 4.273ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 10.150m | 4.473ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 12.124m | 3.500ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 10.578m | 4.697ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 11.721m | 3.754ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 14.460m | 4.872ms | 3 | 3 | 100.00 | ||
| chip_sw_ast_clk_outputs | 18.904m | 7.392ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_external_clk_src_for_lc | chip_sw_clkmgr_external_clk_src_for_lc | 14.857m | 11.291ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_external_clk_src_for_sw | chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 12.124m | 3.500ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 10.578m | 4.697ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_jitter | chip_sw_flash_ctrl_ops_jitter_en | 10.411m | 4.594ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 17.753m | 6.445ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.119h | 19.182ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 4.798m | 3.059ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 22.913m | 6.770ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 4.932m | 3.385ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 36.884m | 11.164ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.472m | 3.840ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 11.386m | 4.699ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 5.040m | 2.686ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_extended_range | chip_sw_clkmgr_jitter_reduced_freq | 4.286m | 2.302ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en_reduced_freq | 12.247m | 5.413ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_ctrl_access_jitter_en_reduced_freq | 21.682m | 7.138ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 1.136h | 25.085ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en_reduced_freq | 5.632m | 3.310ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en_reduced_freq | 5.144m | 3.011ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en_reduced_freq | 27.074m | 9.032ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 6.059m | 3.146ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 10.748m | 5.472ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_init_reduced_freq | 36.644m | 22.035ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_edn_concurrency_reduced_freq | 4.662h | 120.931ms | 2 | 3 | 66.67 | ||
| V2 | chip_sw_clkmgr_deep_sleep_frequency | chip_sw_ast_clk_outputs | 18.904m | 7.392ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_sleep_frequency | chip_sw_clkmgr_sleep_frequency | 11.726m | 4.724ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_reset_frequency | chip_sw_clkmgr_reset_frequency | 7.228m | 3.866ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_escalation_reset | chip_sw_all_escalation_resets | 14.335m | 6.534ms | 98 | 100 | 98.00 |
| V2 | chip_sw_clkmgr_alert_handler_clock_enables | chip_sw_alert_handler_lpg_clkoff | 35.476m | 9.266ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_edn_cmd | chip_sw_entropy_src_csrng | 28.028m | 6.668ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_fuse_en_sw_app_read | chip_sw_csrng_fuse_en_sw_app_read_test | 10.911m | 4.261ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_lc_hw_debug_en | chip_sw_csrng_lc_hw_debug_en_test | 13.756m | 6.232ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_known_answer_tests | chip_sw_csrng_kat_test | 4.655m | 3.343ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 20.515m | 9.229ms | 3 | 3 | 100.00 |
| chip_sw_sysrst_ctrl_reset | 28.251m | 21.686ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sysrst_ctrl_inputs | chip_sw_sysrst_ctrl_inputs | 5.845m | 3.150ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_outputs | chip_sw_sysrst_ctrl_outputs | 7.282m | 3.872ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_in_irq | chip_sw_sysrst_ctrl_in_irq | 12.497m | 4.637ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_wakeup | chip_sw_sysrst_ctrl_reset | 28.251m | 21.686ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_reset | chip_sw_sysrst_ctrl_reset | 28.251m | 21.686ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ec_rst_l | chip_sw_sysrst_ctrl_ec_rst_l | 1.063h | 20.686ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_flash_wp_l | chip_sw_sysrst_ctrl_ec_rst_l | 1.063h | 20.686ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ulp_z3_wakeup | chip_sw_sysrst_ctrl_ulp_z3_wakeup | 8.568m | 6.665ms | 3 | 3 | 100.00 |
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 11.271m | 19.379ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_edn_entropy_reqs | chip_sw_csrng_edn_concurrency | 2.213h | 39.047ms | 10 | 10 | 100.00 |
| chip_sw_entropy_src_ast_rng_req | 4.958m | 3.011ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs | 27.026m | 6.834ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_entropy_src_ast_rng_req | chip_sw_entropy_src_ast_rng_req | 4.958m | 3.011ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_csrng | chip_sw_entropy_src_csrng | 28.028m | 6.668ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fuse_en_fw_read | chip_sw_entropy_src_fuse_en_fw_read_test | 0 | 0 | -- | ||
| V2 | chip_sw_entropy_src_known_answer_tests | chip_sw_entropy_src_kat_test | 4.504m | 2.882ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fw_observe_many_contiguous | chip_sw_entropy_src_fw_observe_many_contiguous | 0 | 0 | -- | ||
| V2 | chip_sw_entropy_src_fw_extract_and_insert | chip_sw_entropy_src_fw_extract_and_insert | 0 | 0 | -- | ||
| V2 | chip_sw_flash_init | chip_sw_flash_init | 42.150m | 23.243ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_host_access | chip_sw_flash_ctrl_access | 18.192m | 5.686ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 17.753m | 6.445ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_ctrl_ops | chip_sw_flash_ctrl_ops | 10.992m | 3.557ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en | 10.411m | 4.594ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_rma_unlocked | chip_sw_flash_rma_unlocked | 1.474h | 44.770ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_scramble | chip_sw_flash_init | 42.150m | 23.243ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_idle_low_power | chip_sw_flash_ctrl_idle_low_power | 7.675m | 2.923ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_keymgr_seeds | chip_sw_keymgr_key_derivation | 25.564m | 8.410ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_creator_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 8.961m | 4.330ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_creator_seed_wipe_on_rma | chip_sw_flash_rma_unlocked | 1.474h | 44.770ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_owner_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 8.961m | 4.330ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 8.961m | 4.330ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_wr_en | chip_sw_flash_ctrl_lc_rw_en | 8.961m | 4.330ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_seed_hw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 8.961m | 4.330ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_escalate_en | chip_sw_all_escalation_resets | 14.335m | 6.534ms | 98 | 100 | 98.00 |
| V2 | chip_sw_flash_prim_tl_access | chip_prim_tl_access | 0 | 3 | 0.00 | ||
| V2 | chip_sw_flash_ctrl_clock_freqs | chip_sw_flash_ctrl_clock_freqs | 21.852m | 5.797ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_escalation_reset | chip_sw_flash_crash_alert | 11.976m | 5.575ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_write_clear | chip_sw_flash_crash_alert | 11.976m | 5.575ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_enc | chip_sw_hmac_enc | 5.575m | 3.274ms | 3 | 3 | 100.00 |
| chip_sw_hmac_enc_jitter_en | 4.932m | 3.385ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_hmac_idle | chip_sw_hmac_enc_idle | 5.867m | 3.240ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_all_configurations | chip_sw_hmac_oneshot | 5.662m | 3.595ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_multistream_mode | chip_sw_hmac_multistream | 30.120m | 7.779ms | 3 | 3 | 100.00 |
| V2 | chip_sw_i2c_host_tx_rx | chip_sw_i2c_host_tx_rx | 14.529m | 5.151ms | 3 | 3 | 100.00 |
| chip_sw_i2c_host_tx_rx_idx1 | 14.582m | 5.806ms | 3 | 3 | 100.00 | ||
| chip_sw_i2c_host_tx_rx_idx2 | 16.823m | 5.542ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_i2c_device_tx_rx | chip_sw_i2c_device_tx_rx | 10.888m | 4.138ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_key_derivation | chip_sw_keymgr_key_derivation | 25.564m | 8.410ms | 3 | 3 | 100.00 |
| chip_sw_keymgr_key_derivation_jitter_en | 36.884m | 11.164ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_keymgr_sideload_kmac | chip_sw_keymgr_sideload_kmac | 43.110m | 12.838ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_aes | chip_sw_keymgr_sideload_aes | 39.442m | 12.120ms | 2 | 3 | 66.67 |
| V2 | chip_sw_keymgr_sideload_otbn | chip_sw_keymgr_sideload_otbn | 1.078h | 15.604ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_enc | chip_sw_kmac_mode_cshake | 4.566m | 2.518ms | 3 | 3 | 100.00 |
| chip_sw_kmac_mode_kmac | 6.274m | 2.858ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 5.472m | 3.840ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_kmac_app_keymgr | chip_sw_keymgr_key_derivation | 25.564m | 8.410ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_app_lc | chip_sw_lc_ctrl_transition | 19.536m | 12.796ms | 15 | 15 | 100.00 |
| V2 | chip_sw_kmac_app_rom | chip_sw_kmac_app_rom | 4.283m | 2.383ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_entropy | chip_sw_kmac_entropy | 4.777m | 3.566ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_idle | chip_sw_kmac_idle | 3.972m | 2.331ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_alert_handler_escalation | chip_sw_alert_handler_escalation | 10.230m | 5.464ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_jtag_access | chip_tap_straps_dev | 21.100m | 12.913ms | 5 | 5 | 100.00 |
| chip_tap_straps_rma | 1.405h | 60.000ms | 4 | 5 | 80.00 | ||
| chip_tap_straps_prod | 35.643m | 17.468ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_otp_hw_cfg0 | chip_sw_lc_ctrl_otp_hw_cfg0 | 4.954m | 3.758ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_init | chip_sw_lc_ctrl_transition | 19.536m | 12.796ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_transitions | chip_sw_lc_ctrl_transition | 19.536m | 12.796ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_kmac_req | chip_sw_lc_ctrl_transition | 19.536m | 12.796ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_key_div | chip_sw_keymgr_key_derivation_prod | 35.766m | 9.216ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_broadcast | chip_sw_flash_ctrl_lc_rw_en | 8.961m | 4.330ms | 3 | 3 | 100.00 |
| chip_sw_flash_rma_unlocked | 1.474h | 44.770ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 14.128m | 3.612ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_dev | 25.346m | 8.603ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 21.584m | 6.174ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 25.757m | 7.365ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 19.536m | 12.796ms | 15 | 15 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 25.564m | 8.410ms | 3 | 3 | 100.00 | ||
| chip_sw_rom_ctrl_integrity_check | 11.790m | 8.308ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_execution_main | 15.739m | 8.838ms | 3 | 3 | 100.00 | ||
| chip_prim_tl_access | 0 | 3 | 0.00 | ||||
| chip_sw_clkmgr_external_clk_src_for_lc | 14.857m | 11.291ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 11.900m | 4.273ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 10.150m | 4.473ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 12.124m | 3.500ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 10.578m | 4.697ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 11.721m | 3.754ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 14.460m | 4.872ms | 3 | 3 | 100.00 | ||
| chip_tap_straps_dev | 21.100m | 12.913ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_rma | 1.405h | 60.000ms | 4 | 5 | 80.00 | ||
| chip_tap_straps_prod | 35.643m | 17.468ms | 5 | 5 | 100.00 | ||
| chip_rv_dm_lc_disabled | 0 | 3 | 0.00 | ||||
| V2 | chip_lc_scrap | chip_sw_lc_ctrl_rma_to_scrap | 4.109m | 3.748ms | 1 | 1 | 100.00 |
| chip_sw_lc_ctrl_raw_to_scrap | 2.245m | 2.684ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_test_locked0_to_scrap | 2.466m | 3.614ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_rand_to_scrap | 4.113m | 3.222ms | 3 | 3 | 100.00 | ||
| V2 | chip_lc_test_locked | chip_sw_lc_walkthrough_testunlocks | 47.976m | 36.646ms | 3 | 3 | 100.00 |
| chip_rv_dm_lc_disabled | 0 | 3 | 0.00 | ||||
| V2 | chip_sw_lc_walkthrough | chip_sw_lc_walkthrough_dev | 1.804h | 50.961ms | 3 | 3 | 100.00 |
| chip_sw_lc_walkthrough_prod | 1.673h | 47.968ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_prodend | 18.452m | 7.943ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_rma | 1.519h | 44.875ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_testunlocks | 47.976m | 36.646ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_volatile_raw_unlock | chip_sw_lc_ctrl_volatile_raw_unlock | 2.054m | 2.487ms | 3 | 3 | 100.00 |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 2.032m | 2.836ms | 3 | 3 | 100.00 | ||
| rom_volatile_raw_unlock | 1.858m | 2.259ms | 3 | 3 | 100.00 | ||
| V2 | chip_otp_ctrl_init | chip_sw_lc_ctrl_transition | 19.536m | 12.796ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_keys | chip_sw_flash_init | 42.150m | 23.243ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 9.185m | 3.588ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 25.564m | 8.410ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 11.894m | 5.808ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 5.128m | 3.222ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_entropy | chip_sw_flash_init | 42.150m | 23.243ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 9.185m | 3.588ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 25.564m | 8.410ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access | 11.894m | 5.808ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 5.128m | 3.222ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_program | chip_sw_lc_ctrl_transition | 19.536m | 12.796ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_program_error | chip_sw_lc_ctrl_program_error | 8.475m | 4.337ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_hw_cfg0 | chip_sw_lc_ctrl_otp_hw_cfg0 | 4.954m | 3.758ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_lc_signals | chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 14.128m | 3.612ms | 3 | 3 | 100.00 |
| chip_sw_otp_ctrl_lc_signals_dev | 25.346m | 8.603ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 21.584m | 6.174ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 25.757m | 7.365ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 19.536m | 12.796ms | 15 | 15 | 100.00 | ||
| chip_prim_tl_access | 0 | 3 | 0.00 | ||||
| V2 | chip_sw_otp_prim_tl_access | chip_prim_tl_access | 0 | 3 | 0.00 | ||
| V2 | chip_sw_otp_ctrl_dai_lock | chip_sw_otp_ctrl_dai_lock | 1.536h | 28.510ms | 1 | 1 | 100.00 |
| V2 | chip_sw_pwrmgr_external_full_reset | chip_sw_pwrmgr_full_aon_reset | 12.988m | 7.621ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_wake_ups | chip_sw_pwrmgr_random_sleep_all_wake_ups | 31.900m | 25.060ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_all_wake_ups | chip_sw_pwrmgr_normal_sleep_all_wake_ups | 7.471m | 7.665ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_por_reset | chip_sw_pwrmgr_deep_sleep_por_reset | 13.790m | 7.868ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_por_reset | chip_sw_pwrmgr_normal_sleep_por_reset | 13.565m | 6.136ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_wake_ups | chip_sw_pwrmgr_deep_sleep_all_wake_ups | 30.671m | 22.534ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 25.178m | 13.517ms | 3 | 3 | 100.00 |
| chip_sw_aon_timer_wdog_bite_reset | 11.832m | 7.770ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 20.937m | 12.208ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_wdog_reset | chip_sw_pwrmgr_wdog_reset | 11.357m | 4.630ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_aon_power_glitch_reset | chip_sw_pwrmgr_full_aon_reset | 12.988m | 7.621ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_main_power_glitch_reset | chip_sw_pwrmgr_main_power_glitch_reset | 7.239m | 4.877ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_power_glitch_reset | chip_sw_pwrmgr_random_sleep_power_glitch_reset | 1.126h | 38.891ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 10.184m | 8.410ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_power_glitch_reset | chip_sw_pwrmgr_sleep_power_glitch_reset | 10.469m | 5.513ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_reset_reqs | chip_sw_pwrmgr_random_sleep_all_reset_reqs | 50.356m | 28.895ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 20.515m | 9.229ms | 3 | 3 | 100.00 |
| chip_sw_pwrmgr_all_reset_reqs | 27.939m | 10.396ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_pwrmgr_b2b_sleep_reset_req | chip_sw_pwrmgr_b2b_sleep_reset_req | 42.145m | 26.937ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_disabled | chip_sw_pwrmgr_sleep_disabled | 4.852m | 2.725ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_escalation_reset | chip_sw_all_escalation_resets | 14.335m | 6.534ms | 98 | 100 | 98.00 |
| V2 | chip_sw_rom_access | chip_sw_rom_ctrl_integrity_check | 11.790m | 8.308ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_ctrl_integrity_check | chip_sw_rom_ctrl_integrity_check | 11.790m | 8.308ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_non_sys_reset_info | chip_sw_pwrmgr_all_reset_reqs | 27.939m | 10.396ms | 3 | 3 | 100.00 |
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 50.356m | 28.895ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_wdog_reset | 11.357m | 4.630ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 7.571m | 6.003ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_rstmgr_sys_reset_info | chip_rv_dm_ndm_reset_req | 8.009m | 3.826ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_cpu_info | chip_sw_rstmgr_cpu_info | 10.980m | 5.775ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_req_reset | chip_sw_rstmgr_sw_req | 7.972m | 4.434ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_alert_info | chip_sw_rstmgr_alert_info | 40.206m | 16.492ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_rst | chip_sw_rstmgr_sw_rst | 5.882m | 3.083ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_escalation_reset | chip_sw_all_escalation_resets | 14.335m | 6.534ms | 98 | 100 | 98.00 |
| V2 | chip_sw_rstmgr_alert_handler_reset_enables | chip_sw_alert_handler_lpg_reset_toggle | 34.765m | 8.982ms | 3 | 3 | 100.00 |
| V2 | chip_sw_plic_all_irqs | chip_plic_all_irqs_0 | 22.165m | 6.156ms | 3 | 3 | 100.00 |
| chip_plic_all_irqs_10 | 11.370m | 4.735ms | 3 | 3 | 100.00 | ||
| chip_plic_all_irqs_20 | 14.350m | 4.174ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_plic_sw_irq | chip_sw_plic_sw_irq | 5.687m | 3.794ms | 3 | 3 | 100.00 |
| V2 | chip_sw_timer | chip_sw_rv_timer_irq | 4.676m | 2.946ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_flash_mode | rom_e2e_smoke | 1.431h | 14.730ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through | chip_sw_spi_device_pass_through | 14.966m | 7.201ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through_collision | chip_sw_spi_device_pass_through_collision | 12.452m | 4.738ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_tpm | chip_sw_spi_device_tpm | 8.752m | 4.209ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_host_tx_rx | chip_sw_spi_host_tx_rx | 5.165m | 2.847ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_scrambled_access | chip_sw_sram_ctrl_scrambled_access | 11.894m | 5.808ms | 3 | 3 | 100.00 |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 11.386m | 4.699ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sleep_sram_ret_contents | chip_sw_sleep_sram_ret_contents_no_scramble | 13.352m | 7.714ms | 3 | 3 | 100.00 |
| chip_sw_sleep_sram_ret_contents_scramble | 14.919m | 9.195ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sram_execution | chip_sw_sram_ctrl_execution_main | 15.739m | 8.838ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_lc_escalation | chip_sw_all_escalation_resets | 14.335m | 6.534ms | 98 | 100 | 98.00 |
| chip_sw_data_integrity_escalation | 12.957m | 5.790ms | 6 | 6 | 100.00 | ||
| V2 | chip_sw_usbdev_mem | chip_sw_usbdev_mem | 0 | 0 | -- | ||
| V2 | chip_sw_usbdev_vbus | chip_sw_usbdev_vbus | 3.880m | 3.056ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_pullup | chip_sw_usbdev_pullup | 4.825m | 3.024ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_aon_pullup | chip_sw_usbdev_aon_pullup | 6.983m | 3.951ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_sof | chip_sw_usbdev_sof | 0 | 0 | -- | ||
| V2 | chip_sw_usbdev_setup_rx | chip_sw_usbdev_setuprx | 9.642m | 4.253ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_config_host | chip_sw_usbdev_config_host | 31.488m | 8.006ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_pincfg | chip_sw_usbdev_pincfg | 2.108h | 31.683ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_tx_rx | chip_sw_usbdev_dpi | 54.403m | 12.879ms | 1 | 1 | 100.00 |
| V2 | chip_sw_alert_handler_alerts | chip_sw_alert_test | 5.354m | 3.302ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalations | chip_sw_alert_handler_escalation | 10.230m | 5.464ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalation_nmi_reset | chip_sw_alert_handler_escalation_nmi_reset | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_escalation_methods | chip_sw_alert_handler_escalation_methods | 0 | 0 | -- | ||
| V2 | chip_sw_all_escalation_resets | chip_sw_all_escalation_resets | 14.335m | 6.534ms | 98 | 100 | 98.00 |
| V2 | chip_sw_alert_handler_irqs | chip_plic_all_irqs | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_entropy | chip_sw_alert_handler_entropy | 6.602m | 3.894ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_crashdump | chip_sw_rstmgr_alert_info | 40.206m | 16.492ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_timeout | chip_sw_alert_handler_ping_timeout | 10.307m | 5.976ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_alerts | chip_sw_alert_handler_lpg_sleep_mode_alerts | 9.033m | 4.234ms | 88 | 90 | 97.78 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_pings | chip_sw_alert_handler_lpg_sleep_mode_pings | 25.705m | 13.440ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_clock_off | chip_sw_alert_handler_lpg_clkoff | 35.476m | 9.266ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_reset_toggle | chip_sw_alert_handler_lpg_reset_toggle | 34.765m | 8.982ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_ok | chip_sw_alert_handler_ping_ok | 28.358m | 7.948ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_reverse_ping_in_deep_sleep | chip_sw_alert_handler_reverse_ping_in_deep_sleep | 3.693h | 256.307ms | 3 | 3 | 100.00 |
| V2 | chip_jtag_csr_rw | chip_jtag_csr_rw | 24.313m | 13.998ms | 3 | 3 | 100.00 |
| V2 | chip_jtag_mem_access | chip_jtag_mem_access | 26.716m | 13.377ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_ndm_reset_req | chip_rv_dm_ndm_reset_req | 8.009m | 3.826ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 9.029m | 4.893ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_access_after_wakeup | chip_sw_rv_dm_access_after_wakeup | 10.212m | 6.000ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_jtag_tap_sel | chip_tap_straps_rma | 1.405h | 60.000ms | 4 | 5 | 80.00 |
| V2 | chip_rv_dm_lc_disabled | chip_rv_dm_lc_disabled | 0 | 3 | 0.00 | ||
| V2 | chip_rv_dm_jtag | chip_rv_dm_jtag | 0 | 0 | -- | ||
| V2 | chip_rv_dm_dtm | chip_rv_dm_dtm | 0 | 0 | -- | ||
| V2 | chip_rv_dm_control_status | chip_rv_dm_control_status | 0 | 0 | -- | ||
| V2 | TOTAL | 881 | 2644 | 33.32 | |||
| V2S | chip_sw_aes_masking_off | chip_sw_aes_masking_off | 5.706m | 2.745ms | 3 | 3 | 100.00 |
| V2S | TOTAL | 3 | 3 | 100.00 | |||
| V3 | chip_sw_usb_suspend | chip_sw_usb_suspend | 0 | 0 | -- | ||
| V3 | chip_sw_coremark | chip_sw_coremark | 3.855h | 71.394ms | 1 | 1 | 100.00 |
| V3 | chip_sw_power_max_load | chip_sw_power_virus | 25.657m | 5.888ms | 3 | 3 | 100.00 |
| V3 | rom_e2e_debug | rom_e2e_jtag_debug_test_unlocked0 | 34.754m | 10.302ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 39.946m | 10.667ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 41.703m | 10.246ms | 1 | 1 | 100.00 | ||
| V3 | rom_e2e_jtag_inject | rom_e2e_jtag_inject_test_unlocked0 | 33.983m | 24.921ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_inject_dev | 38.347m | 24.635ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_inject_rma | 50.092m | 32.404ms | 1 | 1 | 100.00 | ||
| V3 | rom_bootstrap_rma | rom_bootstrap_rma | 0 | 0 | -- | ||
| V3 | rom_e2e_weak_straps | rom_e2e_weak_straps | 0 | 0 | -- | ||
| V3 | rom_e2e_self_hash | rom_e2e_self_hash | 1.680h | 27.359ms | 3 | 3 | 100.00 |
| V3 | manuf_cp_unlock_raw | manuf_cp_unlock_raw | 0 | 0 | -- | ||
| V3 | manuf_scrap | manuf_scrap | 0 | 0 | -- | ||
| V3 | manuf_cp_yield_test | manuf_cp_yield_test | 0 | 0 | -- | ||
| V3 | manuf_cp_ast_test_execution | manuf_cp_ast_test_execution | 0 | 0 | -- | ||
| V3 | manuf_cp_device_info_flash_wr | manuf_cp_device_info_flash_wr | 0 | 0 | -- | ||
| V3 | manuf_cp_test_lock | manuf_cp_test_lock | 0 | 0 | -- | ||
| V3 | manuf_ft_exit_token | manuf_ft_exit_token | 0 | 0 | -- | ||
| V3 | manuf_ft_sku_individualization_preop | manuf_ft_sku_individualization_preop | 0 | 0 | -- | ||
| V3 | manuf_ft_sku_individualization | manuf_ft_sku_individualization | 0 | 0 | -- | ||
| V3 | manuf_ft_provision_rma_token_and_personalization | manuf_ft_provision_rma_token_and_personalization | 0 | 0 | -- | ||
| V3 | manuf_ft_load_transport_image | manuf_ft_load_transport_image | 0 | 0 | -- | ||
| V3 | manuf_ft_load_certificates | manuf_ft_load_certificates | 0 | 0 | -- | ||
| V3 | manuf_ft_eom | manuf_ft_eom | 0 | 0 | -- | ||
| V3 | manuf_rma_entry | manuf_rma_entry | 0 | 0 | -- | ||
| V3 | manuf_sram_program_crc_functest | manuf_sram_program_crc_functest | 0 | 0 | -- | ||
| V3 | chip_sw_adc_ctrl_normal | chip_sw_adc_ctrl_normal | 0 | 0 | -- | ||
| V3 | chip_sw_adc_ctrl_oneshot | chip_sw_adc_ctrl_oneshot | 0 | 0 | -- | ||
| V3 | chip_sw_clkmgr_jitter_cycle_measurements | chip_sw_clkmgr_jitter_frequency | 9.780m | 4.123ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_boot_mode | chip_sw_edn_boot_mode | 13.192m | 2.798ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_auto_mode | chip_sw_edn_auto_mode | 31.877m | 6.607ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_sw_mode | chip_sw_edn_sw_mode | 29.666m | 8.502ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_kat | chip_sw_edn_kat | 10.800m | 3.877ms | 3 | 3 | 100.00 |
| V3 | chip_sw_entropy_src_bypass_mode_health_tests | chip_sw_entropy_src_bypass_mode_health_tests | 0 | 0 | -- | ||
| V3 | chip_sw_entropy_src_fips_mode_health_tests | chip_sw_entropy_src_fips_mode_health_tests | 0 | 0 | -- | ||
| V3 | chip_sw_entropy_src_validation | chip_sw_entropy_src_validation | 0 | 0 | -- | ||
| V3 | chip_sw_flash_memory_protection | chip_sw_flash_ctrl_mem_protection | 22.054m | 5.677ms | 3 | 3 | 100.00 |
| V3 | chip_sw_hmac_sha2_stress | chip_sw_hmac_sha2_stress | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_stress | chip_sw_hmac_stress | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_endianness | chip_sw_hmac_endianness | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_secure_wipe | chip_sw_hmac_secure_wipe | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_error_conditions | chip_sw_hmac_error_conditions | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_speed | chip_sw_i2c_speed | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_override | chip_sw_i2c_override | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_clockstretching | chip_sw_i2c_clockstretching | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_nack | chip_sw_i2c_nack | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_repeatedstart | chip_sw_i2c_repeatedstart | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_sideload_kmac_error | chip_sw_keymgr_sideload_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_derive_attestation | chip_sw_keymgr_derive_attestation | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_derive_sealing | chip_sw_keymgr_derive_sealing | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_sha3_stress | chip_sw_kmac_sha3_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_shake_stress | chip_sw_kmac_shake_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_cshake_stress | chip_sw_kmac_cshake_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_kmac_stress | chip_sw_kmac_kmac_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_kmac_key_sideload | chip_sw_kmac_kmac_key_sideload | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_endianess | chip_sw_kmac_endianess | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_entropy_stress | chip_sw_kmac_entropy_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_error_conditions | chip_sw_kmac_error_conditions | 0 | 0 | -- | ||
| V3 | chip_sw_lc_ctrl_kmac_error | chip_sw_lc_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_lc_ctrl_debug_access | chip_sw_lc_ctrl_debug_access | 0 | 0 | -- | ||
| V3 | chip_sw_otp_ctrl_vendor_test_csr_access | chip_sw_otp_ctrl_vendor_test_csr_access | 4.617m | 2.686ms | 3 | 3 | 100.00 |
| V3 | chip_sw_otp_ctrl_escalation | chip_sw_otp_ctrl_escalation | 10.496m | 5.471ms | 1 | 1 | 100.00 |
| V3 | otp_ctrl_calibration | otp_ctrl_calibration | 0 | 0 | -- | ||
| V3 | otp_ctrl_partition_access_locked | otp_ctrl_partition_access_locked | 0 | 0 | -- | ||
| V3 | otp_ctrl_check_timeout | otp_ctrl_check_timeout | 0 | 0 | -- | ||
| V3 | chip_sw_sensor_ctrl_deep_sleep_wake_up | chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up | 7.690m | 5.662ms | 3 | 3 | 100.00 |
| V3 | chip_sw_pwrmgr_usb_clk_disabled_when_active | chip_sw_pwrmgr_usb_clk_disabled_when_active | 8.511m | 5.248ms | 3 | 3 | 100.00 |
| V3 | chip_sw_all_resets | chip_sw_pwrmgr_all_reset_reqs | 27.939m | 10.396ms | 3 | 3 | 100.00 |
| V3 | chip_sw_rom_ctrl_kmac_error | chip_sw_rom_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_rom_ctrl_digests | chip_sw_rom_ctrl_digests | 0 | 0 | -- | ||
| V3 | chip_sw_plic_alerts | chip_sw_all_escalation_resets | 14.335m | 6.534ms | 98 | 100 | 98.00 |
| V3 | tick_configuration | chip_sw_rv_timer_systick_test | 0 | 3 | 0.00 | ||
| V3 | counter_wrap | chip_sw_rv_timer_systick_test | 0 | 3 | 0.00 | ||
| V3 | chip_sw_spi_device_pass_through_flash_model | //sw/device/tests:spi_passthru_test | 0 | 0 | -- | ||
| V3 | chip_sw_spi_device_output_when_disabled_or_sleeping | chip_sw_spi_device_pinmux_sleep_retention | 5.561m | 3.484ms | 3 | 3 | 100.00 |
| V3 | chip_sw_spi_host_pass_through | //sw/device/tests:spi_passthru_test | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_configuration | //sw/device/tests:spi_host_config_test | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_events | chip_sw_spi_host_events | 0 | 0 | -- | ||
| V3 | chip_sw_sram_memset | chip_sw_sram_memset | 0 | 0 | -- | ||
| V3 | chip_sw_sram_readback | chip_sw_sram_readback | 0 | 0 | -- | ||
| V3 | chip_sw_sram_subword_access | chip_sw_sram_subword_access | 0 | 0 | -- | ||
| V3 | chip_sw_uart_parity | chip_sw_uart_parity | 0 | 0 | -- | ||
| V3 | chip_sw_uart_line_loopback | chip_sw_uart_line_loopback | 0 | 0 | -- | ||
| V3 | chip_sw_uart_system_loopback | chip_sw_uart_system_loopback | 0 | 0 | -- | ||
| V3 | chip_sw_uart_line_break | chip_sw_uart_line_break | 0 | 0 | -- | ||
| V3 | chip_sw_uart_watermarks | chip_sw_uart_tx_rx | 11.151m | 4.453ms | 5 | 5 | 100.00 |
| V3 | chip_sw_usbdev_stream | chip_sw_usbdev_stream | 1.363h | 18.303ms | 1 | 1 | 100.00 |
| V3 | chip_sw_usbdev_iso | chip_sw_usbdev_iso | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_mixed | chip_sw_usbdev_mixed | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_suspend_resume | chip_sw_usbdev_suspend_resume | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_aon_wake_reset | chip_sw_usbdev_aon_wake_reset | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_aon_wake_disconnect | chip_sw_usbdev_aon_wake_disconnect | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_toggle_restore | chip_sw_usbdev_toggle_restore | 0 | 0 | -- | ||
| V3 | chip_rv_dm_perform_debug | rom_e2e_jtag_debug_test_unlocked0 | 34.754m | 10.302ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 39.946m | 10.667ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 41.703m | 10.246ms | 1 | 1 | 100.00 | ||
| V3 | chip_sw_rv_dm_access_after_hw_reset | chip_sw_rv_dm_access_after_escalation_reset | 10.343m | 4.586ms | 3 | 3 | 100.00 |
| V3 | TOTAL | 48 | 51 | 94.12 | |||
| Unmapped tests | chip_sival_flash_info_access | 5.872m | 3.638ms | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_rst_cnsty_escalation | 14.591m | 6.383ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_ecc_error_vendor_test | 4.843m | 2.815ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq | 1.127h | 17.684ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_rnd | 21.111m | 6.028ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_nmi_irq | 17.763m | 4.867ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_lowpower_cancel | 7.856m | 4.669ms | 1 | 3 | 33.33 | ||
| chip_sw_pwrmgr_sleep_wake_5_bug | 10.447m | 6.554ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_address_translation | 5.029m | 2.969ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_lockstep_glitch | 3.399m | 2.099ms | 1 | 3 | 33.33 | ||
| chip_sw_flash_ctrl_write_clear | 5.927m | 3.209ms | 3 | 3 | 100.00 | ||
| TOTAL | 1026 | 2951 | 34.77 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 11 | 11 | 9 | 81.82 |
| V1 | 18 | 18 | 12 | 66.67 |
| V2 | 285 | 270 | 244 | 85.61 |
| V2S | 1 | 1 | 1 | 100.00 |
| V3 | 90 | 23 | 22 | 24.44 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 89.33 | 90.80 | 80.59 | 90.24 | -- | 92.12 | 97.35 | 84.87 |
launch_task.returncode != *, err: * *:*:* * lswatcher.go:*] Failed to connect to Watcher service in the Envelope (you probably need to import _ "google3/tech/env/go/envelope"): generic::unimplemented: envrpc: no envelope available for service "chubby.googleapis.com" Failure to submit jobs: rpc error: code = Unavailable desc = The service is currently unavailable. has 956 failures:
Test chip_csr_bit_bash has 3 failures.
0.chip_csr_bit_bash.31868228332378168166683500624325506105620890205109429291249752611855436765366
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
2.chip_csr_bit_bash.17692393369133339731156666158865141196752034532043780210639312165586442712803
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_csr_bit_bash/latest/run.log
... and 1 more failures.
Test chip_same_csr_outstanding has 3 failures.
0.chip_same_csr_outstanding.50898983459998129895330437382131551610839009397408106949375584977446710660384
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
2.chip_same_csr_outstanding.41343933930394701923392281521277234628211936822828520933977293050557430743313
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_same_csr_outstanding/latest/run.log
... and 1 more failures.
Test chip_prim_tl_access has 2 failures.
0.chip_prim_tl_access.29052198622470571072047554435906471775432131079711930731209638966911613431081
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_prim_tl_access/latest/run.log
2.chip_prim_tl_access.25092043808741984057314736644406598968223805266952717341123465880435950362091
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_prim_tl_access/latest/run.log
Test xbar_smoke has 8 failures.
0.xbar_smoke.105384686322236206742728629691203823092484917736661481295392862919143780342503
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke/latest/run.log
2.xbar_smoke.73953109009105774953886726487014461612305025258088312238217600964132832004055
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke/latest/run.log
... and 6 more failures.
Test xbar_smoke_large_delays has 8 failures.
0.xbar_smoke_large_delays.66260995769484683575854343610283076878136501380481235924700778371315793449843
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_large_delays/latest/run.log
2.xbar_smoke_large_delays.60757520728991916770863385990012917339880767681266579599763138457801427367888
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_large_delays/latest/run.log
... and 6 more failures.
... and 22 more tests.
Job killed most likely because its dependent job failed. has 955 failures:
Test chip_csr_aliasing has 3 failures.
0.chip_csr_aliasing.89152174822268809265619825802712948242916230176576357338744588347725644493042
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
2.chip_csr_aliasing.87029924129921178865711988856700088620010689895173971022429511951955186120791
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_csr_aliasing/latest/run.log
... and 1 more failures.
Test chip_tl_errors has 8 failures.
0.chip_tl_errors.41418889627971518021273676894064846461072820334797426281764631024721540409060
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log
2.chip_tl_errors.51046467224128184502418225989555406466384612304863708197567382306597606147822
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_tl_errors/latest/run.log
... and 6 more failures.
Test chip_rv_dm_lc_disabled has 2 failures.
0.chip_rv_dm_lc_disabled.40698110273693843203094923452107071003628452730803364677868049959112723625794
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
2.chip_rv_dm_lc_disabled.32591477776367821421172834023096962706140713068427175234735369695159629562910
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_rv_dm_lc_disabled/latest/run.log
Test xbar_smoke_zero_delays has 8 failures.
0.xbar_smoke_zero_delays.68444706645291994223728594237974051263527900855997339194560159346291921381663
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_zero_delays/latest/run.log
2.xbar_smoke_zero_delays.65943183994679096955638640950433309072068204193484382659691560227582795874923
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_zero_delays/latest/run.log
... and 6 more failures.
Test xbar_smoke_slow_rsp has 8 failures.
0.xbar_smoke_slow_rsp.76447316974889054009414266362481108620352198440877563510603670320095017454325
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.xbar_smoke_slow_rsp/latest/run.log
2.xbar_smoke_slow_rsp.94319138524988075308419722867346858268960808997958150406733901860322917276065
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.xbar_smoke_slow_rsp/latest/run.log
... and 6 more failures.
... and 22 more tests.
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
Test chip_sw_rv_timer_systick_test has 3 failures.
0.chip_sw_rv_timer_systick_test.70657438333487941082682107482976150474925620279214808262420966071259030834520
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
Job ID: smart:bc8c1157-9951-4826-84b3-fc999f1b71b8
1.chip_sw_rv_timer_systick_test.52439829825556584460237555355002704657588885942520255104986239221408892998717
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
Job ID: smart:69b698bb-3cb4-4f47-908d-1790d3312799
... and 1 more failures.
Test chip_sw_keymgr_sideload_aes has 1 failures.
0.chip_sw_keymgr_sideload_aes.38109216332559417593863416426072346346672559468813809053858437902018801106812
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_sideload_aes/latest/run.log
Job ID: smart:3e68369b-d820-42b6-937c-38278c0cb5c1
Test chip_sw_csrng_edn_concurrency_reduced_freq has 1 failures.
2.chip_sw_csrng_edn_concurrency_reduced_freq.114647158677331477438138016262258923964907676355856464193640617173652855550602
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_csrng_edn_concurrency_reduced_freq/latest/run.log
Job ID: smart:46552382-f4a5-4d88-9f61-eddbe40c49fd
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:84)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status() has 2 failures:
0.chip_sw_pwrmgr_lowpower_cancel.66533270214910623524753381123142527346760544808105164041605119227136094771172
Line 778, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_lowpower_cancel/latest/run.log
UVM_ERROR @ 3397.952846 us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:84)] CHECK-fail: Timed out after 100 usec (10000 CPU cycles) waiting for !get_wakeup_status()
UVM_INFO @ 3397.952846 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.chip_sw_pwrmgr_lowpower_cancel.108352445792715377234525039952308478337529546261592538609922674822026217671547
Line 779, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_lowpower_cancel/latest/run.log
UVM_ERROR @ 2845.408440 us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:84)] CHECK-fail: Timed out after 100 usec (10000 CPU cycles) waiting for !get_wakeup_status()
UVM_INFO @ 2845.408440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation. has 2 failures:
0.chip_sw_rv_core_ibex_lockstep_glitch.2214058487137535607797005807089542933644073029830616508936725601752371819122
Line 792, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
UVM_FATAL @ 3032.130454 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
UVM_INFO @ 3032.130454 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.chip_sw_rv_core_ibex_lockstep_glitch.88614912340464470463211192081429982189847212715047185950102101704696517963470
Line 773, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_rv_core_ibex_lockstep_glitch/latest/run.log
UVM_FATAL @ 2019.753068 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
UVM_INFO @ 2019.753068 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 2 failures:
28.chip_sw_all_escalation_resets.45290488830292001817260330778039839196825791446147199937542549995655875028544
Line 772, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/28.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 2549.185700 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
UVM_INFO @ 2549.185700 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
31.chip_sw_all_escalation_resets.78982797471877679942600597586267505964476652896906356304716901953494804242499
Line 784, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/31.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 2854.065708 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
UVM_INFO @ 2854.065708 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 2 failures:
47.chip_sw_alert_handler_lpg_sleep_mode_alerts.72044448738057686015976050954152800119349640368672688270870125149703105937554
Line 789, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
UVM_ERROR @ 3517.772880 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=2000371c MTVAL=40600800
UVM_INFO @ 3517.772880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
71.chip_sw_alert_handler_lpg_sleep_mode_alerts.20876940315421009317991197248260754674999109053011377955714353713212808815547
Line 807, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
UVM_ERROR @ 3802.266208 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=2000371c MTVAL=40600800
UVM_INFO @ 3802.266208 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * us hit, indicating a probable testbench issue has 1 failures:
4.chip_tap_straps_rma.40077293265699317338099561050072348601556206600307068753322550725854954691506
Line 5966, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/4.chip_tap_straps_rma/latest/run.log
UVM_FATAL @ 60000.000000 us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 60000.000000 us hit, indicating a probable testbench issue
UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---