Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3731996	1			T76	1212		T77	1445		T78	1747
values[2]	756678	1			T76	360		T78	538		T131	391
values[3]	106680	1			T76	1		T78	6		T131	1
values[4]	55095	1			T78	1		T227	222		T777	9
values[5]	36478	1			T227	152		T777	9		T561	25
values[6]	27094	1			T227	70		T777	9		T561	15
values[7]	22445	1			T227	50		T777	9		T561	3
values[8]	19043	1			T227	46		T777	9		T561	5
values[9]	17043	1			T227	46		T777	9		T561	6
values[10]	15431	1			T227	27		T777	9		T561	5
values[11]	14430	1			T227	33		T777	9		T561	16
values[12]	13415	1			T227	11		T777	9		T561	7
values[13]	12354	1			T227	16		T777	9		T561	1
values[14]	11712	1			T227	11		T777	9		T561	1
values[15]	11361	1			T227	19		T777	9		T561	1
values[16]	11011	1			T227	22		T777	9		T561	1
values[17]	10888	1			T227	16		T777	9		T561	3
values[18]	10623	1			T227	14		T777	9		T561	1
values[19]	9768	1			T227	12		T777	9		T561	2
values[20]	9563	1			T227	11		T777	9		T561	1
values[21]	9263	1			T227	9		T777	9		T561	1
values[22]	9008	1			T227	6		T777	9		T561	1
values[23]	8791	1			T227	6		T777	9		T561	3
values[24]	8452	1			T227	9		T777	9		T561	1
values[25]	7759	1			T227	7		T777	9		T561	3
values[26]	7462	1			T227	16		T777	9		T561	2
values[27]	7227	1			T227	19		T777	10		T561	4
values[28]	7007	1			T227	11		T777	9		T561	1
values[29]	6535	1			T227	14		T777	9		T561	2
values[30]	6299	1			T227	13		T777	9		T561	2
values[31]	6033	1			T227	10		T777	10		T561	1
values[32]	5669	1			T227	6		T777	9		T561	4
values[33]	5272	1			T227	10		T777	9		T561	3
values[34]	4945	1			T227	20		T777	9		T561	1
values[35]	4591	1			T227	21		T777	9		T561	2
values[36]	4142	1			T227	9		T777	9		T561	1
values[37]	3996	1			T227	11		T777	9		T561	2
values[38]	3806	1			T227	15		T777	9		T561	1
values[39]	3664	1			T227	6		T777	9		T561	1
values[40]	3517	1			T227	9		T777	10		T561	2
values[41]	3442	1			T227	5		T777	10		T561	1
values[42]	3452	1			T227	7		T777	9		T561	5
values[43]	3376	1			T227	12		T777	9		T561	3
values[44]	3256	1			T227	8		T777	9		T561	3
values[45]	3167	1			T227	16		T777	9		T561	2
values[46]	3106	1			T227	6		T777	9		T561	4
values[47]	3087	1			T227	6		T777	9		T561	3
values[48]	3033	1			T227	3		T777	9		T561	3
values[49]	3024	1			T227	6		T777	9		T561	1
values[50]	2988	1			T227	7		T777	10		T561	1
values[51]	2809	1			T227	11		T777	9		T561	1
values[52]	2794	1			T227	13		T777	9		T561	1
values[53]	2865	1			T227	18		T777	9		T561	3
values[54]	2761	1			T227	12		T777	9		T561	1
values[55]	2635	1			T227	8		T777	9		T561	1
values[56]	2532	1			T227	6		T777	9		T561	1
values[57]	2475	1			T227	7		T777	9		T561	2
values[58]	2484	1			T227	6		T777	9		T561	3
values[59]	2451	1			T227	3		T777	9		T561	4
values[60]	2512	1			T227	6		T777	9		T561	1
values[61]	2673	1			T227	8		T777	9		T561	4
values[62]	3904	1			T227	17		T777	9		T561	8
values[63]	10484	1			T227	63		T777	9		T561	34
values[64]	232751	1			T227	202		T777	1761		T561	90

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4777592	1			T76	1235		T77	1452		T78	1883
values[2]	808448	1			T76	324		T78	463		T131	431
values[3]	84881	1			T76	8		T78	59		T131	15
values[4]	14836	1			T76	1		T78	1		T227	88
values[5]	5487	1			T227	50		T777	7		T561	14
values[6]	3556	1			T227	33		T777	2		T561	8
values[7]	2769	1			T227	25		T561	8		T421	5
values[8]	2294	1			T227	11		T561	3		T421	5
values[9]	2109	1			T227	4		T561	2		T421	7
values[10]	1830	1			T227	5		T561	3		T421	8
values[11]	1728	1			T227	3		T561	4		T421	5
values[12]	1610	1			T227	3		T561	3		T421	6
values[13]	1422	1			T227	4		T561	1		T421	11
values[14]	1276	1			T227	4		T561	2		T421	5
values[15]	1177	1			T227	3		T561	1		T421	5
values[16]	1125	1			T227	3		T561	1		T421	7
values[17]	1049	1			T227	6		T561	2		T421	5
values[18]	969	1			T227	3		T561	1		T421	6
values[19]	965	1			T227	4		T561	1		T421	8
values[20]	978	1			T227	3		T561	1		T421	6
values[21]	923	1			T227	3		T561	1		T421	6
values[22]	908	1			T227	5		T561	3		T421	5
values[23]	810	1			T227	3		T561	2		T421	6
values[24]	795	1			T227	4		T561	2		T421	6
values[25]	812	1			T227	5		T561	1		T421	8
values[26]	776	1			T227	5		T561	1		T421	5
values[27]	743	1			T227	2		T561	1		T421	5
values[28]	689	1			T227	4		T561	1		T421	4
values[29]	651	1			T227	8		T561	2		T421	7
values[30]	648	1			T227	10		T561	4		T421	14
values[31]	562	1			T227	9		T561	2		T421	6
values[32]	566	1			T227	4		T561	2		T421	5
values[33]	586	1			T227	9		T561	1		T421	5
values[34]	580	1			T227	8		T561	2		T421	9
values[35]	553	1			T227	2		T561	2		T421	5
values[36]	580	1			T227	3		T561	4		T421	6
values[37]	526	1			T227	2		T561	2		T421	5
values[38]	578	1			T227	5		T561	1		T421	5
values[39]	568	1			T227	3		T561	2		T421	5
values[40]	526	1			T227	4		T561	1		T421	5
values[41]	468	1			T227	9		T561	3		T421	6
values[42]	488	1			T227	4		T561	1		T421	6
values[43]	460	1			T227	4		T561	5		T421	5
values[44]	484	1			T227	5		T561	7		T421	5
values[45]	470	1			T227	3		T561	3		T421	9
values[46]	450	1			T227	4		T561	2		T421	5
values[47]	456	1			T227	5		T561	2		T421	6
values[48]	452	1			T227	9		T561	2		T421	6
values[49]	419	1			T227	6		T561	1		T421	6
values[50]	415	1			T227	5		T561	1		T421	6
values[51]	424	1			T227	10		T561	2		T421	5
values[52]	437	1			T227	5		T561	2		T421	6
values[53]	418	1			T227	6		T561	2		T421	5
values[54]	421	1			T227	1		T561	5		T421	6
values[55]	381	1			T227	1		T561	7		T421	6
values[56]	388	1			T227	2		T561	2		T421	6
values[57]	364	1			T227	1		T561	2		T421	5
values[58]	389	1			T227	1		T561	2		T421	5
values[59]	379	1			T227	1		T561	1		T421	4
values[60]	392	1			T227	2		T561	1		T421	7
values[61]	421	1			T227	1		T561	1		T421	6
values[62]	714	1			T227	7		T561	5		T421	6
values[63]	2735	1			T227	42		T561	30		T421	14
values[64]	27841	1			T227	86		T561	123		T421	287

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	545421	1			T76	10		T77	1438		T78	25
values[2]	2640579	1			T76	1199		T78	754		T131	1480
values[3]	1224173	1			T76	297		T78	1500		T131	449
values[4]	146244	1			T76	3		T78	62		T227	827
values[5]	75590	1			T227	409		T558	1		T777	9
values[6]	49037	1			T227	201		T777	9		T561	30
values[7]	35070	1			T227	121		T777	9		T561	15
values[8]	28108	1			T227	114		T777	9		T561	5
values[9]	23367	1			T227	113		T777	9		T561	1
values[10]	20145	1			T227	77		T777	9		T561	2
values[11]	18190	1			T227	45		T777	9		T561	1
values[12]	16408	1			T227	27		T777	9		T561	1
values[13]	15419	1			T227	23		T777	9		T561	1
values[14]	14914	1			T227	14		T777	9		T561	1
values[15]	14115	1			T227	16		T777	9		T561	1
values[16]	13440	1			T227	15		T777	9		T561	1
values[17]	12912	1			T227	15		T777	9		T561	2
values[18]	12394	1			T227	14		T777	9		T561	1
values[19]	11482	1			T227	19		T777	9		T561	1
values[20]	11242	1			T227	16		T777	9		T561	1
values[21]	10658	1			T227	9		T777	9		T561	1
values[22]	10194	1			T227	6		T777	9		T561	2
values[23]	9966	1			T227	9		T777	9		T561	4
values[24]	9559	1			T227	15		T777	9		T561	1
values[25]	9333	1			T227	25		T777	9		T561	2
values[26]	8867	1			T227	22		T777	9		T561	2
values[27]	8307	1			T227	15		T777	9		T561	2
values[28]	8053	1			T227	19		T777	9		T561	4
values[29]	7579	1			T227	13		T777	9		T561	3
values[30]	7014	1			T227	13		T777	9		T561	1
values[31]	6414	1			T227	12		T777	9		T561	4
values[32]	5826	1			T227	17		T777	9		T561	3
values[33]	5641	1			T227	19		T777	9		T561	1
values[34]	5296	1			T227	14		T777	9		T561	1
values[35]	4976	1			T227	12		T777	9		T561	4
values[36]	4710	1			T227	20		T777	9		T561	1
values[37]	4515	1			T227	18		T777	9		T561	1
values[38]	4259	1			T227	28		T777	9		T561	2
values[39]	3961	1			T227	14		T777	9		T561	1
values[40]	3772	1			T227	26		T777	9		T561	1
values[41]	3683	1			T227	17		T777	9		T561	1
values[42]	3677	1			T227	16		T777	9		T561	1
values[43]	3711	1			T227	21		T777	9		T561	3
values[44]	3695	1			T227	9		T777	9		T561	1
values[45]	3563	1			T227	5		T777	9		T561	1
values[46]	3462	1			T227	7		T777	9		T561	2
values[47]	3350	1			T227	4		T777	9		T561	1
values[48]	3283	1			T227	5		T777	9		T561	3
values[49]	3258	1			T227	6		T777	10		T561	3
values[50]	3243	1			T227	5		T777	11		T561	2
values[51]	3186	1			T227	10		T777	9		T561	1
values[52]	3129	1			T227	9		T777	9		T561	1
values[53]	3093	1			T227	11		T777	9		T561	1
values[54]	3035	1			T227	7		T777	9		T561	1
values[55]	2881	1			T227	7		T777	10		T561	5
values[56]	2836	1			T227	4		T777	9		T561	2
values[57]	2803	1			T227	5		T777	10		T561	2
values[58]	2827	1			T227	8		T777	9		T561	1
values[59]	2769	1			T227	5		T777	9		T561	2
values[60]	2865	1			T227	9		T777	9		T561	9
values[61]	2893	1			T227	13		T777	9		T561	6
values[62]	3577	1			T227	12		T777	10		T561	5
values[63]	9120	1			T227	35		T777	9		T561	20
values[64]	226499	1			T227	135		T777	1627		T561	123