Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1967860	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

36949980

1

T1

6857

T2

97221

T3

7092

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	27304146	1			T1	2944		T2	53557		T3	3277
values[0x0]	10137369	1			T1	3913		T2	43664		T3	3815
values[0x1]	1476325	1			T1	275		T2	5564		T3	519

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	644843	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

38272997

1

T1

7132

T2

102785

T3

7611

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18229663	1			T1	3566		T2	51396		T3	3806
valid_sources[0x01]	18229073	1			T1	3566		T2	51389		T3	3805
valid_sources[0x02]	40040	1			T80	1		T741	617		T148	129
valid_sources[0x03]	40576	1			T46	1		T80	1		T147	1
valid_sources[0x04]	40414	1			T46	1		T741	636		T148	123
valid_sources[0x05]	39756	1			T80	1		T741	664		T148	122
valid_sources[0x06]	39309	1			T80	1		T147	1		T741	655
valid_sources[0x07]	41347	1			T46	1		T80	1		T741	708
valid_sources[0x08]	39248	1			T46	1		T741	641		T148	113
valid_sources[0x09]	39611	1			T46	1		T80	1		T741	642
valid_sources[0x0a]	39826	1			T80	1		T741	634		T148	117
valid_sources[0x0b]	40071	1			T46	1		T741	678		T148	125
valid_sources[0x0c]	40193	1			T80	2		T741	652		T148	126
valid_sources[0x0d]	39617	1			T46	2		T741	659		T148	129
valid_sources[0x0e]	39195	1			T80	2		T741	634		T148	115
valid_sources[0x0f]	38059	1			T46	1		T80	1		T741	663
valid_sources[0x10]	39635	1			T46	2		T741	698		T148	103
valid_sources[0x11]	39542	1			T46	2		T80	1		T147	5
valid_sources[0x12]	40669	1			T741	630		T148	115		T149	255
valid_sources[0x13]	39434	1			T741	704		T148	120		T149	253
valid_sources[0x14]	40858	1			T80	1		T741	639		T148	112
valid_sources[0x15]	39034	1			T741	656		T148	132		T149	235
valid_sources[0x16]	39112	1			T46	1		T147	4		T741	608
valid_sources[0x17]	39349	1			T80	1		T204	39		T147	1
valid_sources[0x18]	38172	1			T741	618		T148	106		T149	246
valid_sources[0x19]	38972	1			T46	1		T147	3		T741	701
valid_sources[0x1a]	39298	1			T741	667		T148	136		T149	234
valid_sources[0x1b]	39755	1			T46	1		T741	611		T148	130
valid_sources[0x1c]	38743	1			T46	2		T741	640		T148	147
valid_sources[0x1d]	38611	1			T741	602		T148	137		T149	266
valid_sources[0x1e]	39969	1			T46	1		T147	2		T741	646
valid_sources[0x1f]	38888	1			T147	4		T205	39		T741	757
valid_sources[0x20]	39103	1			T80	1		T81	23		T741	585

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26579719

1

T1

2944

T2

53557

T3

3277

values[0x0]

all_enables

biggest_size

10083683

1

T1

3913

T2

43664

T3

3815

values[0x1]

all_enables

biggest_size

286578

1

T46

19

T80

21

T81

19

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3000766	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

475290

1

T76

203

T77

188

T78

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1175922	1			T76	517		T77	495		T78	45
values[0x0]	1125349	1			T76	497		T77	476		T78	11
values[0x1]	1174785	1			T76	559		T77	474		T78	59

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2324134	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1151922

1

T76

532

T77

467

T78

49

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	53478	1			T76	23		T77	15		T78	1
valid_sources[0x01]	53639	1			T76	24		T77	32		T227	318
valid_sources[0x02]	54113	1			T76	14		T77	43		T227	307
valid_sources[0x03]	54631	1			T76	3		T77	11		T78	1
valid_sources[0x04]	53833	1			T77	11		T78	2		T131	1
valid_sources[0x05]	54469	1			T76	16		T77	14		T227	368
valid_sources[0x06]	52959	1			T76	10		T77	16		T78	3
valid_sources[0x07]	53528	1			T76	27		T131	1		T227	290
valid_sources[0x08]	55452	1			T76	7		T77	47		T78	2
valid_sources[0x09]	54189	1			T76	18		T77	10		T227	474
valid_sources[0x0a]	53503	1			T76	4		T77	6		T78	3
valid_sources[0x0b]	54172	1			T76	16		T77	54		T78	2
valid_sources[0x0c]	54067	1			T76	13		T77	9		T78	1
valid_sources[0x0d]	55512	1			T76	36		T77	29		T78	3
valid_sources[0x0e]	54847	1			T76	7		T77	11		T78	1
valid_sources[0x0f]	54255	1			T76	9		T77	20		T78	2
valid_sources[0x10]	53736	1			T76	39		T77	49		T78	3
valid_sources[0x11]	53827	1			T76	12		T77	23		T78	2
valid_sources[0x12]	54673	1			T76	34		T77	24		T78	2
valid_sources[0x13]	54858	1			T76	50		T77	8		T78	2
valid_sources[0x14]	55110	1			T76	33		T77	16		T227	329
valid_sources[0x15]	54211	1			T76	12		T77	34		T131	1
valid_sources[0x16]	54402	1			T76	45		T78	2		T131	2
valid_sources[0x17]	53544	1			T76	29		T77	7		T227	247
valid_sources[0x18]	54536	1			T76	27		T77	36		T78	2
valid_sources[0x19]	53360	1			T76	32		T77	15		T78	3
valid_sources[0x1a]	53641	1			T76	5		T77	23		T78	3
valid_sources[0x1b]	54422	1			T76	19		T77	10		T78	3
valid_sources[0x1c]	54257	1			T76	22		T77	40		T78	8
valid_sources[0x1d]	53607	1			T76	31		T77	19		T227	218
valid_sources[0x1e]	54575	1			T76	28		T77	38		T227	385
valid_sources[0x1f]	54434	1			T76	12		T77	36		T78	1
valid_sources[0x20]	55092	1			T76	73		T77	20		T78	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49668

1

T76

22

T77

29

T78

4

values[0x0]

all_enables

biggest_size

375924

1

T76

167

T77

147

T78

7

values[0x1]

all_enables

biggest_size

49698

1

T76

14

T77

12

T78

3

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3206901	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

522249

1

T76

219

T77

191

T78

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1275006	1			T76	565		T77	515		T78	53
values[0x0]	1178968	1			T76	506		T77	480		T78	5
values[0x1]	1275176	1			T76	497		T77	457		T78	49

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2462921	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1266229

1

T76

547

T77

471

T78

45

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	58598	1			T76	36		T77	6		T227	284
valid_sources[0x01]	58337	1			T76	22		T77	23		T227	337
valid_sources[0x02]	57871	1			T76	42		T77	34		T131	4
valid_sources[0x03]	59523	1			T76	16		T77	9		T78	1
valid_sources[0x04]	59050	1			T76	22		T77	6		T78	2
valid_sources[0x05]	59045	1			T76	40		T77	19		T78	5
valid_sources[0x06]	57310	1			T76	20		T77	8		T78	5
valid_sources[0x07]	58249	1			T76	30		T78	1		T131	1
valid_sources[0x08]	58856	1			T76	36		T77	54		T78	3
valid_sources[0x09]	57630	1			T76	31		T77	8		T78	2
valid_sources[0x0a]	56864	1			T76	32		T77	13		T78	5
valid_sources[0x0b]	58075	1			T76	22		T77	50		T131	2
valid_sources[0x0c]	59554	1			T76	19		T77	12		T78	2
valid_sources[0x0d]	57594	1			T76	16		T77	36		T78	1
valid_sources[0x0e]	58143	1			T76	23		T77	6		T78	3
valid_sources[0x0f]	58071	1			T76	20		T77	23		T131	2
valid_sources[0x10]	58235	1			T76	20		T77	44		T78	5
valid_sources[0x11]	57778	1			T76	25		T77	30		T78	1
valid_sources[0x12]	58599	1			T76	31		T77	20		T78	5
valid_sources[0x13]	58262	1			T76	16		T77	15		T78	1
valid_sources[0x14]	58809	1			T76	22		T77	14		T78	1
valid_sources[0x15]	58945	1			T76	17		T77	32		T78	3
valid_sources[0x16]	57895	1			T76	22		T78	2		T131	5
valid_sources[0x17]	56936	1			T76	23		T77	18		T78	1
valid_sources[0x18]	57595	1			T76	19		T77	34		T131	3
valid_sources[0x19]	57239	1			T76	26		T77	9		T131	1
valid_sources[0x1a]	58180	1			T76	24		T77	31		T78	5
valid_sources[0x1b]	58546	1			T76	22		T77	5		T78	2
valid_sources[0x1c]	58109	1			T76	27		T77	42		T227	365
valid_sources[0x1d]	58693	1			T76	16		T77	15		T78	2
valid_sources[0x1e]	57695	1			T76	10		T77	51		T227	394
valid_sources[0x1f]	57873	1			T76	20		T77	34		T78	4
valid_sources[0x20]	58608	1			T76	30		T77	13		T78	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

54495

1

T76

18

T77

19

T78

6

values[0x0]

all_enables

biggest_size

412847

1

T76

177

T77

157

T78

1

values[0x1]

all_enables

biggest_size

54907

1

T76

24

T77

15

T78

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3020605	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

477212

1

T76

220

T77

190

T78

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1181228	1			T76	505		T77	488		T78	43
values[0x0]	1132192	1			T76	506		T77	473		T78	3
values[0x1]	1184397	1			T76	498		T77	477		T78	46

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2339096	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1158721

1

T76

496

T77

466

T78

38

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	54428	1			T76	6		T77	8		T78	1
valid_sources[0x01]	53968	1			T76	40		T77	21		T78	1
valid_sources[0x02]	54447	1			T76	17		T77	45		T131	3
valid_sources[0x03]	55145	1			T76	7		T77	8		T131	1
valid_sources[0x04]	54308	1			T76	27		T77	17		T78	3
valid_sources[0x05]	54844	1			T76	28		T77	15		T78	1
valid_sources[0x06]	54239	1			T76	46		T77	17		T227	336
valid_sources[0x07]	54886	1			T76	11		T78	1		T131	1
valid_sources[0x08]	55317	1			T76	28		T77	39		T131	2
valid_sources[0x09]	54553	1			T76	2		T77	7		T78	2
valid_sources[0x0a]	54785	1			T76	12		T77	19		T78	3
valid_sources[0x0b]	53949	1			T76	3		T77	78		T78	2
valid_sources[0x0c]	54473	1			T76	20		T77	5		T78	1
valid_sources[0x0d]	53917	1			T76	30		T77	23		T78	1
valid_sources[0x0e]	53666	1			T76	26		T77	5		T131	2
valid_sources[0x0f]	54883	1			T76	39		T77	27		T78	4
valid_sources[0x10]	54705	1			T76	54		T77	56		T78	2
valid_sources[0x11]	55628	1			T76	36		T77	15		T78	4
valid_sources[0x12]	54602	1			T76	11		T77	29		T78	2
valid_sources[0x13]	54536	1			T76	56		T77	9		T78	1
valid_sources[0x14]	55230	1			T76	25		T77	7		T131	1
valid_sources[0x15]	54990	1			T76	6		T77	49		T78	1
valid_sources[0x16]	54062	1			T76	21		T78	2		T131	3
valid_sources[0x17]	54018	1			T76	8		T77	11		T78	2
valid_sources[0x18]	54698	1			T76	35		T77	25		T78	2
valid_sources[0x19]	54096	1			T76	19		T77	19		T78	2
valid_sources[0x1a]	54273	1			T76	3		T77	28		T131	2
valid_sources[0x1b]	55195	1			T76	35		T77	17		T78	1
valid_sources[0x1c]	54285	1			T76	14		T77	49		T78	1
valid_sources[0x1d]	53999	1			T76	29		T77	17		T78	2
valid_sources[0x1e]	54632	1			T76	29		T77	27		T78	2
valid_sources[0x1f]	55022	1			T76	25		T77	44		T78	3
valid_sources[0x20]	54678	1			T76	38		T77	16		T78	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49613

1

T76

17

T77

20

T78

3

values[0x0]

all_enables

biggest_size

377760

1

T76

182

T77

152

T78

1

values[0x1]

all_enables

biggest_size

49839

1

T76

21

T77

18

T78

3