Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	513256253	59283176	0	0
DepthKnown_A	513256253	513148722	0	0
RvalidKnown_A	513256253	513148722	0	0
WreadyKnown_A	513256253	513148722	0	0
gen_passthru_fifo.paramCheckPass	1024	1024	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513256253	59283176	0	0
T1	136026	18457	0	0
T2	167764	192009	0	0
T3	95552	11661	0	0
T4	162400	22035	0	0
T29	242319	24298	0	0
T33	172049	20024	0	0
T62	176234	24341	0	0
T86	158443	21425	0	0
T87	598022	38809	0	0
T88	244615	25657	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513256253	513148722	0	0
T1	136026	135975	0	0
T2	167764	167672	0	0
T3	95552	95490	0	0
T4	162400	162338	0	0
T29	242319	242213	0	0
T33	172049	171951	0	0
T62	176234	176133	0	0
T86	158443	158392	0	0
T87	598022	597967	0	0
T88	244615	244553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513256253	513148722	0	0
T1	136026	135975	0	0
T2	167764	167672	0	0
T3	95552	95490	0	0
T4	162400	162338	0	0
T29	242319	242213	0	0
T33	172049	171951	0	0
T62	176234	176133	0	0
T86	158443	158392	0	0
T87	598022	597967	0	0
T88	244615	244553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513256253	513148722	0	0
T1	136026	135975	0	0
T2	167764	167672	0	0
T3	95552	95490	0	0
T4	162400	162338	0	0
T29	242319	242213	0	0
T33	172049	171951	0	0
T62	176234	176133	0	0
T86	158443	158392	0	0
T87	598022	597967	0	0
T88	244615	244553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1024	1024	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T29	1	1	0	0
T33	1	1	0	0
T62	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	513256253	45363312	0	0
DepthKnown_A	513256253	513148722	0	0
RvalidKnown_A	513256253	513148722	0	0
WreadyKnown_A	513256253	513148722	0	0
gen_passthru_fifo.paramCheckPass	1024	1024	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513256253	45363312	0	0
T1	136026	13268	0	0
T2	167764	146061	0	0
T3	95552	8924	0	0
T4	162400	16813	0	0
T29	242319	17471	0	0
T33	172049	15007	0	0
T62	176234	17071	0	0
T86	158443	16243	0	0
T87	598022	36117	0	0
T88	244615	21671	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513256253	513148722	0	0
T1	136026	135975	0	0
T2	167764	167672	0	0
T3	95552	95490	0	0
T4	162400	162338	0	0
T29	242319	242213	0	0
T33	172049	171951	0	0
T62	176234	176133	0	0
T86	158443	158392	0	0
T87	598022	597967	0	0
T88	244615	244553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513256253	513148722	0	0
T1	136026	135975	0	0
T2	167764	167672	0	0
T3	95552	95490	0	0
T4	162400	162338	0	0
T29	242319	242213	0	0
T33	172049	171951	0	0
T62	176234	176133	0	0
T86	158443	158392	0	0
T87	598022	597967	0	0
T88	244615	244553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513256253	513148722	0	0
T1	136026	135975	0	0
T2	167764	167672	0	0
T3	95552	95490	0	0
T4	162400	162338	0	0
T29	242319	242213	0	0
T33	172049	171951	0	0
T62	176234	176133	0	0
T86	158443	158392	0	0
T87	598022	597967	0	0
T88	244615	244553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1024	1024	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T29	1	1	0	0
T33	1	1	0	0
T62	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	513256253	43422108	0	0
DepthKnown_A	513256253	513148722	0	0
RvalidKnown_A	513256253	513148722	0	0
WreadyKnown_A	513256253	513148722	0	0
gen_passthru_fifo.paramCheckPass	1024	1024	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513256253	43422108	0	0
T1	136026	7409	0	0
T2	167764	105062	0	0
T3	95552	8196	0	0
T4	162400	9970	0	0
T29	242319	11942	0	0
T33	172049	11060	0	0
T62	176234	10865	0	0
T86	158443	9586	0	0
T87	598022	48810	0	0
T88	244615	23264	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513256253	513148722	0	0
T1	136026	135975	0	0
T2	167764	167672	0	0
T3	95552	95490	0	0
T4	162400	162338	0	0
T29	242319	242213	0	0
T33	172049	171951	0	0
T62	176234	176133	0	0
T86	158443	158392	0	0
T87	598022	597967	0	0
T88	244615	244553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513256253	513148722	0	0
T1	136026	135975	0	0
T2	167764	167672	0	0
T3	95552	95490	0	0
T4	162400	162338	0	0
T29	242319	242213	0	0
T33	172049	171951	0	0
T62	176234	176133	0	0
T86	158443	158392	0	0
T87	598022	597967	0	0
T88	244615	244553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513256253	513148722	0	0
T1	136026	135975	0	0
T2	167764	167672	0	0
T3	95552	95490	0	0
T4	162400	162338	0	0
T29	242319	242213	0	0
T33	172049	171951	0	0
T62	176234	176133	0	0
T86	158443	158392	0	0
T87	598022	597967	0	0
T88	244615	244553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1024	1024	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T29	1	1	0	0
T33	1	1	0	0
T62	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	513256253	36458318	0	0
DepthKnown_A	513256253	513148722	0	0
RvalidKnown_A	513256253	513148722	0	0
WreadyKnown_A	513256253	513148722	0	0
gen_passthru_fifo.paramCheckPass	1024	1024	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513256253	36458318	0	0
T1	136026	7132	0	0
T2	167764	102785	0	0
T3	95552	7611	0	0
T4	162400	9690	0	0
T29	242319	11603	0	0
T33	172049	10710	0	0
T62	176234	10484	0	0
T86	158443	9308	0	0
T87	598022	48667	0	0
T88	244615	23059	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513256253	513148722	0	0
T1	136026	135975	0	0
T2	167764	167672	0	0
T3	95552	95490	0	0
T4	162400	162338	0	0
T29	242319	242213	0	0
T33	172049	171951	0	0
T62	176234	176133	0	0
T86	158443	158392	0	0
T87	598022	597967	0	0
T88	244615	244553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513256253	513148722	0	0
T1	136026	135975	0	0
T2	167764	167672	0	0
T3	95552	95490	0	0
T4	162400	162338	0	0
T29	242319	242213	0	0
T33	172049	171951	0	0
T62	176234	176133	0	0
T86	158443	158392	0	0
T87	598022	597967	0	0
T88	244615	244553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	513256253	513148722	0	0
T1	136026	135975	0	0
T2	167764	167672	0	0
T3	95552	95490	0	0
T4	162400	162338	0	0
T29	242319	242213	0	0
T33	172049	171951	0	0
T62	176234	176133	0	0
T86	158443	158392	0	0
T87	598022	597967	0	0
T88	244615	244553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1024	1024	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T29	1	1	0	0
T33	1	1	0	0
T62	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	596807424	95665	0	0
DepthKnown_A	596807424	596684013	0	0
RvalidKnown_A	596807424	596684013	0	0
WreadyKnown_A	596807424	596684013	0	0
gen_passthru_fifo.paramCheckPass	2932	2932	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596807424	95665	0	0
T1	136026	26	0	0
T2	167764	286	0	0
T3	95552	34	0	0
T4	162400	26	0	0
T29	242319	102	0	0
T33	172049	74	0	0
T62	176234	40	0	0
T86	158443	26	0	0
T87	598022	14	0	0
T88	244615	53	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596807424	596684013	0	0
T1	136026	135975	0	0
T2	167764	167672	0	0
T3	95552	95490	0	0
T4	162400	162338	0	0
T29	242319	242213	0	0
T33	172049	171951	0	0
T62	176234	176133	0	0
T86	158443	158392	0	0
T87	598022	597967	0	0
T88	244615	244553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596807424	596684013	0	0
T1	136026	135975	0	0
T2	167764	167672	0	0
T3	95552	95490	0	0
T4	162400	162338	0	0
T29	242319	242213	0	0
T33	172049	171951	0	0
T62	176234	176133	0	0
T86	158443	158392	0	0
T87	598022	597967	0	0
T88	244615	244553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596807424	596684013	0	0
T1	136026	135975	0	0
T2	167764	167672	0	0
T3	95552	95490	0	0
T4	162400	162338	0	0
T29	242319	242213	0	0
T33	172049	171951	0	0
T62	176234	176133	0	0
T86	158443	158392	0	0
T87	598022	597967	0	0
T88	244615	244553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2932	2932	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T29	1	1	0	0
T33	1	1	0	0
T62	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	596807424	99049	0	0
DepthKnown_A	596807424	596684013	0	0
RvalidKnown_A	596807424	596684013	0	0
WreadyKnown_A	596807424	596684013	0	0
gen_passthru_fifo.paramCheckPass	2932	2932	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596807424	99049	0	0
T1	136026	26	0	0
T2	167764	286	0	0
T3	95552	34	0	0
T4	162400	26	0	0
T29	242319	102	0	0
T33	172049	74	0	0
T62	176234	40	0	0
T86	158443	26	0	0
T87	598022	14	0	0
T88	244615	53	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596807424	596684013	0	0
T1	136026	135975	0	0
T2	167764	167672	0	0
T3	95552	95490	0	0
T4	162400	162338	0	0
T29	242319	242213	0	0
T33	172049	171951	0	0
T62	176234	176133	0	0
T86	158443	158392	0	0
T87	598022	597967	0	0
T88	244615	244553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596807424	596684013	0	0
T1	136026	135975	0	0
T2	167764	167672	0	0
T3	95552	95490	0	0
T4	162400	162338	0	0
T29	242319	242213	0	0
T33	172049	171951	0	0
T62	176234	176133	0	0
T86	158443	158392	0	0
T87	598022	597967	0	0
T88	244615	244553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596807424	596684013	0	0
T1	136026	135975	0	0
T2	167764	167672	0	0
T3	95552	95490	0	0
T4	162400	162338	0	0
T29	242319	242213	0	0
T33	172049	171951	0	0
T62	176234	176133	0	0
T86	158443	158392	0	0
T87	598022	597967	0	0
T88	244615	244553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2932	2932	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T29	1	1	0	0
T33	1	1	0	0
T62	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	596807424	51979	0	0
DepthKnown_A	596807424	596684013	0	0
RvalidKnown_A	596807424	596684013	0	0
WreadyKnown_A	596807424	596684013	0	0
gen_passthru_fifo.paramCheckPass	2932	2932	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596807424	51979	0	0
T1	136026	23	0	0
T2	167764	250	0	0
T3	95552	33	0	0
T4	162400	23	0	0
T29	242319	94	0	0
T33	172049	72	0	0
T62	176234	34	0	0
T86	158443	23	0	0
T87	598022	12	0	0
T88	244615	52	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596807424	596684013	0	0
T1	136026	135975	0	0
T2	167764	167672	0	0
T3	95552	95490	0	0
T4	162400	162338	0	0
T29	242319	242213	0	0
T33	172049	171951	0	0
T62	176234	176133	0	0
T86	158443	158392	0	0
T87	598022	597967	0	0
T88	244615	244553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596807424	596684013	0	0
T1	136026	135975	0	0
T2	167764	167672	0	0
T3	95552	95490	0	0
T4	162400	162338	0	0
T29	242319	242213	0	0
T33	172049	171951	0	0
T62	176234	176133	0	0
T86	158443	158392	0	0
T87	598022	597967	0	0
T88	244615	244553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596807424	596684013	0	0
T1	136026	135975	0	0
T2	167764	167672	0	0
T3	95552	95490	0	0
T4	162400	162338	0	0
T29	242319	242213	0	0
T33	172049	171951	0	0
T62	176234	176133	0	0
T86	158443	158392	0	0
T87	598022	597967	0	0
T88	244615	244553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2932	2932	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T29	1	1	0	0
T33	1	1	0	0
T62	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	596807424	51978	0	0
DepthKnown_A	596807424	596684013	0	0
RvalidKnown_A	596807424	596684013	0	0
WreadyKnown_A	596807424	596684013	0	0
gen_passthru_fifo.paramCheckPass	2932	2932	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596807424	51978	0	0
T1	136026	23	0	0
T2	167764	250	0	0
T3	95552	33	0	0
T4	162400	23	0	0
T29	242319	94	0	0
T33	172049	72	0	0
T62	176234	34	0	0
T86	158443	23	0	0
T87	598022	12	0	0
T88	244615	52	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596807424	596684013	0	0
T1	136026	135975	0	0
T2	167764	167672	0	0
T3	95552	95490	0	0
T4	162400	162338	0	0
T29	242319	242213	0	0
T33	172049	171951	0	0
T62	176234	176133	0	0
T86	158443	158392	0	0
T87	598022	597967	0	0
T88	244615	244553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596807424	596684013	0	0
T1	136026	135975	0	0
T2	167764	167672	0	0
T3	95552	95490	0	0
T4	162400	162338	0	0
T29	242319	242213	0	0
T33	172049	171951	0	0
T62	176234	176133	0	0
T86	158443	158392	0	0
T87	598022	597967	0	0
T88	244615	244553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596807424	596684013	0	0
T1	136026	135975	0	0
T2	167764	167672	0	0
T3	95552	95490	0	0
T4	162400	162338	0	0
T29	242319	242213	0	0
T33	172049	171951	0	0
T62	176234	176133	0	0
T86	158443	158392	0	0
T87	598022	597967	0	0
T88	244615	244553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2932	2932	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T29	1	1	0	0
T33	1	1	0	0
T62	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	596807424	43686	0	0
DepthKnown_A	596807424	596684013	0	0
RvalidKnown_A	596807424	596684013	0	0
WreadyKnown_A	596807424	596684013	0	0
gen_passthru_fifo.paramCheckPass	2932	2932	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596807424	43686	0	0
T1	136026	3	0	0
T2	167764	36	0	0
T3	95552	1	0	0
T4	162400	3	0	0
T29	242319	8	0	0
T33	172049	2	0	0
T62	176234	6	0	0
T86	158443	3	0	0
T87	598022	2	0	0
T88	244615	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596807424	596684013	0	0
T1	136026	135975	0	0
T2	167764	167672	0	0
T3	95552	95490	0	0
T4	162400	162338	0	0
T29	242319	242213	0	0
T33	172049	171951	0	0
T62	176234	176133	0	0
T86	158443	158392	0	0
T87	598022	597967	0	0
T88	244615	244553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596807424	596684013	0	0
T1	136026	135975	0	0
T2	167764	167672	0	0
T3	95552	95490	0	0
T4	162400	162338	0	0
T29	242319	242213	0	0
T33	172049	171951	0	0
T62	176234	176133	0	0
T86	158443	158392	0	0
T87	598022	597967	0	0
T88	244615	244553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596807424	596684013	0	0
T1	136026	135975	0	0
T2	167764	167672	0	0
T3	95552	95490	0	0
T4	162400	162338	0	0
T29	242319	242213	0	0
T33	172049	171951	0	0
T62	176234	176133	0	0
T86	158443	158392	0	0
T87	598022	597967	0	0
T88	244615	244553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2932	2932	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T29	1	1	0	0
T33	1	1	0	0
T62	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	596807424	47071	0	0
DepthKnown_A	596807424	596684013	0	0
RvalidKnown_A	596807424	596684013	0	0
WreadyKnown_A	596807424	596684013	0	0
gen_passthru_fifo.paramCheckPass	2932	2932	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596807424	47071	0	0
T1	136026	3	0	0
T2	167764	36	0	0
T3	95552	1	0	0
T4	162400	3	0	0
T29	242319	8	0	0
T33	172049	2	0	0
T62	176234	6	0	0
T86	158443	3	0	0
T87	598022	2	0	0
T88	244615	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596807424	596684013	0	0
T1	136026	135975	0	0
T2	167764	167672	0	0
T3	95552	95490	0	0
T4	162400	162338	0	0
T29	242319	242213	0	0
T33	172049	171951	0	0
T62	176234	176133	0	0
T86	158443	158392	0	0
T87	598022	597967	0	0
T88	244615	244553	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596807424	596684013	0	0
T1	136026	135975	0	0
T2	167764	167672	0	0
T3	95552	95490	0	0
T4	162400	162338	0	0
T29	242319	242213	0	0
T33	172049	171951	0	0
T62	176234	176133	0	0
T86	158443	158392	0	0
T87	598022	597967	0	0
T88	244615	244553	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	596807424	596684013	0	0
T1	136026	135975	0	0
T2	167764	167672	0	0
T3	95552	95490	0	0
T4	162400	162338	0	0
T29	242319	242213	0	0
T33	172049	171951	0	0
T62	176234	176133	0	0
T86	158443	158392	0	0
T87	598022	597967	0	0
T88	244615	244553	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2932	2932	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T29	1	1	0	0
T33	1	1	0	0
T62	1	1	0	0
T86	1	1	0	0
T87	1	1	0	0
T88	1	1	0	0