Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T88,T44,T120	Yes	T88,T44,T120	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T88,T44,T120	Yes	T88,T44,T120	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T45,*T46,*T79	Yes	T45,T46,T79	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T46,T80,T81	Yes	T46,T80,T81	INPUT
tl_i.a_valid	Yes	Yes	T88,T44,T120	Yes	T88,T44,T120	INPUT
tl_o.a_ready	Yes	Yes	T88,T120,T277	Yes	T88,T120,T277	OUTPUT
tl_o.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T88,T120,T277	Yes	T88,T120,T277	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T88,T120,T277	Yes	T88,T120,T277	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T88,T120,T277	Yes	T88,T120,T277	OUTPUT
tl_o.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T234,*T760,*T147	Yes	T234,T760,T147	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T88,*T120,*T277	Yes	T88,T120,T277	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T88,T120,T277	Yes	T88,T120,T277	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T83,T728	Yes	T1,T83,T728	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T83,T737,T724	Yes	T83,T84,T159	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T83,T84,T159	Yes	T83,T737,T724	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T83,T728	Yes	T1,T83,T728	OUTPUT
cio_rx_i	Yes	Yes	T2,T88,T29	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T88,T120,T277	Yes	T88,T120,T277	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T88,T120,T277	Yes	T88,T120,T277	OUTPUT
intr_tx_empty_o	Yes	Yes	T88,T120,T277	Yes	T88,T120,T277	OUTPUT
intr_rx_watermark_o	Yes	Yes	T88,T120,T277	Yes	T88,T120,T277	OUTPUT
intr_tx_done_o	Yes	Yes	T88,T120,T277	Yes	T88,T120,T277	OUTPUT
intr_rx_overflow_o	Yes	Yes	T88,T120,T277	Yes	T88,T120,T277	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T317,T332,T320	Yes	T317,T332,T320	OUTPUT
intr_rx_break_err_o	Yes	Yes	T317,T332,T320	Yes	T317,T332,T320	OUTPUT
intr_rx_timeout_o	Yes	Yes	T317,T332,T320	Yes	T317,T332,T320	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T317,T332,T320	Yes	T317,T332,T320	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T88,T44,T277	Yes	T88,T44,T277	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T88,T44,T277	Yes	T88,T44,T277	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T45,*T46,*T79	Yes	T45,T46,T79	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T46,T80,T81	Yes	T46,T80,T81	INPUT
tl_i.a_valid	Yes	Yes	T88,T44,T277	Yes	T88,T44,T277	INPUT
tl_o.a_ready	Yes	Yes	T88,T277,T43	Yes	T88,T277,T43	OUTPUT
tl_o.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T88,T277,T43	Yes	T88,T277,T43	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T88,T277,T43	Yes	T88,T277,T43	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T88,T277,T43	Yes	T88,T277,T43	OUTPUT
tl_o.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T234,*T760,*T147	Yes	T234,T760,T147	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T88,*T277,*T43	Yes	T88,T277,T43	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T88,T277,T43	Yes	T88,T277,T43	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T83,T728,T323	Yes	T83,T728,T323	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T83,T724,T84	Yes	T83,T84,T159	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T83,T84,T159	Yes	T83,T724,T84	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T83,T728,T323	Yes	T83,T728,T323	OUTPUT
cio_rx_i	Yes	Yes	T2,T88,T29	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T88,T277,T43	Yes	T88,T277,T43	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T88,T277,T307	Yes	T88,T277,T307	OUTPUT
intr_tx_empty_o	Yes	Yes	T88,T277,T307	Yes	T88,T277,T307	OUTPUT
intr_rx_watermark_o	Yes	Yes	T88,T277,T307	Yes	T88,T277,T307	OUTPUT
intr_tx_done_o	Yes	Yes	T88,T277,T307	Yes	T88,T277,T307	OUTPUT
intr_rx_overflow_o	Yes	Yes	T88,T277,T307	Yes	T88,T277,T307	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T317,T332,T320	Yes	T317,T332,T320	OUTPUT
intr_rx_break_err_o	Yes	Yes	T317,T332,T320	Yes	T317,T332,T320	OUTPUT
intr_rx_timeout_o	Yes	Yes	T317,T332,T320	Yes	T317,T332,T320	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T317,T332,T320	Yes	T317,T332,T320	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T317,T275,T333	Yes	T317,T275,T333	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T317,T275,T333	Yes	T317,T275,T333	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T45,*T46,*T79	Yes	T45,T46,T79	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T46,T80,T81	Yes	T46,T80,T81	INPUT
tl_i.a_valid	Yes	Yes	T317,T275,T333	Yes	T317,T275,T333	INPUT
tl_o.a_ready	Yes	Yes	T317,T275,T333	Yes	T317,T275,T333	OUTPUT
tl_o.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T317,T275,T333	Yes	T317,T275,T333	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T317,T275,T333	Yes	T317,T275,T333	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T317,T275,T333	Yes	T317,T275,T333	OUTPUT
tl_o.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T147,*T76,*T77	Yes	T147,T76,T77	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T317,*T275,*T333	Yes	T317,T275,T333	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T317,T275,T333	Yes	T317,T275,T333	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T83,T98,T729	Yes	T83,T98,T729	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T83,T98,T729	Yes	T83,T98,T729	OUTPUT
cio_rx_i	Yes	Yes	T31,T275,T333	Yes	T7,T31,T275	INPUT
cio_tx_o	Yes	Yes	T275,T333,T348	Yes	T275,T333,T348	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T317,T275,T333	Yes	T317,T275,T333	OUTPUT
intr_tx_empty_o	Yes	Yes	T317,T275,T333	Yes	T317,T275,T333	OUTPUT
intr_rx_watermark_o	Yes	Yes	T317,T275,T333	Yes	T317,T275,T333	OUTPUT
intr_tx_done_o	Yes	Yes	T317,T275,T333	Yes	T317,T275,T333	OUTPUT
intr_rx_overflow_o	Yes	Yes	T317,T275,T333	Yes	T317,T275,T333	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T317,T332,T320	Yes	T317,T332,T320	OUTPUT
intr_rx_break_err_o	Yes	Yes	T317,T332,T320	Yes	T317,T332,T320	OUTPUT
intr_rx_timeout_o	Yes	Yes	T317,T332,T320	Yes	T317,T332,T320	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T317,T332,T320	Yes	T317,T332,T320	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T120,T317,T328	Yes	T120,T317,T328	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T120,T317,T328	Yes	T120,T317,T328	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T45,*T46,*T79	Yes	T45,T46,T79	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T46,T80,T81	Yes	T46,T80,T81	INPUT
tl_i.a_valid	Yes	Yes	T120,T317,T328	Yes	T120,T317,T328	INPUT
tl_o.a_ready	Yes	Yes	T120,T317,T328	Yes	T120,T317,T328	OUTPUT
tl_o.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T120,T317,T328	Yes	T120,T317,T328	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T120,T317,T328	Yes	T120,T317,T328	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T120,T317,T328	Yes	T120,T317,T328	OUTPUT
tl_o.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T147,*T76,*T77	Yes	T147,T76,T77	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T120,*T317,*T328	Yes	T120,T317,T328	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T120,T317,T328	Yes	T120,T317,T328	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T83,T323,T48	Yes	T83,T323,T48	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T83,T323,T48	Yes	T83,T323,T48	OUTPUT
cio_rx_i	Yes	Yes	T120,T328,T334	Yes	T120,T328,T334	INPUT
cio_tx_o	Yes	Yes	T120,T328,T334	Yes	T120,T328,T334	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T120,T317,T328	Yes	T120,T317,T328	OUTPUT
intr_tx_empty_o	Yes	Yes	T120,T317,T328	Yes	T120,T317,T328	OUTPUT
intr_rx_watermark_o	Yes	Yes	T120,T317,T328	Yes	T120,T317,T328	OUTPUT
intr_tx_done_o	Yes	Yes	T120,T317,T328	Yes	T120,T317,T328	OUTPUT
intr_rx_overflow_o	Yes	Yes	T120,T317,T328	Yes	T120,T317,T328	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T317,T332,T320	Yes	T317,T332,T320	OUTPUT
intr_rx_break_err_o	Yes	Yes	T317,T332,T320	Yes	T317,T332,T320	OUTPUT
intr_rx_timeout_o	Yes	Yes	T317,T332,T320	Yes	T317,T332,T320	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T317,T332,T320	Yes	T317,T332,T320	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T14,T317,T266	Yes	T14,T317,T266	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T14,T317,T266	Yes	T14,T317,T266	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T45,*T46,*T79	Yes	T45,T46,T79	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T46,T80,T81	Yes	T46,T80,T81	INPUT
tl_i.a_valid	Yes	Yes	T14,T317,T266	Yes	T14,T317,T266	INPUT
tl_o.a_ready	Yes	Yes	T14,T317,T266	Yes	T14,T317,T266	OUTPUT
tl_o.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T14,T317,T266	Yes	T14,T317,T266	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T14,T317,T266	Yes	T14,T317,T266	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T14,T317,T266	Yes	T14,T317,T266	OUTPUT
tl_o.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T147,*T76,*T77	Yes	T147,T76,T77	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T14,*T317,*T266	Yes	T14,T317,T266	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T14,T317,T266	Yes	T14,T317,T266	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T83,T730	Yes	T1,T83,T730	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T83,T737,T84	Yes	T83,T84,T85	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T83,T84,T85	Yes	T83,T737,T84	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T83,T730	Yes	T1,T83,T730	OUTPUT
cio_rx_i	Yes	Yes	T14,T266,T349	Yes	T14,T266,T349	INPUT
cio_tx_o	Yes	Yes	T14,T266,T349	Yes	T14,T266,T349	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T14,T317,T266	Yes	T14,T317,T266	OUTPUT
intr_tx_empty_o	Yes	Yes	T14,T317,T266	Yes	T14,T317,T266	OUTPUT
intr_rx_watermark_o	Yes	Yes	T14,T317,T266	Yes	T14,T317,T266	OUTPUT
intr_tx_done_o	Yes	Yes	T14,T317,T266	Yes	T14,T317,T266	OUTPUT
intr_rx_overflow_o	Yes	Yes	T14,T317,T266	Yes	T14,T317,T266	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T317,T332,T320	Yes	T317,T332,T320	OUTPUT
intr_rx_break_err_o	Yes	Yes	T317,T332,T320	Yes	T317,T332,T320	OUTPUT
intr_rx_timeout_o	Yes	Yes	T317,T332,T320	Yes	T317,T332,T320	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T317,T332,T320	Yes	T317,T332,T320	OUTPUT

*Tests covering at least one bit in the range