Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T77,T78,T227	Yes	T76,T77,T78	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T29,T196,T228	Yes	T29,T196,T228	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T29,T196,T220	Yes	T29,T196,T220	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T46,T80,T81	Yes	T46,T80,T81	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T80,T76,T77	Yes	T80,T76,T77	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T80,T76,T77	Yes	T80,T76,T77	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T29,T65,T196	Yes	T29,T65,T196	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T45,T46,T79	Yes	T45,T46,T79	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T45,T46,T79	Yes	T45,T46,T79	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T45,T46,T79	Yes	T45,T46,T79	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T45,T46,T79	Yes	T45,T46,T79	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T45,T46,T63	Yes	T45,T46,T63	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T45,T46,T79	Yes	T45,T46,T79	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T45,*T46,*T79	Yes	T45,T46,T79	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T45,T46,T79	Yes	T45,T46,T79	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T77,T78,T227	Yes	T76,T77,T78	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T79,T233,T234	Yes	T79,T233,T234	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T79,T233,T234	Yes	T79,T233,T234	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T79,T233,T234	Yes	T79,T233,T234	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T79,T233,T234	Yes	T79,T233,T234	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T79,T233,T234	Yes	T79,T233,T234	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T79,*T233,*T234	Yes	T79,T233,T234	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T79,T233,T234	Yes	T79,T233,T234	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T2,T62,T33	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T79,T233,T234	Yes	T79,T233,T234	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T79,T233,T234	Yes	T79,T233,T234	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T2,T62,T33	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T79,*T233,*T234	Yes	T79,T233,T234	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T62,T33	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T79,T233,T234	Yes	T79,T233,T234	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T43,T40,T63	Yes	T43,T40,T63	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T43,T40,T41	Yes	T43,T40,T41	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T48,T49,T50	Yes	T48,T49,T50	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T247,T406,T48	Yes	T247,T406,T48	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T247,T406,T48	Yes	T247,T406,T48	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T48,T49,T50	Yes	T48,T49,T50	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T247,T406,T48	Yes	T247,T406,T48	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T247,T406,T48	Yes	T247,T406,T48	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T247,T406,T48	Yes	T247,T406,T48	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T247,T407,T408	Yes	T247,T407,T408	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T76,T77,T78	Yes	T48,T49,T50	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T247,T407,T408	Yes	T247,T48,T407	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T247,*T406,*T409	Yes	T247,T406,T407	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T247,T406,T48	Yes	T247,T406,T48	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T45,*T46,*T79	Yes	T45,T46,T79	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T46,T80,T81	Yes	T46,T80,T81	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T220,T361,T465	Yes	T220,T361,T465	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T45,*T46,*T79	Yes	T45,T46,T79	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T396,T10,T153	Yes	T396,T10,T153	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T10,T153,T154	Yes	T10,T153,T154	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T396,T10,T153	Yes	T396,T10,T153	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T396,T10,T153	Yes	T396,T10,T153	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T10,T153,T154	Yes	T10,T153,T154	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T396,T10,T153	Yes	T396,T10,T153	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T205,*T76,*T77	Yes	T205,T76,T77	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T198,T199,T200	Yes	T198,T199,T200	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T396,T10,T153	Yes	T396,T10,T153	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T396,T10,T153	Yes	T396,T10,T153	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T10,T153,T154	Yes	T10,T153,T154	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T396,T10,T153	Yes	T396,T10,T153	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T10,T153,T154	Yes	T10,T153,T154	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T205,*T76,*T77	Yes	T205,T76,T77	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T396,*T10,*T153	Yes	T396,T10,T153	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T396,T10,T153	Yes	T396,T10,T153	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T31,T396,T153	Yes	T31,T396,T153	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T31,T153,T154	Yes	T31,T153,T154	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T31,T396,T153	Yes	T31,T396,T153	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T31,T396,T153	Yes	T31,T396,T153	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T31,T153,T154	Yes	T31,T153,T154	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T31,T396,T153	Yes	T31,T396,T153	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T205,*T76,*T77	Yes	T205,T76,T77	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T31,T396,T153	Yes	T31,T396,T153	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T31,T396,T153	Yes	T31,T396,T153	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T31,T153,T154	Yes	T31,T153,T154	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T31,T396,T153	Yes	T31,T396,T153	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T31,T153,T154	Yes	T31,T153,T154	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T205,*T76,*T77	Yes	T205,T76,T77	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T31,*T396,*T153	Yes	T31,T396,T153	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T31,T396,T153	Yes	T31,T396,T153	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T16,T17,T317	Yes	T16,T17,T317	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T16,T17,T317	Yes	T16,T17,T317	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T16,T17,T317	Yes	T16,T17,T317	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T16,T17,T317	Yes	T16,T17,T317	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T16,T17,T317	Yes	T16,T17,T317	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T16,T17,T317	Yes	T16,T17,T317	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T147,*T76,*T77	Yes	T147,T76,T77	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T16,T17,T317	Yes	T16,T17,T317	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T16,T17,T317	Yes	T16,T17,T317	INPUT
tl_usbdev_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T17,T317,T396	Yes	T17,T317,T396	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T17,T317,T396	Yes	T17,T317,T396	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T16,T17,T317	Yes	T16,T17,T317	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T147,*T76,*T77	Yes	T147,T76,T77	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T16,*T17,*T317	Yes	T16,T17,T317	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T16,T17,T317	Yes	T16,T17,T317	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T46,*T76,*T77	Yes	T46,T76,T77	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T2,T62,T33	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T2,T62,T33	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T46,*T76,*T77	Yes	T46,T76,T77	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T46,T76,T77	Yes	T46,T76,T77	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T46,T76,T77	Yes	T46,T76,T77	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T46,T76,T77	Yes	T46,T76,T77	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T46,T76,T77	Yes	T46,T76,T77	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T46,T76,T77	Yes	T46,T76,T77	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T46,T76,T77	Yes	T46,T76,T77	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T46,T76,T77	Yes	T46,T76,T77	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T46,T77,T78	Yes	T46,T76,T77	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T46,T76,T77	Yes	T46,T76,T77	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T46,T76,T77	Yes	T46,T76,T77	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T46,T76,T77	Yes	T46,T76,T77	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T46,*T76,*T77	Yes	T46,T76,T77	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T46,T76,T77	Yes	T46,T76,T77	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T2,T62,T33	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_hmac_o.d_ready	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T46,T43,T40	Yes	T46,T43,T40	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T46,T43,T40	Yes	T46,T43,T40	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T30,T222,T254	Yes	T30,T222,T254	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T46,T43,T40	Yes	T46,T43,T40	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T30,T222,T254	Yes	T30,T222,T254	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T46,*T76,*T77	Yes	T46,T76,T77	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T100,T103,T749	Yes	T100,T103,T749	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T30,T222,T254	Yes	T30,T222,T254	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T30,T222,T254	Yes	T30,T222,T254	INPUT
tl_hmac_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T30,T222,T254	Yes	T30,T222,T254	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T30,T222,T254	Yes	T30,T222,T254	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T46,T43,T40	Yes	T46,T43,T40	INPUT
tl_hmac_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T46,*T76,*T77	Yes	T46,T76,T77	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T46,*T43,*T40	Yes	T46,T43,T40	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T30,T222,T254	Yes	T30,T222,T254	INPUT
tl_kmac_o.d_ready	Yes	Yes	T2,T3,T62	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T3,T95,T151	Yes	T3,T95,T151	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T3,T30,T95	Yes	T3,T30,T95	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T3,T30,T95	Yes	T3,T30,T95	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T3,T95,T151	Yes	T3,T95,T151	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T3,T30,T95	Yes	T3,T30,T95	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T46,*T76,*T77	Yes	T46,T76,T77	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T3,T95,T457	Yes	T3,T95,T457	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T3,T30,T95	Yes	T3,T30,T95	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T3,T30,T95	Yes	T3,T30,T95	INPUT
tl_kmac_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T3,T30,T95	Yes	T3,T30,T95	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T30,T95	Yes	T3,T30,T95	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T3,T95,T151	Yes	T3,T95,T151	INPUT
tl_kmac_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T46,*T76,*T77	Yes	T46,T76,T77	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T3,*T95,*T151	Yes	T3,T95,T457	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T3,T30,T95	Yes	T3,T30,T95	INPUT
tl_aes_o.d_ready	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T128,T46,T130	Yes	T128,T46,T130	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T128,T46,T130	Yes	T128,T46,T130	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T30,T128,T222	Yes	T30,T128,T222	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T128,T46,T130	Yes	T128,T46,T130	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T30,T128,T222	Yes	T30,T128,T222	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T46,*T76,*T77	Yes	T46,T76,T77	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T30,T128,T222	Yes	T30,T128,T222	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T30,T128,T222	Yes	T30,T128,T222	INPUT
tl_aes_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T30,T128,T222	Yes	T30,T128,T222	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T128,T46,T130	Yes	T128,T46,T130	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T30,T128,T222	Yes	T30,T128,T222	INPUT
tl_aes_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T46,*T76,*T77	Yes	T46,T76,T77	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T30,*T128,*T222	Yes	T30,T128,T222	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T30,T128,T222	Yes	T30,T128,T222	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T46,*T76,*T77	Yes	T46,T76,T77	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T128,T129,T46	Yes	T128,T129,T46	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T46,*T76,*T77	Yes	T46,T76,T77	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T128,*T129,*T46	Yes	T128,T129,T46	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T128,T129,T46	Yes	T128,T129,T46	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T46,*T76,*T77	Yes	T46,T76,T77	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T128,T129,T46	Yes	T128,T129,T46	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T46,*T76,*T77	Yes	T46,T76,T77	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T128,*T129,*T46	Yes	T128,T129,T46	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T128,T129,T46	Yes	T128,T129,T46	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T128,T129,T46	Yes	T128,T129,T46	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T46,*T76,*T77	Yes	T46,T76,T77	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T128,T129,T46	Yes	T128,T129,T46	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T46,*T76,*T77	Yes	T46,T76,T77	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T128,*T129,*T46	Yes	T128,T129,T46	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T128,T129,T46	Yes	T128,T129,T46	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T128,T129,T46	Yes	T128,T129,T46	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T128,T129,T46	Yes	T128,T129,T46	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T128,T129,T46	Yes	T128,T129,T46	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T128,T129,T46	Yes	T128,T129,T46	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T46,*T76,*T77	Yes	T46,T76,T77	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T128,T129,T46	Yes	T128,T129,T46	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T128,T129,T46	Yes	T128,T129,T46	INPUT
tl_edn1_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T128,T129,T46	Yes	T128,T129,T46	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T128,T129,T46	Yes	T128,T129,T46	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T128,T129,T46	Yes	T128,T129,T46	INPUT
tl_edn1_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T46,*T76,*T77	Yes	T46,T76,T77	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T128,*T129,*T46	Yes	T128,T129,T46	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T128,T129,T46	Yes	T128,T129,T46	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T205,*T76,*T77	Yes	T205,T76,T77	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T205,*T76,*T77	Yes	T205,T76,T77	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_otbn_o.d_ready	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T129,T130,T43	Yes	T129,T130,T43	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T30,T222,T254	Yes	T30,T222,T254	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T30,T222,T254	Yes	T30,T222,T254	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T129,T130,T43	Yes	T129,T130,T43	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T30,T222,T254	Yes	T30,T222,T254	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T80,*T81,*T204	Yes	T80,T81,T204	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T30,T222,T254	Yes	T30,T222,T254	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T30,T222,T254	Yes	T30,T222,T254	INPUT
tl_otbn_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T129,T130,T43	Yes	T129,T130,T43	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T222,T129,T130	Yes	T222,T129,T130	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T222,T129,T130	Yes	T222,T129,T130	INPUT
tl_otbn_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T80,*T81,*T204	Yes	T80,T81,T204	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T129,*T130,*T43	Yes	T129,T130,T43	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T222,T129,T130	Yes	T222,T129,T130	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T44,T151,T152	Yes	T44,T151,T152	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T44,T151,T152	Yes	T44,T151,T152	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T44,T151,T152	Yes	T44,T151,T152	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T44,T151,T46	Yes	T44,T151,T46	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T44,T151,T152	Yes	T44,T151,T152	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T46,*T76,*T77	Yes	T46,T76,T77	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T44,T151,T152	Yes	T44,T151,T152	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T44,T151,T152	Yes	T44,T151,T152	INPUT
tl_keymgr_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T44,T151,T46	Yes	T44,T151,T46	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T44,T151,T46	Yes	T44,T151,T46	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T44,T151,T46	Yes	T44,T151,T46	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T46,*T76,*T77	Yes	T46,T76,T77	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T44,*T151,*T46	Yes	T44,T151,T152	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T44,T151,T152	Yes	T44,T151,T152	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T2,T62,T33	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T45,T43,T40	Yes	T45,T43,T40	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T45,T43,T40	Yes	T45,T43,T40	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T45,T43,T40	Yes	T45,T43,T40	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T45,T43,T40	Yes	T45,T43,T40	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T45,T43,T40	Yes	T45,T43,T40	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T205,*T76,*T77	Yes	T205,T76,T77	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T45,T43,T40	Yes	T45,T43,T40	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T45,T43,T40	Yes	T45,T43,T40	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T182,T273,T274	Yes	T182,T273,T274	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T40,T41,T42	Yes	T45,T43,T40	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T40,T41,T42	Yes	T45,T43,T40	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T205,*T76,*T77	Yes	T205,T76,T77	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T182,*T178,*T180	Yes	T450,T182,T451	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T45,T43,T40	Yes	T45,T43,T40	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T2,T62,T33	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range