5fd4ecc0fc| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | chip_sw_example_tests | chip_sw_example_flash | 4.405m | 2.424ms | 3 | 3 | 100.00 |
| chip_sw_example_rom | 2.398m | 2.678ms | 3 | 3 | 100.00 | ||
| chip_sw_example_manufacturer | 4.787m | 2.646ms | 3 | 3 | 100.00 | ||
| chip_sw_example_concurrency | 5.261m | 3.012ms | 3 | 3 | 100.00 | ||
| V1 | csr_hw_reset | chip_csr_hw_reset | 8.069m | 8.054ms | 4 | 5 | 80.00 |
| V1 | csr_rw | chip_csr_rw | 11.977m | 5.335ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | chip_csr_bit_bash | 55.891m | 32.107ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | chip_csr_aliasing | 2.817h | 69.077ms | 3 | 5 | 60.00 |
| V1 | csr_mem_rw_with_rand_reset | chip_csr_mem_rw_with_rand_reset | 18.368m | 9.334ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | chip_csr_aliasing | 2.817h | 69.077ms | 3 | 5 | 60.00 |
| chip_csr_rw | 11.977m | 5.335ms | 20 | 20 | 100.00 | ||
| V1 | xbar_smoke | xbar_smoke | 11.170s | 247.656us | 100 | 100 | 100.00 |
| V1 | chip_sw_gpio_out | chip_sw_gpio | 8.468m | 3.150ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_in | chip_sw_gpio | 8.468m | 3.150ms | 3 | 3 | 100.00 |
| V1 | chip_sw_gpio_irq | chip_sw_gpio | 8.468m | 3.150ms | 3 | 3 | 100.00 |
| V1 | chip_sw_uart_tx_rx | chip_sw_uart_tx_rx | 14.739m | 4.742ms | 5 | 5 | 100.00 |
| V1 | chip_sw_uart_rx_overflow | chip_sw_uart_tx_rx | 14.739m | 4.742ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_idx1 | 14.502m | 4.404ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx2 | 14.560m | 4.156ms | 5 | 5 | 100.00 | ||
| chip_sw_uart_tx_rx_idx3 | 14.490m | 4.728ms | 5 | 5 | 100.00 | ||
| V1 | chip_sw_uart_baud_rate | chip_sw_uart_rand_baudrate | 48.401m | 13.482ms | 20 | 20 | 100.00 |
| V1 | chip_sw_uart_tx_rx_alt_clk_freq | chip_sw_uart_tx_rx_alt_clk_freq | 29.343m | 8.444ms | 5 | 5 | 100.00 |
| chip_sw_uart_tx_rx_alt_clk_freq_low_speed | 22.112m | 8.556ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 217 | 220 | 98.64 | |||
| V2 | chip_pin_mux | chip_padctrl_attributes | 5.673m | 4.560ms | 10 | 10 | 100.00 |
| V2 | chip_padctrl_attributes | chip_padctrl_attributes | 5.673m | 4.560ms | 10 | 10 | 100.00 |
| V2 | chip_sw_sleep_pin_mio_dio_val | chip_sw_sleep_pin_mio_dio_val | 5.797m | 3.028ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_wake | chip_sw_sleep_pin_wake | 8.464m | 7.094ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pin_retention | chip_sw_sleep_pin_retention | 6.663m | 4.107ms | 3 | 3 | 100.00 |
| V2 | chip_sw_tap_strap_sampling | chip_tap_straps_dev | 1.572h | 60.000ms | 4 | 5 | 80.00 |
| chip_tap_straps_testunlock0 | 7.904m | 5.416ms | 3 | 5 | 60.00 | ||
| chip_tap_straps_rma | 10.711m | 6.717ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 25.192m | 12.959ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_pattgen_ios | chip_sw_pattgen_ios | 5.204m | 2.594ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sleep_pwm_pulses | chip_sw_sleep_pwm_pulses | 23.968m | 8.779ms | 3 | 3 | 100.00 |
| V2 | chip_sw_data_integrity | chip_sw_data_integrity_escalation | 13.610m | 6.845ms | 6 | 6 | 100.00 |
| V2 | chip_sw_instruction_integrity | chip_sw_data_integrity_escalation | 13.610m | 6.845ms | 6 | 6 | 100.00 |
| V2 | chip_sw_ast_clk_outputs | chip_sw_ast_clk_outputs | 18.633m | 7.246ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_clk_rst_inputs | chip_sw_ast_clk_rst_inputs | 53.055m | 20.478ms | 3 | 3 | 100.00 |
| V2 | chip_sw_ast_sys_clk_jitter | chip_sw_flash_ctrl_ops_jitter_en | 12.318m | 4.869ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 21.938m | 6.109ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.181h | 18.323ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 5.293m | 2.667ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 25.076m | 7.865ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 5.598m | 2.728ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 41.580m | 11.772ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 6.075m | 3.047ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 11.226m | 5.607ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 4.588m | 3.416ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_ast_usb_clk_calib | chip_sw_usb_ast_clk_calib | 5.126m | 3.106ms | 1 | 1 | 100.00 |
| V2 | chip_sw_sensor_ctrl_ast_alerts | chip_sw_sensor_ctrl_alert | 17.367m | 6.839ms | 5 | 5 | 100.00 |
| chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 11.172m | 5.639ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sensor_ctrl_ast_status | chip_sw_sensor_ctrl_status | 4.439m | 3.124ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup | 11.172m | 5.639ms | 3 | 3 | 100.00 |
| V2 | chip_sw_smoketest | chip_sw_flash_scrambling_smoketest | 4.417m | 3.277ms | 3 | 3 | 100.00 |
| chip_sw_aes_smoketest | 6.667m | 3.042ms | 3 | 3 | 100.00 | ||
| chip_sw_aon_timer_smoketest | 4.613m | 3.140ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_smoketest | 4.838m | 2.924ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_smoketest | 4.797m | 2.457ms | 3 | 3 | 100.00 | ||
| chip_sw_entropy_src_smoketest | 10.817m | 4.370ms | 3 | 3 | 100.00 | ||
| chip_sw_gpio_smoketest | 4.121m | 2.746ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_smoketest | 7.626m | 3.176ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_smoketest | 6.884m | 3.325ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_smoketest | 29.423m | 7.847ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 9.440m | 6.673ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_usbdev_smoketest | 7.279m | 6.115ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_plic_smoketest | 3.802m | 2.825ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_timer_smoketest | 4.613m | 2.718ms | 3 | 3 | 100.00 | ||
| chip_sw_rstmgr_smoketest | 4.997m | 2.686ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_smoketest | 6.323m | 3.671ms | 3 | 3 | 100.00 | ||
| chip_sw_uart_smoketest | 4.205m | 2.841ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_smoketest | chip_sw_otp_ctrl_smoketest | 6.412m | 3.553ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_functests | rom_keymgr_functest | 12.543m | 4.388ms | 3 | 3 | 100.00 |
| V2 | chip_sw_boot | chip_sw_uart_tx_rx_bootstrap | 4.345h | 78.870ms | 3 | 3 | 100.00 |
| V2 | chip_sw_secure_boot | rom_e2e_smoke | 1.170h | 15.403ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_raw_unlock | rom_raw_unlock | 4.897m | 5.716ms | 3 | 3 | 100.00 |
| V2 | chip_sw_power_idle_load | chip_sw_power_idle_load | 12.894m | 4.011ms | 3 | 3 | 100.00 |
| V2 | chip_sw_power_sleep_load | chip_sw_power_sleep_load | 14.470m | 10.835ms | 3 | 3 | 100.00 |
| V2 | chip_sw_exit_test_unlocked_bootstrap | chip_sw_exit_test_unlocked_bootstrap | 3.304h | 58.995ms | 3 | 3 | 100.00 |
| V2 | chip_sw_inject_scramble_seed | chip_sw_inject_scramble_seed | 3.308h | 64.084ms | 3 | 3 | 100.00 |
| V2 | tl_d_oob_addr_access | chip_tl_errors | 10.082m | 5.253ms | 30 | 30 | 100.00 |
| V2 | tl_d_illegal_access | chip_tl_errors | 10.082m | 5.253ms | 30 | 30 | 100.00 |
| V2 | tl_d_outstanding_access | chip_csr_aliasing | 2.817h | 69.077ms | 3 | 5 | 60.00 |
| chip_same_csr_outstanding | 1.210h | 30.954ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 8.069m | 8.054ms | 4 | 5 | 80.00 | ||
| chip_csr_rw | 11.977m | 5.335ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | chip_csr_aliasing | 2.817h | 69.077ms | 3 | 5 | 60.00 |
| chip_same_csr_outstanding | 1.210h | 30.954ms | 20 | 20 | 100.00 | ||
| chip_csr_hw_reset | 8.069m | 8.054ms | 4 | 5 | 80.00 | ||
| chip_csr_rw | 11.977m | 5.335ms | 20 | 20 | 100.00 | ||
| V2 | xbar_base_random_sequence | xbar_random | 1.818m | 2.597ms | 100 | 100 | 100.00 |
| V2 | xbar_random_delay | xbar_smoke_zero_delays | 8.550s | 60.102us | 100 | 100 | 100.00 |
| xbar_smoke_large_delays | 1.992m | 10.854ms | 100 | 100 | 100.00 | ||
| xbar_smoke_slow_rsp | 2.171m | 7.081ms | 100 | 100 | 100.00 | ||
| xbar_random_zero_delays | 1.100m | 553.872us | 100 | 100 | 100.00 | ||
| xbar_random_large_delays | 20.832m | 110.535ms | 100 | 100 | 100.00 | ||
| xbar_random_slow_rsp | 20.070m | 67.025ms | 100 | 100 | 100.00 | ||
| V2 | xbar_unmapped_address | xbar_unmapped_addr | 1.246m | 1.382ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 58.980s | 1.450ms | 100 | 100 | 100.00 | ||
| V2 | xbar_error_cases | xbar_error_random | 1.652m | 2.477ms | 100 | 100 | 100.00 |
| xbar_error_and_unmapped_addr | 58.980s | 1.450ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_access_same_device | xbar_access_same_device | 2.877m | 3.720ms | 100 | 100 | 100.00 |
| xbar_access_same_device_slow_rsp | 47.270m | 158.211ms | 100 | 100 | 100.00 | ||
| V2 | xbar_all_hosts_use_same_source_id | xbar_same_source | 1.583m | 2.743ms | 100 | 100 | 100.00 |
| V2 | xbar_stress_all | xbar_stress_all | 11.935m | 15.788ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_error | 13.513m | 18.399ms | 100 | 100 | 100.00 | ||
| V2 | xbar_stress_with_reset | xbar_stress_all_with_rand_reset | 21.384m | 9.650ms | 100 | 100 | 100.00 |
| xbar_stress_all_with_reset_error | 13.407m | 15.012ms | 100 | 100 | 100.00 | ||
| V2 | rom_e2e_smoke | rom_e2e_smoke | 1.170h | 15.403ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_output | rom_e2e_shutdown_output | 1.191h | 25.894ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_shutdown_exception_c | rom_e2e_shutdown_exception_c | 1.072h | 14.721ms | 3 | 3 | 100.00 |
| V2 | rom_e2e_boot_policy_valid | rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 | 47.370m | 11.338ms | 1 | 1 | 100.00 |
| rom_e2e_boot_policy_valid_a_good_b_good_dev | 1.033h | 15.328ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod | 1.144h | 15.604ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_prod_end | 1.151h | 14.817ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_good_rma | 1.403h | 14.725ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 | 51.881m | 12.017ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_dev | 1.077h | 15.211ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod | 1.086h | 15.065ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_prod_end | 1.357h | 14.783ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_good_b_bad_rma | 1.156h | 15.096ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 | 1.322h | 18.408ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_dev | 1.770h | 24.484ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod | 1.972h | 24.561ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_prod_end | 1.762h | 24.937ms | 1 | 1 | 100.00 | ||
| rom_e2e_boot_policy_valid_a_bad_b_good_rma | 1.827h | 22.911ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_sigverify_always | rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 | 1.249h | 17.954ms | 1 | 1 | 100.00 |
| rom_e2e_sigverify_always_a_bad_b_bad_dev | 1.972h | 23.047ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod | 2.096h | 24.289ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_prod_end | 1.888h | 23.916ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_bad_rma | 2.035h | 21.972ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 | 48.395m | 11.273ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_dev | 57.617m | 14.850ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod | 58.477m | 14.891ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_prod_end | 52.615m | 14.270ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_bad_b_nothing_rma | 1.005h | 14.189ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 | 49.719m | 11.523ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_dev | 1.076h | 14.104ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod | 1.141h | 14.856ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_prod_end | 59.543m | 14.318ms | 1 | 1 | 100.00 | ||
| rom_e2e_sigverify_always_a_nothing_b_bad_rma | 59.885m | 14.068ms | 1 | 1 | 100.00 | ||
| V2 | rom_e2e_asm_init | rom_e2e_asm_init_test_unlocked0 | 55.596m | 10.693ms | 3 | 3 | 100.00 |
| rom_e2e_asm_init_dev | 1.235h | 16.181ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_prod | 1.244h | 14.872ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_prod_end | 1.261h | 15.642ms | 3 | 3 | 100.00 | ||
| rom_e2e_asm_init_rma | 1.296h | 15.154ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_keymgr_init | rom_e2e_keymgr_init_rom_ext_meas | 1.348h | 15.561ms | 3 | 3 | 100.00 |
| rom_e2e_keymgr_init_rom_ext_no_meas | 1.187h | 14.930ms | 3 | 3 | 100.00 | ||
| rom_e2e_keymgr_init_rom_ext_invalid_meas | 1.084h | 15.284ms | 3 | 3 | 100.00 | ||
| V2 | rom_e2e_static_critical | rom_e2e_static_critical | 1.255h | 16.828ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_enc | chip_sw_aes_enc | 5.646m | 3.165ms | 3 | 3 | 100.00 |
| chip_sw_aes_enc_jitter_en | 5.293m | 2.667ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_aes_multi_block | chip_sw_aes_multi_block | 0 | 0 | -- | ||
| V2 | chip_sw_aes_interrupt_encryption | chip_sw_aes_interrupt_encryption | 0 | 0 | -- | ||
| V2 | chip_sw_aes_entropy | chip_sw_aes_entropy | 4.977m | 2.697ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_prng_reseed | chip_sw_aes_prng_reseed | 0 | 0 | -- | ||
| V2 | chip_sw_aes_force_prng_reseed | chip_sw_aes_force_prng_reseed | 0 | 0 | -- | ||
| V2 | chip_sw_aes_idle | chip_sw_aes_idle | 6.183m | 3.091ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aes_sideload | chip_sw_keymgr_sideload_aes | 26.583m | 7.653ms | 2 | 3 | 66.67 |
| V2 | chip_sw_adc_ctrl_debug_cable_irq | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 11.562m | 17.804ms | 3 | 3 | 100.00 |
| V2 | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 11.562m | 17.804ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wakeup_irq | chip_sw_aon_timer_irq | 7.777m | 3.760ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wakeup | chip_sw_pwrmgr_smoketest | 9.440m | 6.673ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bark_irq | chip_sw_aon_timer_irq | 7.777m | 3.760ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 16.105m | 9.778ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_bite_reset | chip_sw_aon_timer_wdog_bite_reset | 16.105m | 9.778ms | 3 | 3 | 100.00 |
| V2 | chip_sw_aon_timer_sleep_wdog_sleep_pause | chip_sw_aon_timer_sleep_wdog_sleep_pause | 10.000m | 6.706ms | 5 | 5 | 100.00 |
| V2 | chip_sw_aon_timer_wdog_lc_escalate | chip_sw_aon_timer_wdog_lc_escalate | 10.606m | 6.141ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_idle_trans | chip_sw_otbn_randomness | 18.892m | 5.510ms | 3 | 3 | 100.00 |
| chip_sw_aes_idle | 6.183m | 3.091ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_idle | 5.469m | 3.248ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_idle | 4.734m | 2.877ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_trans | chip_sw_clkmgr_off_aes_trans | 11.271m | 5.683ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_off_hmac_trans | 11.224m | 6.007ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_kmac_trans | 10.672m | 4.721ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_off_otbn_trans | 8.263m | 4.297ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_off_peri | chip_sw_clkmgr_off_peri | 30.536m | 10.387ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_div | chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 12.868m | 4.435ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 10.874m | 5.525ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 12.090m | 4.376ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 12.246m | 5.096ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 11.659m | 4.321ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 13.072m | 4.410ms | 3 | 3 | 100.00 | ||
| chip_sw_ast_clk_outputs | 18.633m | 7.246ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_external_clk_src_for_lc | chip_sw_clkmgr_external_clk_src_for_lc | 10.638m | 6.431ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_external_clk_src_for_sw | chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 12.090m | 4.376ms | 3 | 3 | 100.00 |
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 12.246m | 5.096ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_jitter | chip_sw_flash_ctrl_ops_jitter_en | 12.318m | 4.869ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 21.938m | 6.109ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en | 1.181h | 18.323ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en | 5.293m | 2.667ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs_jitter | 25.076m | 7.865ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en | 5.598m | 2.728ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en | 41.580m | 11.772ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 6.075m | 3.047ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 11.226m | 5.607ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_jitter | 4.588m | 3.416ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_extended_range | chip_sw_clkmgr_jitter_reduced_freq | 4.027m | 3.355ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en_reduced_freq | 13.036m | 4.340ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_ctrl_access_jitter_en_reduced_freq | 23.987m | 7.142ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq | 1.254h | 24.278ms | 3 | 3 | 100.00 | ||
| chip_sw_aes_enc_jitter_en_reduced_freq | 5.092m | 3.437ms | 3 | 3 | 100.00 | ||
| chip_sw_hmac_enc_jitter_en_reduced_freq | 4.891m | 3.721ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation_jitter_en_reduced_freq | 36.704m | 12.754ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en_reduced_freq | 5.699m | 3.236ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq | 11.855m | 5.422ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_init_reduced_freq | 41.635m | 19.479ms | 3 | 3 | 100.00 | ||
| chip_sw_csrng_edn_concurrency_reduced_freq | 3.593h | 89.968ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_clkmgr_deep_sleep_frequency | chip_sw_ast_clk_outputs | 18.633m | 7.246ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_sleep_frequency | chip_sw_clkmgr_sleep_frequency | 11.919m | 4.375ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_reset_frequency | chip_sw_clkmgr_reset_frequency | 8.587m | 3.732ms | 3 | 3 | 100.00 |
| V2 | chip_sw_clkmgr_escalation_reset | chip_sw_all_escalation_resets | 16.382m | 5.995ms | 98 | 100 | 98.00 |
| V2 | chip_sw_clkmgr_alert_handler_clock_enables | chip_sw_alert_handler_lpg_clkoff | 28.500m | 8.054ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_edn_cmd | chip_sw_entropy_src_csrng | 35.107m | 7.965ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_fuse_en_sw_app_read | chip_sw_csrng_fuse_en_sw_app_read_test | 10.216m | 5.530ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_lc_hw_debug_en | chip_sw_csrng_lc_hw_debug_en_test | 13.167m | 6.693ms | 3 | 3 | 100.00 |
| V2 | chip_sw_csrng_known_answer_tests | chip_sw_csrng_kat_test | 5.237m | 3.148ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 23.207m | 8.347ms | 3 | 3 | 100.00 |
| chip_sw_sysrst_ctrl_reset | 32.069m | 24.746ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sysrst_ctrl_inputs | chip_sw_sysrst_ctrl_inputs | 7.518m | 4.013ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_outputs | chip_sw_sysrst_ctrl_outputs | 7.576m | 4.410ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_in_irq | chip_sw_sysrst_ctrl_in_irq | 11.441m | 4.760ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_wakeup | chip_sw_sysrst_ctrl_reset | 32.069m | 24.746ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_sleep_reset | chip_sw_sysrst_ctrl_reset | 32.069m | 24.746ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ec_rst_l | chip_sw_sysrst_ctrl_ec_rst_l | 59.342m | 20.367ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_flash_wp_l | chip_sw_sysrst_ctrl_ec_rst_l | 59.342m | 20.367ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sysrst_ctrl_ulp_z3_wakeup | chip_sw_sysrst_ctrl_ulp_z3_wakeup | 7.763m | 5.220ms | 3 | 3 | 100.00 |
| chip_sw_adc_ctrl_sleep_debug_cable_wakeup | 11.562m | 17.804ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_edn_entropy_reqs | chip_sw_csrng_edn_concurrency | 1.899h | 28.750ms | 10 | 10 | 100.00 |
| chip_sw_entropy_src_ast_rng_req | 3.635m | 2.410ms | 3 | 3 | 100.00 | ||
| chip_sw_edn_entropy_reqs | 24.733m | 6.482ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_entropy_src_ast_rng_req | chip_sw_entropy_src_ast_rng_req | 3.635m | 2.410ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_csrng | chip_sw_entropy_src_csrng | 35.107m | 7.965ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fuse_en_fw_read | chip_sw_entropy_src_fuse_en_fw_read_test | 0 | 0 | -- | ||
| V2 | chip_sw_entropy_src_known_answer_tests | chip_sw_entropy_src_kat_test | 4.329m | 2.576ms | 3 | 3 | 100.00 |
| V2 | chip_sw_entropy_src_fw_observe_many_contiguous | chip_sw_entropy_src_fw_observe_many_contiguous | 0 | 0 | -- | ||
| V2 | chip_sw_entropy_src_fw_extract_and_insert | chip_sw_entropy_src_fw_extract_and_insert | 0 | 0 | -- | ||
| V2 | chip_sw_flash_init | chip_sw_flash_init | 40.509m | 19.890ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_host_access | chip_sw_flash_ctrl_access | 17.793m | 5.832ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_access_jitter_en | 21.938m | 6.109ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_ctrl_ops | chip_sw_flash_ctrl_ops | 11.824m | 4.489ms | 3 | 3 | 100.00 |
| chip_sw_flash_ctrl_ops_jitter_en | 12.318m | 4.869ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_flash_rma_unlocked | chip_sw_flash_rma_unlocked | 1.488h | 42.929ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_scramble | chip_sw_flash_init | 40.509m | 19.890ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_idle_low_power | chip_sw_flash_ctrl_idle_low_power | 6.481m | 3.906ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_keymgr_seeds | chip_sw_keymgr_key_derivation | 50.735m | 12.871ms | 2 | 3 | 66.67 |
| V2 | chip_sw_flash_lc_creator_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 11.042m | 6.066ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_creator_seed_wipe_on_rma | chip_sw_flash_rma_unlocked | 1.488h | 42.929ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_owner_seed_sw_rw_en | chip_sw_flash_ctrl_lc_rw_en | 11.042m | 6.066ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 11.042m | 6.066ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_iso_part_sw_wr_en | chip_sw_flash_ctrl_lc_rw_en | 11.042m | 6.066ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_seed_hw_rd_en | chip_sw_flash_ctrl_lc_rw_en | 11.042m | 6.066ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_lc_escalate_en | chip_sw_all_escalation_resets | 16.382m | 5.995ms | 98 | 100 | 98.00 |
| V2 | chip_sw_flash_prim_tl_access | chip_prim_tl_access | 6.651m | 7.635ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_clock_freqs | chip_sw_flash_ctrl_clock_freqs | 22.079m | 5.766ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_escalation_reset | chip_sw_flash_crash_alert | 12.808m | 5.418ms | 3 | 3 | 100.00 |
| V2 | chip_sw_flash_ctrl_write_clear | chip_sw_flash_crash_alert | 12.808m | 5.418ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_enc | chip_sw_hmac_enc | 6.528m | 3.535ms | 3 | 3 | 100.00 |
| chip_sw_hmac_enc_jitter_en | 5.598m | 2.728ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_hmac_idle | chip_sw_hmac_enc_idle | 5.469m | 3.248ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_all_configurations | chip_sw_hmac_oneshot | 6.395m | 2.804ms | 3 | 3 | 100.00 |
| V2 | chip_sw_hmac_multistream_mode | chip_sw_hmac_multistream | 34.318m | 7.489ms | 3 | 3 | 100.00 |
| V2 | chip_sw_i2c_host_tx_rx | chip_sw_i2c_host_tx_rx | 14.681m | 5.639ms | 3 | 3 | 100.00 |
| chip_sw_i2c_host_tx_rx_idx1 | 15.556m | 5.004ms | 3 | 3 | 100.00 | ||
| chip_sw_i2c_host_tx_rx_idx2 | 15.821m | 5.275ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_i2c_device_tx_rx | chip_sw_i2c_device_tx_rx | 12.854m | 4.683ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_key_derivation | chip_sw_keymgr_key_derivation | 50.735m | 12.871ms | 2 | 3 | 66.67 |
| chip_sw_keymgr_key_derivation_jitter_en | 41.580m | 11.772ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_keymgr_sideload_kmac | chip_sw_keymgr_sideload_kmac | 39.574m | 11.493ms | 3 | 3 | 100.00 |
| V2 | chip_sw_keymgr_sideload_aes | chip_sw_keymgr_sideload_aes | 26.583m | 7.653ms | 2 | 3 | 66.67 |
| V2 | chip_sw_keymgr_sideload_otbn | chip_sw_keymgr_sideload_otbn | 1.280h | 15.675ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_enc | chip_sw_kmac_mode_cshake | 5.180m | 3.524ms | 3 | 3 | 100.00 |
| chip_sw_kmac_mode_kmac | 5.585m | 3.452ms | 3 | 3 | 100.00 | ||
| chip_sw_kmac_mode_kmac_jitter_en | 6.075m | 3.047ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_kmac_app_keymgr | chip_sw_keymgr_key_derivation | 50.735m | 12.871ms | 2 | 3 | 66.67 |
| V2 | chip_sw_kmac_app_lc | chip_sw_lc_ctrl_transition | 18.259m | 10.004ms | 15 | 15 | 100.00 |
| V2 | chip_sw_kmac_app_rom | chip_sw_kmac_app_rom | 4.890m | 3.139ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_entropy | chip_sw_kmac_entropy | 4.711m | 2.853ms | 3 | 3 | 100.00 |
| V2 | chip_sw_kmac_idle | chip_sw_kmac_idle | 4.734m | 2.877ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_alert_handler_escalation | chip_sw_alert_handler_escalation | 10.480m | 6.031ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_jtag_access | chip_tap_straps_dev | 1.572h | 60.000ms | 4 | 5 | 80.00 |
| chip_tap_straps_rma | 10.711m | 6.717ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 25.192m | 12.959ms | 5 | 5 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_otp_hw_cfg0 | chip_sw_lc_ctrl_otp_hw_cfg0 | 5.750m | 3.756ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_init | chip_sw_lc_ctrl_transition | 18.259m | 10.004ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_transitions | chip_sw_lc_ctrl_transition | 18.259m | 10.004ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_kmac_req | chip_sw_lc_ctrl_transition | 18.259m | 10.004ms | 15 | 15 | 100.00 |
| V2 | chip_sw_lc_ctrl_key_div | chip_sw_keymgr_key_derivation_prod | 44.110m | 9.869ms | 3 | 3 | 100.00 |
| V2 | chip_sw_lc_ctrl_broadcast | chip_sw_flash_ctrl_lc_rw_en | 11.042m | 6.066ms | 3 | 3 | 100.00 |
| chip_sw_flash_rma_unlocked | 1.488h | 42.929ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 12.531m | 4.682ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_dev | 28.368m | 9.093ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 23.776m | 9.255ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 23.378m | 7.596ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 18.259m | 10.004ms | 15 | 15 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 50.735m | 12.871ms | 2 | 3 | 66.67 | ||
| chip_sw_rom_ctrl_integrity_check | 10.452m | 9.191ms | 3 | 3 | 100.00 | ||
| chip_sw_sram_ctrl_execution_main | 21.314m | 10.667ms | 3 | 3 | 100.00 | ||
| chip_prim_tl_access | 6.651m | 7.635ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_lc | 10.638m | 6.431ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 | 12.868m | 4.435ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 | 10.874m | 5.525ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_dev | 12.090m | 4.376ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_dev | 12.246m | 5.096ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_fast_rma | 11.659m | 4.321ms | 3 | 3 | 100.00 | ||
| chip_sw_clkmgr_external_clk_src_for_sw_slow_rma | 13.072m | 4.410ms | 3 | 3 | 100.00 | ||
| chip_tap_straps_dev | 1.572h | 60.000ms | 4 | 5 | 80.00 | ||
| chip_tap_straps_rma | 10.711m | 6.717ms | 5 | 5 | 100.00 | ||
| chip_tap_straps_prod | 25.192m | 12.959ms | 5 | 5 | 100.00 | ||
| chip_rv_dm_lc_disabled | 10.254m | 11.850ms | 3 | 3 | 100.00 | ||
| V2 | chip_lc_scrap | chip_sw_lc_ctrl_rma_to_scrap | 3.222m | 3.514ms | 1 | 1 | 100.00 |
| chip_sw_lc_ctrl_raw_to_scrap | 2.633m | 2.957ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_test_locked0_to_scrap | 2.864m | 3.358ms | 1 | 1 | 100.00 | ||
| chip_sw_lc_ctrl_rand_to_scrap | 5.255m | 3.860ms | 3 | 3 | 100.00 | ||
| V2 | chip_lc_test_locked | chip_sw_lc_walkthrough_testunlocks | 42.277m | 30.634ms | 3 | 3 | 100.00 |
| chip_rv_dm_lc_disabled | 10.254m | 11.850ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_walkthrough | chip_sw_lc_walkthrough_dev | 1.757h | 49.629ms | 3 | 3 | 100.00 |
| chip_sw_lc_walkthrough_prod | 1.765h | 49.944ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_prodend | 21.430m | 11.233ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_rma | 1.755h | 49.508ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_walkthrough_testunlocks | 42.277m | 30.634ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_lc_ctrl_volatile_raw_unlock | chip_sw_lc_ctrl_volatile_raw_unlock | 2.290m | 2.418ms | 3 | 3 | 100.00 |
| chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz | 2.325m | 3.043ms | 3 | 3 | 100.00 | ||
| rom_volatile_raw_unlock | 2.169m | 2.356ms | 3 | 3 | 100.00 | ||
| V2 | chip_otp_ctrl_init | chip_sw_lc_ctrl_transition | 18.259m | 10.004ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_keys | chip_sw_flash_init | 40.509m | 19.890ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 10.054m | 3.771ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 50.735m | 12.871ms | 2 | 3 | 66.67 | ||
| chip_sw_sram_ctrl_scrambled_access | 14.177m | 6.103ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 5.372m | 3.266ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_entropy | chip_sw_flash_init | 40.509m | 19.890ms | 3 | 3 | 100.00 |
| chip_sw_otbn_mem_scramble | 10.054m | 3.771ms | 3 | 3 | 100.00 | ||
| chip_sw_keymgr_key_derivation | 50.735m | 12.871ms | 2 | 3 | 66.67 | ||
| chip_sw_sram_ctrl_scrambled_access | 14.177m | 6.103ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_icache_invalidate | 5.372m | 3.266ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_ctrl_program | chip_sw_lc_ctrl_transition | 18.259m | 10.004ms | 15 | 15 | 100.00 |
| V2 | chip_sw_otp_ctrl_program_error | chip_sw_lc_ctrl_program_error | 10.180m | 5.926ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_hw_cfg0 | chip_sw_lc_ctrl_otp_hw_cfg0 | 5.750m | 3.756ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_lc_signals | chip_sw_otp_ctrl_lc_signals_test_unlocked0 | 12.531m | 4.682ms | 3 | 3 | 100.00 |
| chip_sw_otp_ctrl_lc_signals_dev | 28.368m | 9.093ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_prod | 23.776m | 9.255ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_lc_signals_rma | 23.378m | 7.596ms | 3 | 3 | 100.00 | ||
| chip_sw_lc_ctrl_transition | 18.259m | 10.004ms | 15 | 15 | 100.00 | ||
| chip_prim_tl_access | 6.651m | 7.635ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_otp_prim_tl_access | chip_prim_tl_access | 6.651m | 7.635ms | 3 | 3 | 100.00 |
| V2 | chip_sw_otp_ctrl_dai_lock | chip_sw_otp_ctrl_dai_lock | 1.551h | 28.482ms | 1 | 1 | 100.00 |
| V2 | chip_sw_pwrmgr_external_full_reset | chip_sw_pwrmgr_full_aon_reset | 11.248m | 9.591ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_wake_ups | chip_sw_pwrmgr_random_sleep_all_wake_ups | 34.375m | 21.346ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_all_wake_ups | chip_sw_pwrmgr_normal_sleep_all_wake_ups | 9.051m | 7.476ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_por_reset | chip_sw_pwrmgr_deep_sleep_por_reset | 17.389m | 8.659ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_normal_sleep_por_reset | chip_sw_pwrmgr_normal_sleep_por_reset | 9.478m | 5.265ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_wake_ups | chip_sw_pwrmgr_deep_sleep_all_wake_ups | 35.062m | 26.512ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | chip_sw_pwrmgr_deep_sleep_all_reset_reqs | 30.713m | 15.938ms | 3 | 3 | 100.00 |
| chip_sw_aon_timer_wdog_bite_reset | 16.105m | 9.778ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | chip_sw_pwrmgr_normal_sleep_all_reset_reqs | 27.436m | 11.599ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_wdog_reset | chip_sw_pwrmgr_wdog_reset | 11.640m | 5.090ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_aon_power_glitch_reset | chip_sw_pwrmgr_full_aon_reset | 11.248m | 9.591ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_main_power_glitch_reset | chip_sw_pwrmgr_main_power_glitch_reset | 11.651m | 4.007ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_power_glitch_reset | chip_sw_pwrmgr_random_sleep_power_glitch_reset | 1.091h | 41.848ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | chip_sw_pwrmgr_deep_sleep_power_glitch_reset | 9.343m | 7.673ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_power_glitch_reset | chip_sw_pwrmgr_sleep_power_glitch_reset | 9.575m | 5.242ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_random_sleep_all_reset_reqs | chip_sw_pwrmgr_random_sleep_all_reset_reqs | 55.025m | 29.135ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sysrst_ctrl_reset | chip_sw_pwrmgr_sysrst_ctrl_reset | 23.207m | 8.347ms | 3 | 3 | 100.00 |
| chip_sw_pwrmgr_all_reset_reqs | 31.456m | 12.991ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_pwrmgr_b2b_sleep_reset_req | chip_sw_pwrmgr_b2b_sleep_reset_req | 47.391m | 27.467ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_sleep_disabled | chip_sw_pwrmgr_sleep_disabled | 6.017m | 3.629ms | 3 | 3 | 100.00 |
| V2 | chip_sw_pwrmgr_escalation_reset | chip_sw_all_escalation_resets | 16.382m | 5.995ms | 98 | 100 | 98.00 |
| V2 | chip_sw_rom_access | chip_sw_rom_ctrl_integrity_check | 10.452m | 9.191ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rom_ctrl_integrity_check | chip_sw_rom_ctrl_integrity_check | 10.452m | 9.191ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_non_sys_reset_info | chip_sw_pwrmgr_all_reset_reqs | 31.456m | 12.991ms | 3 | 3 | 100.00 |
| chip_sw_pwrmgr_random_sleep_all_reset_reqs | 55.025m | 29.135ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_wdog_reset | 11.640m | 5.090ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_smoketest | 9.440m | 6.673ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_rstmgr_sys_reset_info | chip_rv_dm_ndm_reset_req | 8.457m | 3.909ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_cpu_info | chip_sw_rstmgr_cpu_info | 12.018m | 5.472ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_req_reset | chip_sw_rstmgr_sw_req | 8.792m | 5.001ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_alert_info | chip_sw_rstmgr_alert_info | 35.327m | 11.781ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_sw_rst | chip_sw_rstmgr_sw_rst | 4.853m | 3.557ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rstmgr_escalation_reset | chip_sw_all_escalation_resets | 16.382m | 5.995ms | 98 | 100 | 98.00 |
| V2 | chip_sw_rstmgr_alert_handler_reset_enables | chip_sw_alert_handler_lpg_reset_toggle | 32.747m | 7.550ms | 3 | 3 | 100.00 |
| V2 | chip_sw_plic_all_irqs | chip_plic_all_irqs_0 | 20.974m | 6.158ms | 3 | 3 | 100.00 |
| chip_plic_all_irqs_10 | 11.229m | 4.209ms | 3 | 3 | 100.00 | ||
| chip_plic_all_irqs_20 | 14.986m | 5.088ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_plic_sw_irq | chip_sw_plic_sw_irq | 5.484m | 3.522ms | 3 | 3 | 100.00 |
| V2 | chip_sw_timer | chip_sw_rv_timer_irq | 6.560m | 3.307ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_flash_mode | rom_e2e_smoke | 1.170h | 15.403ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through | chip_sw_spi_device_pass_through | 13.894m | 6.658ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_pass_through_collision | chip_sw_spi_device_pass_through_collision | 9.547m | 5.079ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_device_tpm | chip_sw_spi_device_tpm | 5.934m | 3.542ms | 3 | 3 | 100.00 |
| V2 | chip_sw_spi_host_tx_rx | chip_sw_spi_host_tx_rx | 6.021m | 3.068ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_scrambled_access | chip_sw_sram_ctrl_scrambled_access | 14.177m | 6.103ms | 3 | 3 | 100.00 |
| chip_sw_sram_ctrl_scrambled_access_jitter_en | 11.226m | 5.607ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sleep_sram_ret_contents | chip_sw_sleep_sram_ret_contents_no_scramble | 13.375m | 6.869ms | 3 | 3 | 100.00 |
| chip_sw_sleep_sram_ret_contents_scramble | 15.841m | 7.782ms | 3 | 3 | 100.00 | ||
| V2 | chip_sw_sram_execution | chip_sw_sram_ctrl_execution_main | 21.314m | 10.667ms | 3 | 3 | 100.00 |
| V2 | chip_sw_sram_lc_escalation | chip_sw_all_escalation_resets | 16.382m | 5.995ms | 98 | 100 | 98.00 |
| chip_sw_data_integrity_escalation | 13.610m | 6.845ms | 6 | 6 | 100.00 | ||
| V2 | chip_sw_usbdev_mem | chip_sw_usbdev_mem | 0 | 0 | -- | ||
| V2 | chip_sw_usbdev_vbus | chip_sw_usbdev_vbus | 3.421m | 2.533ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_pullup | chip_sw_usbdev_pullup | 4.377m | 3.061ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_aon_pullup | chip_sw_usbdev_aon_pullup | 9.975m | 4.266ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_sof | chip_sw_usbdev_sof | 0 | 0 | -- | ||
| V2 | chip_sw_usbdev_setup_rx | chip_sw_usbdev_setuprx | 9.451m | 3.860ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_config_host | chip_sw_usbdev_config_host | 36.560m | 7.960ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_pincfg | chip_sw_usbdev_pincfg | 1.902h | 31.568ms | 1 | 1 | 100.00 |
| V2 | chip_sw_usbdev_tx_rx | chip_sw_usbdev_dpi | 48.115m | 12.055ms | 1 | 1 | 100.00 |
| V2 | chip_sw_alert_handler_alerts | chip_sw_alert_test | 6.668m | 3.452ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalations | chip_sw_alert_handler_escalation | 10.480m | 6.031ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_escalation_nmi_reset | chip_sw_alert_handler_escalation_nmi_reset | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_escalation_methods | chip_sw_alert_handler_escalation_methods | 0 | 0 | -- | ||
| V2 | chip_sw_all_escalation_resets | chip_sw_all_escalation_resets | 16.382m | 5.995ms | 98 | 100 | 98.00 |
| V2 | chip_sw_alert_handler_irqs | chip_plic_all_irqs | 0 | 0 | -- | ||
| V2 | chip_sw_alert_handler_entropy | chip_sw_alert_handler_entropy | 7.869m | 4.136ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_crashdump | chip_sw_rstmgr_alert_info | 35.327m | 11.781ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_timeout | chip_sw_alert_handler_ping_timeout | 7.653m | 3.584ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_alerts | chip_sw_alert_handler_lpg_sleep_mode_alerts | 10.365m | 3.891ms | 86 | 90 | 95.56 |
| V2 | chip_sw_alert_handler_lpg_sleep_mode_pings | chip_sw_alert_handler_lpg_sleep_mode_pings | 22.922m | 11.478ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_clock_off | chip_sw_alert_handler_lpg_clkoff | 28.500m | 8.054ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_lpg_reset_toggle | chip_sw_alert_handler_lpg_reset_toggle | 32.747m | 7.550ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_ping_ok | chip_sw_alert_handler_ping_ok | 24.375m | 7.731ms | 3 | 3 | 100.00 |
| V2 | chip_sw_alert_handler_reverse_ping_in_deep_sleep | chip_sw_alert_handler_reverse_ping_in_deep_sleep | 3.661h | 255.176ms | 1 | 3 | 33.33 |
| V2 | chip_jtag_csr_rw | chip_jtag_csr_rw | 44.352m | 18.375ms | 3 | 3 | 100.00 |
| V2 | chip_jtag_mem_access | chip_jtag_mem_access | 26.865m | 13.769ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_ndm_reset_req | chip_rv_dm_ndm_reset_req | 8.457m | 3.909ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | chip_sw_rv_dm_ndm_reset_req_when_cpu_halted | 10.047m | 4.548ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_access_after_wakeup | chip_sw_rv_dm_access_after_wakeup | 10.096m | 5.406ms | 3 | 3 | 100.00 |
| V2 | chip_sw_rv_dm_jtag_tap_sel | chip_tap_straps_rma | 10.711m | 6.717ms | 5 | 5 | 100.00 |
| V2 | chip_rv_dm_lc_disabled | chip_rv_dm_lc_disabled | 10.254m | 11.850ms | 3 | 3 | 100.00 |
| V2 | chip_rv_dm_jtag | chip_rv_dm_jtag | 0 | 0 | -- | ||
| V2 | chip_rv_dm_dtm | chip_rv_dm_dtm | 0 | 0 | -- | ||
| V2 | chip_rv_dm_control_status | chip_rv_dm_control_status | 0 | 0 | -- | ||
| V2 | TOTAL | 2631 | 2644 | 99.51 | |||
| V2S | chip_sw_aes_masking_off | chip_sw_aes_masking_off | 6.537m | 3.403ms | 3 | 3 | 100.00 |
| V2S | TOTAL | 3 | 3 | 100.00 | |||
| V3 | chip_sw_usb_suspend | chip_sw_usb_suspend | 0 | 0 | -- | ||
| V3 | chip_sw_coremark | chip_sw_coremark | 3.836h | 72.035ms | 1 | 1 | 100.00 |
| V3 | chip_sw_power_max_load | chip_sw_power_virus | 31.767m | 6.032ms | 3 | 3 | 100.00 |
| V3 | rom_e2e_debug | rom_e2e_jtag_debug_test_unlocked0 | 36.088m | 11.495ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 33.745m | 11.144ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 33.613m | 11.002ms | 1 | 1 | 100.00 | ||
| V3 | rom_e2e_jtag_inject | rom_e2e_jtag_inject_test_unlocked0 | 47.680m | 31.970ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_inject_dev | 29.508m | 25.869ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_inject_rma | 54.979m | 29.858ms | 1 | 1 | 100.00 | ||
| V3 | rom_bootstrap_rma | rom_bootstrap_rma | 0 | 0 | -- | ||
| V3 | rom_e2e_weak_straps | rom_e2e_weak_straps | 0 | 0 | -- | ||
| V3 | rom_e2e_self_hash | rom_e2e_self_hash | 1.901h | 26.107ms | 3 | 3 | 100.00 |
| V3 | manuf_cp_unlock_raw | manuf_cp_unlock_raw | 0 | 0 | -- | ||
| V3 | manuf_scrap | manuf_scrap | 0 | 0 | -- | ||
| V3 | manuf_cp_yield_test | manuf_cp_yield_test | 0 | 0 | -- | ||
| V3 | manuf_cp_ast_test_execution | manuf_cp_ast_test_execution | 0 | 0 | -- | ||
| V3 | manuf_cp_device_info_flash_wr | manuf_cp_device_info_flash_wr | 0 | 0 | -- | ||
| V3 | manuf_cp_test_lock | manuf_cp_test_lock | 0 | 0 | -- | ||
| V3 | manuf_ft_exit_token | manuf_ft_exit_token | 0 | 0 | -- | ||
| V3 | manuf_ft_sku_individualization_preop | manuf_ft_sku_individualization_preop | 0 | 0 | -- | ||
| V3 | manuf_ft_sku_individualization | manuf_ft_sku_individualization | 0 | 0 | -- | ||
| V3 | manuf_ft_provision_rma_token_and_personalization | manuf_ft_provision_rma_token_and_personalization | 0 | 0 | -- | ||
| V3 | manuf_ft_load_transport_image | manuf_ft_load_transport_image | 0 | 0 | -- | ||
| V3 | manuf_ft_load_certificates | manuf_ft_load_certificates | 0 | 0 | -- | ||
| V3 | manuf_ft_eom | manuf_ft_eom | 0 | 0 | -- | ||
| V3 | manuf_rma_entry | manuf_rma_entry | 0 | 0 | -- | ||
| V3 | manuf_sram_program_crc_functest | manuf_sram_program_crc_functest | 0 | 0 | -- | ||
| V3 | chip_sw_adc_ctrl_normal | chip_sw_adc_ctrl_normal | 0 | 0 | -- | ||
| V3 | chip_sw_adc_ctrl_oneshot | chip_sw_adc_ctrl_oneshot | 0 | 0 | -- | ||
| V3 | chip_sw_clkmgr_jitter_cycle_measurements | chip_sw_clkmgr_jitter_frequency | 7.886m | 2.767ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_boot_mode | chip_sw_edn_boot_mode | 9.930m | 3.155ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_auto_mode | chip_sw_edn_auto_mode | 32.473m | 6.000ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_sw_mode | chip_sw_edn_sw_mode | 35.473m | 9.733ms | 3 | 3 | 100.00 |
| V3 | chip_sw_edn_kat | chip_sw_edn_kat | 12.999m | 3.158ms | 3 | 3 | 100.00 |
| V3 | chip_sw_entropy_src_bypass_mode_health_tests | chip_sw_entropy_src_bypass_mode_health_tests | 0 | 0 | -- | ||
| V3 | chip_sw_entropy_src_fips_mode_health_tests | chip_sw_entropy_src_fips_mode_health_tests | 0 | 0 | -- | ||
| V3 | chip_sw_entropy_src_validation | chip_sw_entropy_src_validation | 0 | 0 | -- | ||
| V3 | chip_sw_flash_memory_protection | chip_sw_flash_ctrl_mem_protection | 19.587m | 5.903ms | 3 | 3 | 100.00 |
| V3 | chip_sw_hmac_sha2_stress | chip_sw_hmac_sha2_stress | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_stress | chip_sw_hmac_stress | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_endianness | chip_sw_hmac_endianness | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_secure_wipe | chip_sw_hmac_secure_wipe | 0 | 0 | -- | ||
| V3 | chip_sw_hmac_error_conditions | chip_sw_hmac_error_conditions | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_speed | chip_sw_i2c_speed | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_override | chip_sw_i2c_override | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_clockstretching | chip_sw_i2c_clockstretching | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_nack | chip_sw_i2c_nack | 0 | 0 | -- | ||
| V3 | chip_sw_i2c_repeatedstart | chip_sw_i2c_repeatedstart | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_sideload_kmac_error | chip_sw_keymgr_sideload_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_derive_attestation | chip_sw_keymgr_derive_attestation | 0 | 0 | -- | ||
| V3 | chip_sw_keymgr_derive_sealing | chip_sw_keymgr_derive_sealing | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_sha3_stress | chip_sw_kmac_sha3_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_shake_stress | chip_sw_kmac_shake_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_cshake_stress | chip_sw_kmac_cshake_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_kmac_stress | chip_sw_kmac_kmac_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_kmac_key_sideload | chip_sw_kmac_kmac_key_sideload | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_endianess | chip_sw_kmac_endianess | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_entropy_stress | chip_sw_kmac_entropy_stress | 0 | 0 | -- | ||
| V3 | chip_sw_kmac_error_conditions | chip_sw_kmac_error_conditions | 0 | 0 | -- | ||
| V3 | chip_sw_lc_ctrl_kmac_error | chip_sw_lc_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_lc_ctrl_debug_access | chip_sw_lc_ctrl_debug_access | 0 | 0 | -- | ||
| V3 | chip_sw_otp_ctrl_vendor_test_csr_access | chip_sw_otp_ctrl_vendor_test_csr_access | 5.610m | 2.811ms | 3 | 3 | 100.00 |
| V3 | chip_sw_otp_ctrl_escalation | chip_sw_otp_ctrl_escalation | 10.592m | 6.067ms | 1 | 1 | 100.00 |
| V3 | otp_ctrl_calibration | otp_ctrl_calibration | 0 | 0 | -- | ||
| V3 | otp_ctrl_partition_access_locked | otp_ctrl_partition_access_locked | 0 | 0 | -- | ||
| V3 | otp_ctrl_check_timeout | otp_ctrl_check_timeout | 0 | 0 | -- | ||
| V3 | chip_sw_sensor_ctrl_deep_sleep_wake_up | chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up | 8.001m | 6.835ms | 3 | 3 | 100.00 |
| V3 | chip_sw_pwrmgr_usb_clk_disabled_when_active | chip_sw_pwrmgr_usb_clk_disabled_when_active | 7.393m | 4.533ms | 3 | 3 | 100.00 |
| V3 | chip_sw_all_resets | chip_sw_pwrmgr_all_reset_reqs | 31.456m | 12.991ms | 3 | 3 | 100.00 |
| V3 | chip_sw_rom_ctrl_kmac_error | chip_sw_rom_ctrl_kmac_error | 0 | 0 | -- | ||
| V3 | chip_sw_rom_ctrl_digests | chip_sw_rom_ctrl_digests | 0 | 0 | -- | ||
| V3 | chip_sw_plic_alerts | chip_sw_all_escalation_resets | 16.382m | 5.995ms | 98 | 100 | 98.00 |
| V3 | tick_configuration | chip_sw_rv_timer_systick_test | 0 | 3 | 0.00 | ||
| V3 | counter_wrap | chip_sw_rv_timer_systick_test | 0 | 3 | 0.00 | ||
| V3 | chip_sw_spi_device_pass_through_flash_model | //sw/device/tests:spi_passthru_test | 0 | 0 | -- | ||
| V3 | chip_sw_spi_device_output_when_disabled_or_sleeping | chip_sw_spi_device_pinmux_sleep_retention | 6.996m | 3.561ms | 3 | 3 | 100.00 |
| V3 | chip_sw_spi_host_pass_through | //sw/device/tests:spi_passthru_test | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_configuration | //sw/device/tests:spi_host_config_test | 0 | 0 | -- | ||
| V3 | chip_sw_spi_host_events | chip_sw_spi_host_events | 0 | 0 | -- | ||
| V3 | chip_sw_sram_memset | chip_sw_sram_memset | 0 | 0 | -- | ||
| V3 | chip_sw_sram_readback | chip_sw_sram_readback | 0 | 0 | -- | ||
| V3 | chip_sw_sram_subword_access | chip_sw_sram_subword_access | 0 | 0 | -- | ||
| V3 | chip_sw_uart_parity | chip_sw_uart_parity | 0 | 0 | -- | ||
| V3 | chip_sw_uart_line_loopback | chip_sw_uart_line_loopback | 0 | 0 | -- | ||
| V3 | chip_sw_uart_system_loopback | chip_sw_uart_system_loopback | 0 | 0 | -- | ||
| V3 | chip_sw_uart_line_break | chip_sw_uart_line_break | 0 | 0 | -- | ||
| V3 | chip_sw_uart_watermarks | chip_sw_uart_tx_rx | 14.739m | 4.742ms | 5 | 5 | 100.00 |
| V3 | chip_sw_usbdev_stream | chip_sw_usbdev_stream | 1.282h | 18.542ms | 1 | 1 | 100.00 |
| V3 | chip_sw_usbdev_iso | chip_sw_usbdev_iso | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_mixed | chip_sw_usbdev_mixed | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_suspend_resume | chip_sw_usbdev_suspend_resume | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_aon_wake_reset | chip_sw_usbdev_aon_wake_reset | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_aon_wake_disconnect | chip_sw_usbdev_aon_wake_disconnect | 0 | 0 | -- | ||
| V3 | chip_sw_usbdev_toggle_restore | chip_sw_usbdev_toggle_restore | 0 | 0 | -- | ||
| V3 | chip_rv_dm_perform_debug | rom_e2e_jtag_debug_test_unlocked0 | 36.088m | 11.495ms | 1 | 1 | 100.00 |
| rom_e2e_jtag_debug_dev | 33.745m | 11.144ms | 1 | 1 | 100.00 | ||
| rom_e2e_jtag_debug_rma | 33.613m | 11.002ms | 1 | 1 | 100.00 | ||
| V3 | chip_sw_rv_dm_access_after_hw_reset | chip_sw_rv_dm_access_after_escalation_reset | 8.827m | 4.897ms | 3 | 3 | 100.00 |
| V3 | TOTAL | 48 | 51 | 94.12 | |||
| Unmapped tests | chip_sival_flash_info_access | 5.853m | 3.636ms | 3 | 3 | 100.00 | |
| chip_sw_rstmgr_rst_cnsty_escalation | 13.150m | 5.857ms | 3 | 3 | 100.00 | ||
| chip_sw_otp_ctrl_ecc_error_vendor_test | 6.052m | 3.714ms | 3 | 3 | 100.00 | ||
| chip_sw_otbn_ecdsa_op_irq | 1.166h | 17.130ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_rnd | 18.062m | 5.243ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_nmi_irq | 17.365m | 4.731ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_lowpower_cancel | 7.911m | 4.212ms | 3 | 3 | 100.00 | ||
| chip_sw_pwrmgr_sleep_wake_5_bug | 9.158m | 6.044ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_address_translation | 6.063m | 3.576ms | 3 | 3 | 100.00 | ||
| chip_sw_rv_core_ibex_lockstep_glitch | 4.790m | 3.480ms | 3 | 3 | 100.00 | ||
| chip_sw_flash_ctrl_write_clear | 6.207m | 2.989ms | 3 | 3 | 100.00 | ||
| TOTAL | 2932 | 2951 | 99.36 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 11 | 11 | 11 | 100.00 |
| V1 | 18 | 18 | 16 | 88.89 |
| V2 | 285 | 270 | 263 | 92.28 |
| V2S | 1 | 1 | 1 | 100.00 |
| V3 | 90 | 23 | 22 | 24.44 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.02 | 95.49 | 93.82 | 95.32 | -- | 94.57 | 97.35 | 99.55 |
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 9 failures:
Test chip_sw_rv_timer_systick_test has 3 failures.
0.chip_sw_rv_timer_systick_test.112810016633867586177217680247024995982396898436632609439616072019305292650128
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
Job ID: smart:dfc6237a-7b5d-4e9a-9537-1169f2a59127
1.chip_sw_rv_timer_systick_test.91749458578188068926366374038154676444720999620961227945053227016737543237805
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
Job ID: smart:a27e4890-ad0e-40cf-bdc2-28ac511513c8
... and 1 more failures.
Test chip_sw_alert_handler_reverse_ping_in_deep_sleep has 2 failures.
0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.56041378274381360511098560761382378717427682800612911097482541700912925730818
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest/run.log
Job ID: smart:37d5e4fc-f072-4843-8615-a7ae0ee6c5e5
2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.29341983066835888004809852639767751763483899856273671993843539032166324652586
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest/run.log
Job ID: smart:d28fa1e4-6ba4-4a0b-b38a-8aa11584a274
Test chip_sw_keymgr_key_derivation has 1 failures.
0.chip_sw_keymgr_key_derivation.109516194473806972717277790776159856593680621265966362176032784875135692499571
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_keymgr_key_derivation/latest/run.log
Job ID: smart:79e0aa23-3680-4897-a1e0-319cdad45214
Test chip_sw_keymgr_sideload_aes has 1 failures.
2.chip_sw_keymgr_sideload_aes.23738019940764700524114303929459446295325063412458996717879291919820613186522
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_keymgr_sideload_aes/latest/run.log
Job ID: smart:4bc6d6f0-645b-4086-b907-70b597a895e9
Test chip_tap_straps_testunlock0 has 2 failures.
2.chip_tap_straps_testunlock0.102635090382856779807759679956040514586130901416913331430783552672055338648443
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_tap_straps_testunlock0/latest/run.log
Job ID: smart:c95eb13f-b553-4921-906d-bff44e4eb768
3.chip_tap_straps_testunlock0.23505178407034937141325712530303379761960122457127281308447985240338838516510
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/3.chip_tap_straps_testunlock0/latest/run.log
Job ID: smart:53130839-d805-47ef-8de9-5a89f837011c
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 4 failures:
3.chip_sw_alert_handler_lpg_sleep_mode_alerts.85422739088638592907848573597335123854806551610708975854599857623861707639631
Line 787, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
UVM_ERROR @ 4009.622568 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=2000371c MTVAL=40600800
UVM_INFO @ 4009.622568 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
25.chip_sw_alert_handler_lpg_sleep_mode_alerts.87083664695793127639308651478471338236879911495514763240680602088683025501614
Line 833, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
UVM_ERROR @ 3684.692132 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=2000371c MTVAL=40600800
UVM_INFO @ 3684.692132 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
Job chip_earlgrey_asic-sim-vcs_run_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
0.chip_csr_aliasing.29695806110629084553744191299049501915790573675621714101068354424495117615699
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
Job ID: smart:828f4750-1752-42bd-a0f4-687118b809ab
3.chip_csr_aliasing.52196853046844948789695506159424297822851152286819547899146566657119009888883
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/3.chip_csr_aliasing/latest/run.log
Job ID: smart:0eea3d97-c0df-411d-8a9a-4156fd9012fe
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 2 failures:
8.chip_sw_all_escalation_resets.75136827026339518121261685338891668368352989869645434507944371127200940858792
Line 802, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/8.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 2307.562500 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
UVM_INFO @ 2307.562500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
60.chip_sw_all_escalation_resets.64812424190555009190727511612725889032250162068577694951213151689061699957387
Line 812, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/60.chip_sw_all_escalation_resets/latest/run.log
UVM_ERROR @ 3064.211800 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
UVM_INFO @ 3064.211800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * us hit, indicating a probable testbench issue has 1 failures:
0.chip_tap_straps_dev.75345672096010971464058680002383578868282451601449609547004872708835107847559
Line 6129, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_tap_straps_dev/latest/run.log
UVM_FATAL @ 60000.000000 us: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 60000.000000 us hit, indicating a probable testbench issue
UVM_INFO @ 60000.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_if.sv:151) [tb.dut.chip_if] Detected an X on MioPadIor* (num=46) has 1 failures:
0.chip_csr_hw_reset.39020447647890470942395258131399911682996301683743014223359872213793789530714
Line 341, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_hw_reset/latest/run.log
UVM_ERROR @ 2640.760417 us: (chip_if.sv:151) [tb.dut.chip_if] Detected an X on MioPadIor13 (num=46)
UVM_INFO @ 2640.760417 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---