Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3951840	1			T81	3588		T82	9661		T85	1729
values[2]	782356	1			T81	1345		T82	2927		T85	551
values[3]	112347	1			T81	478		T82	674		T85	40
values[4]	61230	1			T81	263		T82	358		T85	1
values[5]	41925	1			T81	195		T82	246		T461	236
values[6]	31670	1			T81	190		T82	185		T461	212
values[7]	25677	1			T81	163		T82	178		T461	103
values[8]	22233	1			T81	125		T82	107		T461	47
values[9]	19551	1			T81	108		T82	87		T461	46
values[10]	17687	1			T81	147		T82	69		T461	32
values[11]	16697	1			T81	96		T82	48		T461	32
values[12]	15299	1			T81	70		T82	47		T461	34
values[13]	14597	1			T81	109		T82	33		T461	44
values[14]	14053	1			T81	95		T82	32		T461	29
values[15]	13759	1			T81	99		T82	21		T461	27
values[16]	13161	1			T81	99		T82	28		T461	27
values[17]	12847	1			T81	78		T82	27		T461	16
values[18]	12145	1			T81	103		T82	22		T461	21
values[19]	11780	1			T81	80		T82	19		T461	12
values[20]	11528	1			T81	88		T82	15		T461	24
values[21]	11275	1			T81	88		T82	13		T461	18
values[22]	10762	1			T81	91		T82	9		T461	23
values[23]	10134	1			T81	55		T82	9		T461	24
values[24]	9770	1			T81	40		T82	9		T461	26
values[25]	9466	1			T81	49		T82	13		T461	29
values[26]	9093	1			T81	44		T82	17		T461	41
values[27]	8729	1			T81	50		T82	17		T461	65
values[28]	8029	1			T81	26		T82	15		T461	33
values[29]	7477	1			T81	21		T82	7		T461	20
values[30]	7344	1			T81	15		T82	15		T461	10
values[31]	6878	1			T81	20		T82	12		T461	15
values[32]	6429	1			T81	35		T82	10		T461	14
values[33]	6059	1			T81	41		T82	11		T461	13
values[34]	5559	1			T81	39		T82	16		T461	8
values[35]	5020	1			T81	26		T82	9		T461	9
values[36]	4796	1			T81	22		T82	12		T461	11
values[37]	4562	1			T81	19		T82	16		T461	15
values[38]	4277	1			T81	26		T82	11		T461	18
values[39]	4063	1			T81	21		T82	12		T461	10
values[40]	3912	1			T81	17		T82	11		T461	12
values[41]	3812	1			T81	30		T82	14		T461	8
values[42]	3726	1			T81	25		T82	16		T461	7
values[43]	3671	1			T81	24		T82	14		T461	9
values[44]	3595	1			T81	31		T82	15		T461	10
values[45]	3405	1			T81	26		T82	15		T461	15
values[46]	3426	1			T81	20		T82	15		T461	16
values[47]	3314	1			T81	27		T82	15		T461	14
values[48]	3263	1			T81	20		T82	15		T461	17
values[49]	3163	1			T81	25		T82	18		T461	11
values[50]	3074	1			T81	21		T82	24		T461	18
values[51]	3041	1			T81	31		T82	11		T461	16
values[52]	2848	1			T81	19		T82	13		T461	11
values[53]	2726	1			T81	20		T82	11		T461	15
values[54]	2815	1			T81	20		T82	9		T461	17
values[55]	2756	1			T81	9		T82	17		T461	19
values[56]	2684	1			T81	19		T82	12		T461	12
values[57]	2743	1			T81	29		T82	11		T461	11
values[58]	2690	1			T81	19		T82	16		T461	25
values[59]	2616	1			T81	20		T82	11		T461	23
values[60]	2618	1			T81	21		T82	14		T461	21
values[61]	2841	1			T81	15		T82	16		T461	20
values[62]	4255	1			T81	46		T82	20		T461	33
values[63]	11947	1			T81	126		T82	74		T461	118
values[64]	235025	1			T81	455		T82	365		T461	438

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	5063250	1			T81	8859		T82	14325		T85	1830
values[2]	875528	1			T81	1803		T82	3057		T85	426
values[3]	87917	1			T81	271		T82	432		T85	59
values[4]	15674	1			T81	34		T82	36		T85	2
values[5]	6039	1			T81	21		T461	9		T494	1
values[6]	3679	1			T81	19		T461	13		T565	2
values[7]	2535	1			T81	24		T461	11		T470	1
values[8]	2038	1			T81	26		T461	9		T455	7
values[9]	1840	1			T81	42		T461	23		T455	2
values[10]	1640	1			T81	32		T461	8		T422	3
values[11]	1540	1			T81	27		T461	2		T866	4
values[12]	1518	1			T81	22		T461	1		T866	12
values[13]	1320	1			T81	38		T461	1		T866	22
values[14]	1201	1			T81	46		T461	1		T866	35
values[15]	1142	1			T81	40		T461	2		T866	15
values[16]	1051	1			T81	40		T461	4		T866	25
values[17]	998	1			T81	23		T461	4		T866	22
values[18]	960	1			T81	46		T461	2		T866	17
values[19]	922	1			T81	51		T461	1		T866	7
values[20]	979	1			T81	49		T461	1		T866	12
values[21]	853	1			T81	37		T461	3		T866	8
values[22]	770	1			T81	28		T461	1		T866	5
values[23]	734	1			T81	29		T461	3		T866	3
values[24]	759	1			T81	22		T461	2		T866	3
values[25]	698	1			T81	28		T461	1		T866	5
values[26]	712	1			T81	27		T461	3		T866	2
values[27]	731	1			T81	20		T461	2		T866	1
values[28]	711	1			T81	15		T461	2		T866	5
values[29]	652	1			T81	18		T461	1		T866	2
values[30]	666	1			T81	23		T461	1		T866	2
values[31]	590	1			T81	9		T461	1		T866	2
values[32]	612	1			T81	12		T461	1		T866	4
values[33]	594	1			T81	7		T461	1		T866	2
values[34]	616	1			T81	8		T461	2		T866	2
values[35]	577	1			T81	5		T461	2		T866	2
values[36]	579	1			T81	5		T461	2		T866	1
values[37]	592	1			T81	4		T461	2		T866	1
values[38]	553	1			T81	4		T461	2		T866	1
values[39]	531	1			T81	5		T461	7		T866	1
values[40]	512	1			T81	4		T461	4		T866	2
values[41]	519	1			T81	14		T461	1		T866	3
values[42]	501	1			T81	17		T461	1		T866	8
values[43]	503	1			T81	26		T461	1		T866	9
values[44]	476	1			T81	14		T461	2		T866	5
values[45]	482	1			T81	15		T461	2		T866	1
values[46]	458	1			T81	8		T461	1		T866	1
values[47]	444	1			T81	3		T461	2		T866	1
values[48]	463	1			T81	6		T461	1		T866	3
values[49]	481	1			T81	10		T461	1		T866	2
values[50]	463	1			T81	7		T461	2		T866	1
values[51]	442	1			T81	4		T461	2		T866	4
values[52]	442	1			T81	10		T461	1		T866	2
values[53]	445	1			T81	13		T461	1		T866	1
values[54]	435	1			T81	4		T461	1		T866	1
values[55]	382	1			T81	1		T461	1		T866	1
values[56]	397	1			T81	2		T461	3		T866	2
values[57]	375	1			T81	4		T461	1		T866	2
values[58]	393	1			T81	2		T461	2		T866	1
values[59]	364	1			T81	2		T461	2		T866	6
values[60]	386	1			T81	2		T461	4		T866	3
values[61]	416	1			T461	1		T866	2		T684	7
values[62]	745	1			T461	8		T866	3		T684	18
values[63]	3139	1			T461	33		T866	26		T684	66
values[64]	26797	1			T461	83		T866	76		T684	241

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	563127	1			T81	191		T82	512		T85	17
values[2]	2840647	1			T81	1896		T82	3915		T85	611
values[3]	1259634	1			T81	3240		T82	7437		T85	1685
values[4]	157385	1			T81	636		T82	803		T85	54
values[5]	81102	1			T81	416		T82	457		T461	272
values[6]	53704	1			T81	210		T82	369		T461	182
values[7]	39593	1			T81	185		T82	279		T461	158
values[8]	31257	1			T81	161		T82	208		T461	82
values[9]	27114	1			T81	136		T82	172		T461	38
values[10]	24257	1			T81	128		T82	180		T461	59
values[11]	21186	1			T81	135		T82	166		T461	68
values[12]	19539	1			T81	116		T82	145		T461	45
values[13]	18467	1			T81	129		T82	143		T461	39
values[14]	17234	1			T81	97		T82	86		T461	37
values[15]	16237	1			T81	86		T82	72		T461	34
values[16]	15578	1			T81	112		T82	45		T461	47
values[17]	15169	1			T81	95		T82	37		T461	34
values[18]	14291	1			T81	92		T82	39		T461	26
values[19]	13954	1			T81	68		T82	25		T461	27
values[20]	13364	1			T81	66		T82	29		T461	23
values[21]	12739	1			T81	62		T82	24		T461	12
values[22]	12349	1			T81	71		T82	21		T461	24
values[23]	11791	1			T81	80		T82	24		T461	17
values[24]	11176	1			T81	75		T82	25		T461	24
values[25]	10618	1			T81	57		T82	32		T461	37
values[26]	10303	1			T81	67		T82	26		T461	50
values[27]	9737	1			T81	78		T82	23		T461	41
values[28]	9124	1			T81	103		T82	14		T461	41
values[29]	8460	1			T81	80		T82	13		T461	29
values[30]	8093	1			T81	62		T82	18		T461	26
values[31]	7472	1			T81	54		T82	14		T461	14
values[32]	6717	1			T81	42		T82	11		T461	13
values[33]	6248	1			T81	36		T82	16		T461	14
values[34]	5747	1			T81	31		T82	18		T461	12
values[35]	5490	1			T81	40		T82	27		T461	12
values[36]	5087	1			T81	42		T82	12		T461	15
values[37]	4637	1			T81	42		T82	19		T461	22
values[38]	4402	1			T81	39		T82	19		T461	18
values[39]	4393	1			T81	22		T82	16		T461	11
values[40]	4222	1			T81	20		T82	21		T461	11
values[41]	3948	1			T81	13		T82	17		T461	16
values[42]	3841	1			T81	17		T82	22		T461	16
values[43]	3817	1			T81	18		T82	20		T461	21
values[44]	3638	1			T81	31		T82	12		T461	22
values[45]	3681	1			T81	21		T82	19		T461	16
values[46]	3636	1			T81	35		T82	25		T461	14
values[47]	3564	1			T81	24		T82	25		T461	14
values[48]	3502	1			T81	12		T82	27		T461	16
values[49]	3299	1			T81	15		T82	18		T461	16
values[50]	3260	1			T81	17		T82	17		T461	19
values[51]	3229	1			T81	28		T82	20		T461	19
values[52]	3153	1			T81	32		T82	19		T461	17
values[53]	3048	1			T81	33		T82	8		T461	17
values[54]	3136	1			T81	32		T82	16		T461	10
values[55]	2987	1			T81	19		T82	13		T461	12
values[56]	3038	1			T81	17		T82	12		T461	12
values[57]	2947	1			T81	16		T82	13		T461	26
values[58]	2874	1			T81	17		T82	12		T461	33
values[59]	2820	1			T81	26		T82	27		T461	33
values[60]	2794	1			T81	20		T82	27		T461	29
values[61]	3060	1			T81	25		T82	19		T461	19
values[62]	3983	1			T81	19		T82	37		T461	47
values[63]	10168	1			T81	88		T82	112		T461	124
values[64]	226750	1			T81	343		T82	356		T461	449