Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1953976	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

37676992

1

T1

207824

T2

8132

T3

2602

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	27768388	1			T1	132599		T2	2521		T3	358
values[0x0]	10427050	1			T1	75225		T2	5611		T3	2244
values[0x1]	1435530	1			T1	1049		T2	375		T3	42

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	658693	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

38972275

1

T1

208873

T2

8507

T3

2644

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18605885	1			T1	104437		T2	4254		T3	1322
valid_sources[0x01]	18604763	1			T1	104436		T2	4253		T3	1322
valid_sources[0x02]	38824	1			T23	1		T84	1		T80	87
valid_sources[0x03]	38302	1			T84	1		T211	2		T80	81
valid_sources[0x04]	38682	1			T23	1		T73	4		T84	1
valid_sources[0x05]	38754	1			T210	3		T211	1		T80	85
valid_sources[0x06]	38779	1			T73	1		T84	2		T80	106
valid_sources[0x07]	53292	1			T23	1		T84	2		T211	1
valid_sources[0x08]	38256	1			T23	1		T84	1		T210	2
valid_sources[0x09]	38741	1			T210	1		T211	1		T80	81
valid_sources[0x0a]	38562	1			T211	1		T80	89		T917	39
valid_sources[0x0b]	39056	1			T84	2		T54	3		T80	93
valid_sources[0x0c]	38558	1			T84	2		T80	87		T917	64
valid_sources[0x0d]	38838	1			T23	3		T84	1		T210	2
valid_sources[0x0e]	38203	1			T23	3		T80	83		T917	65
valid_sources[0x0f]	39465	1			T23	1		T54	4		T210	2
valid_sources[0x10]	39166	1			T23	1		T84	1		T210	2
valid_sources[0x11]	38514	1			T211	1		T80	75		T917	53
valid_sources[0x12]	38657	1			T23	1		T80	86		T917	79
valid_sources[0x13]	38300	1			T211	1		T80	78		T917	73
valid_sources[0x14]	39396	1			T23	1		T73	3		T210	2
valid_sources[0x15]	38478	1			T84	3		T211	2		T80	78
valid_sources[0x16]	38961	1			T84	1		T80	75		T917	70
valid_sources[0x17]	38265	1			T23	1		T80	87		T917	41
valid_sources[0x18]	38723	1			T23	1		T210	1		T211	1
valid_sources[0x19]	38860	1			T23	1		T84	1		T211	1
valid_sources[0x1a]	38506	1			T211	1		T80	74		T917	69
valid_sources[0x1b]	38541	1			T84	1		T211	1		T80	83
valid_sources[0x1c]	38579	1			T23	3		T210	1		T80	77
valid_sources[0x1d]	38412	1			T73	8		T80	84		T917	61
valid_sources[0x1e]	38615	1			T84	1		T54	12		T210	1
valid_sources[0x1f]	38358	1			T23	2		T84	1		T54	4
valid_sources[0x20]	38628	1			T84	1		T210	3		T80	66

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27030982

1

T1

132599

T2

2521

T3

358

values[0x0]

all_enables

biggest_size

10371819

1

T1

75225

T2

5611

T3

2244

values[0x1]

all_enables

biggest_size

274191

1

T23

15

T73

19

T84

21

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2971905	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

469902

1

T81

1295

T82

81

T85

316

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1166451	1			T81	3165		T82	331		T85	786
values[0x0]	1110075	1			T81	3057		T82	63		T85	767
values[0x1]	1165281	1			T81	3053		T82	359		T85	768

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2300180	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1141627

1

T81

3012

T82

263

T85

769

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52758	1			T81	136		T82	6		T85	13
valid_sources[0x01]	54131	1			T81	123		T82	8		T85	42
valid_sources[0x02]	53694	1			T81	125		T82	10		T85	26
valid_sources[0x03]	56083	1			T81	276		T82	8		T85	22
valid_sources[0x04]	53151	1			T81	111		T82	9		T85	28
valid_sources[0x05]	53192	1			T81	170		T82	6		T85	48
valid_sources[0x06]	53996	1			T81	135		T82	13		T85	35
valid_sources[0x07]	53838	1			T81	185		T82	11		T85	33
valid_sources[0x08]	53729	1			T81	180		T82	10		T85	26
valid_sources[0x09]	53517	1			T81	152		T82	9		T85	47
valid_sources[0x0a]	53816	1			T81	152		T82	12		T85	29
valid_sources[0x0b]	53373	1			T81	289		T82	11		T85	47
valid_sources[0x0c]	53487	1			T81	171		T82	10		T85	45
valid_sources[0x0d]	54618	1			T81	118		T82	12		T85	44
valid_sources[0x0e]	53405	1			T81	125		T82	14		T85	25
valid_sources[0x0f]	53997	1			T81	127		T82	12		T85	48
valid_sources[0x10]	53809	1			T81	144		T82	7		T85	32
valid_sources[0x11]	52494	1			T81	108		T82	9		T85	59
valid_sources[0x12]	52523	1			T81	157		T82	7		T85	33
valid_sources[0x13]	53790	1			T81	95		T82	18		T85	28
valid_sources[0x14]	54841	1			T81	118		T82	5		T85	37
valid_sources[0x15]	53715	1			T81	126		T82	9		T85	30
valid_sources[0x16]	54224	1			T81	175		T82	11		T85	41
valid_sources[0x17]	53164	1			T81	111		T82	13		T85	27
valid_sources[0x18]	53902	1			T81	129		T82	9		T85	40
valid_sources[0x19]	52689	1			T81	139		T82	14		T85	49
valid_sources[0x1a]	52979	1			T81	133		T82	10		T85	44
valid_sources[0x1b]	52235	1			T81	133		T82	16		T85	21
valid_sources[0x1c]	52830	1			T81	205		T82	8		T85	18
valid_sources[0x1d]	53425	1			T81	197		T82	16		T85	45
valid_sources[0x1e]	54514	1			T81	101		T82	13		T85	35
valid_sources[0x1f]	53686	1			T81	131		T82	7		T85	45
valid_sources[0x20]	54156	1			T81	114		T82	12		T85	34

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49639

1

T81

137

T82

28

T85

33

values[0x0]

all_enables

biggest_size

371292

1

T81

1020

T82

32

T85

248

values[0x1]

all_enables

biggest_size

48971

1

T81

138

T82

21

T85

35

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3184021	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

518208

1

T81

1690

T82

89

T85

310

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1268394	1			T81	4010		T82	369		T85	831
values[0x0]	1167364	1			T81	3805		T82	64		T85	721
values[0x1]	1266471	1			T81	4157		T82	382		T85	765

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2443654	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1258575

1

T81

4073

T82

321

T85

764

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	56961	1			T81	179		T82	12		T85	44
valid_sources[0x01]	58486	1			T81	193		T82	14		T85	30
valid_sources[0x02]	57680	1			T81	178		T82	11		T85	34
valid_sources[0x03]	58233	1			T81	216		T82	9		T85	33
valid_sources[0x04]	57213	1			T81	198		T82	17		T85	47
valid_sources[0x05]	58183	1			T81	171		T82	16		T85	35
valid_sources[0x06]	57507	1			T81	187		T82	12		T85	25
valid_sources[0x07]	57399	1			T81	187		T82	12		T85	43
valid_sources[0x08]	56787	1			T81	204		T82	10		T85	32
valid_sources[0x09]	57940	1			T81	201		T82	13		T85	35
valid_sources[0x0a]	57584	1			T81	157		T82	16		T85	37
valid_sources[0x0b]	57848	1			T81	190		T82	9		T85	50
valid_sources[0x0c]	58248	1			T81	216		T82	14		T85	34
valid_sources[0x0d]	58017	1			T81	203		T82	14		T85	41
valid_sources[0x0e]	57426	1			T81	207		T82	16		T85	25
valid_sources[0x0f]	57476	1			T81	191		T82	16		T85	30
valid_sources[0x10]	57813	1			T81	162		T82	10		T85	60
valid_sources[0x11]	58229	1			T81	165		T82	6		T85	32
valid_sources[0x12]	57847	1			T81	212		T82	19		T85	54
valid_sources[0x13]	58110	1			T81	169		T82	18		T85	19
valid_sources[0x14]	57760	1			T81	187		T82	10		T85	33
valid_sources[0x15]	57337	1			T81	178		T82	15		T85	32
valid_sources[0x16]	57381	1			T81	180		T82	8		T85	31
valid_sources[0x17]	59295	1			T81	192		T82	14		T85	26
valid_sources[0x18]	58563	1			T81	182		T82	18		T85	26
valid_sources[0x19]	57688	1			T81	185		T82	11		T85	47
valid_sources[0x1a]	57389	1			T81	180		T82	4		T85	41
valid_sources[0x1b]	57745	1			T81	190		T82	11		T85	24
valid_sources[0x1c]	56596	1			T81	174		T82	14		T85	26
valid_sources[0x1d]	57697	1			T81	196		T82	16		T85	31
valid_sources[0x1e]	57891	1			T81	202		T82	14		T85	20
valid_sources[0x1f]	57886	1			T81	184		T82	12		T85	41
valid_sources[0x20]	58472	1			T81	177		T82	10		T85	41

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

54888

1

T81

171

T82

28

T85

38

values[0x0]

all_enables

biggest_size

408949

1

T81

1345

T82

30

T85

249

values[0x1]

all_enables

biggest_size

54371

1

T81

174

T82

31

T85

23

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2996434	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

473559

1

T81

1434

T82

74

T85

320

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1175475	1			T81	3355		T82	362		T85	794
values[0x0]	1118416	1			T81	3352		T82	57		T85	821
values[0x1]	1176102	1			T81	3414		T82	327		T85	752

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2320690	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1149303

1

T81

3408

T82

295

T85

771

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	54362	1			T81	152		T82	8		T85	24
valid_sources[0x01]	54454	1			T81	152		T82	9		T85	45
valid_sources[0x02]	53715	1			T81	168		T82	19		T85	26
valid_sources[0x03]	53714	1			T81	172		T82	15		T85	39
valid_sources[0x04]	53389	1			T81	156		T82	10		T85	40
valid_sources[0x05]	55206	1			T81	169		T82	7		T85	25
valid_sources[0x06]	53756	1			T81	156		T82	16		T85	22
valid_sources[0x07]	54595	1			T81	149		T82	6		T85	41
valid_sources[0x08]	54191	1			T81	157		T82	7		T85	60
valid_sources[0x09]	54442	1			T81	160		T82	15		T85	56
valid_sources[0x0a]	54210	1			T81	142		T82	14		T85	26
valid_sources[0x0b]	53786	1			T81	176		T82	18		T85	37
valid_sources[0x0c]	54152	1			T81	153		T82	9		T85	67
valid_sources[0x0d]	53977	1			T81	177		T82	12		T85	19
valid_sources[0x0e]	53530	1			T81	171		T82	10		T85	23
valid_sources[0x0f]	54259	1			T81	147		T82	13		T85	34
valid_sources[0x10]	54366	1			T81	174		T82	13		T85	24
valid_sources[0x11]	55002	1			T81	148		T82	8		T85	30
valid_sources[0x12]	54204	1			T81	139		T82	9		T85	23
valid_sources[0x13]	54218	1			T81	157		T82	15		T85	23
valid_sources[0x14]	54672	1			T81	184		T82	13		T85	54
valid_sources[0x15]	54251	1			T81	164		T82	13		T85	42
valid_sources[0x16]	53726	1			T81	130		T82	7		T85	71
valid_sources[0x17]	54029	1			T81	172		T82	8		T85	62
valid_sources[0x18]	55454	1			T81	147		T82	13		T85	37
valid_sources[0x19]	53395	1			T81	167		T82	9		T85	19
valid_sources[0x1a]	53949	1			T81	157		T82	16		T85	15
valid_sources[0x1b]	53793	1			T81	176		T82	14		T85	48
valid_sources[0x1c]	54300	1			T81	151		T82	10		T85	39
valid_sources[0x1d]	53868	1			T81	169		T82	8		T85	55
valid_sources[0x1e]	54282	1			T81	140		T82	10		T85	48
valid_sources[0x1f]	53982	1			T81	154		T82	15		T85	32
valid_sources[0x20]	55230	1			T81	161		T82	10		T85	48

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49930

1

T81

142

T82

22

T85

29

values[0x0]

all_enables

biggest_size

373740

1

T81

1151

T82

28

T85

267

values[0x1]

all_enables

biggest_size

49889

1

T81

141

T82

24

T85

24