Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	527459792	62001373	0	0
DepthKnown_A	527459792	527351598	0	0
RvalidKnown_A	527459792	527351598	0	0
WreadyKnown_A	527459792	527351598	0	0
gen_passthru_fifo.paramCheckPass	1025	1025	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527459792	62001373	0	0
T1	100886	148107	0	0
T2	193268	16111	0	0
T3	55941	3939	0	0
T4	124483	17106	0	0
T5	653778	58047	0	0
T6	160292	22000	0	0
T7	881661	103741	0	0
T48	845983	728590	0	0
T49	129923	144255	0	0
T90	241285	25148	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527459792	527351598	0	0
T1	100886	100880	0	0
T2	193268	193155	0	0
T3	55941	55883	0	0
T4	124483	124425	0	0
T5	653778	653723	0	0
T6	160292	160230	0	0
T7	881661	881048	0	0
T48	845983	845921	0	0
T49	129923	129917	0	0
T90	241285	241230	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527459792	527351598	0	0
T1	100886	100880	0	0
T2	193268	193155	0	0
T3	55941	55883	0	0
T4	124483	124425	0	0
T5	653778	653723	0	0
T6	160292	160230	0	0
T7	881661	881048	0	0
T48	845983	845921	0	0
T49	129923	129917	0	0
T90	241285	241230	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527459792	527351598	0	0
T1	100886	100880	0	0
T2	193268	193155	0	0
T3	55941	55883	0	0
T4	124483	124425	0	0
T5	653778	653723	0	0
T6	160292	160230	0	0
T7	881661	881048	0	0
T48	845983	845921	0	0
T49	129923	129917	0	0
T90	241285	241230	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1025	1025	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T48	1	1	0	0
T49	1	1	0	0
T90	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	527459792	47816684	0	0
DepthKnown_A	527459792	527351598	0	0
RvalidKnown_A	527459792	527351598	0	0
WreadyKnown_A	527459792	527351598	0	0
gen_passthru_fifo.paramCheckPass	1025	1025	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527459792	47816684	0	0
T1	100886	132030	0	0
T2	193268	11908	0	0
T3	55941	2898	0	0
T4	124483	11929	0	0
T5	653778	54067	0	0
T6	160292	16706	0	0
T7	881661	72099	0	0
T48	845983	306691	0	0
T49	129923	124691	0	0
T90	241285	21207	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527459792	527351598	0	0
T1	100886	100880	0	0
T2	193268	193155	0	0
T3	55941	55883	0	0
T4	124483	124425	0	0
T5	653778	653723	0	0
T6	160292	160230	0	0
T7	881661	881048	0	0
T48	845983	845921	0	0
T49	129923	129917	0	0
T90	241285	241230	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527459792	527351598	0	0
T1	100886	100880	0	0
T2	193268	193155	0	0
T3	55941	55883	0	0
T4	124483	124425	0	0
T5	653778	653723	0	0
T6	160292	160230	0	0
T7	881661	881048	0	0
T48	845983	845921	0	0
T49	129923	129917	0	0
T90	241285	241230	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527459792	527351598	0	0
T1	100886	100880	0	0
T2	193268	193155	0	0
T3	55941	55883	0	0
T4	124483	124425	0	0
T5	653778	653723	0	0
T6	160292	160230	0	0
T7	881661	881048	0	0
T48	845983	845921	0	0
T49	129923	129917	0	0
T90	241285	241230	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1025	1025	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T48	1	1	0	0
T49	1	1	0	0
T90	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	527459792	43937240	0	0
DepthKnown_A	527459792	527351598	0	0
RvalidKnown_A	527459792	527351598	0	0
WreadyKnown_A	527459792	527351598	0	0
gen_passthru_fifo.paramCheckPass	1025	1025	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527459792	43937240	0	0
T1	100886	209449	0	0
T2	193268	8752	0	0
T3	55941	2726	0	0
T4	124483	6451	0	0
T5	653778	70768	0	0
T6	160292	9855	0	0
T7	881661	60403	0	0
T48	845983	252625	0	0
T49	129923	182530	0	0
T90	241285	22922	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527459792	527351598	0	0
T1	100886	100880	0	0
T2	193268	193155	0	0
T3	55941	55883	0	0
T4	124483	124425	0	0
T5	653778	653723	0	0
T6	160292	160230	0	0
T7	881661	881048	0	0
T48	845983	845921	0	0
T49	129923	129917	0	0
T90	241285	241230	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527459792	527351598	0	0
T1	100886	100880	0	0
T2	193268	193155	0	0
T3	55941	55883	0	0
T4	124483	124425	0	0
T5	653778	653723	0	0
T6	160292	160230	0	0
T7	881661	881048	0	0
T48	845983	845921	0	0
T49	129923	129917	0	0
T90	241285	241230	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527459792	527351598	0	0
T1	100886	100880	0	0
T2	193268	193155	0	0
T3	55941	55883	0	0
T4	124483	124425	0	0
T5	653778	653723	0	0
T6	160292	160230	0	0
T7	881661	881048	0	0
T48	845983	845921	0	0
T49	129923	129917	0	0
T90	241285	241230	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1025	1025	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T48	1	1	0	0
T49	1	1	0	0
T90	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	527459792	37191885	0	0
DepthKnown_A	527459792	527351598	0	0
RvalidKnown_A	527459792	527351598	0	0
WreadyKnown_A	527459792	527351598	0	0
gen_passthru_fifo.paramCheckPass	1025	1025	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527459792	37191885	0	0
T1	100886	208873	0	0
T2	193268	8507	0	0
T3	55941	2644	0	0
T4	124483	6173	0	0
T5	653778	70563	0	0
T6	160292	9571	0	0
T7	881661	58759	0	0
T48	845983	60502	0	0
T49	129923	117141	0	0
T90	241285	22718	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527459792	527351598	0	0
T1	100886	100880	0	0
T2	193268	193155	0	0
T3	55941	55883	0	0
T4	124483	124425	0	0
T5	653778	653723	0	0
T6	160292	160230	0	0
T7	881661	881048	0	0
T48	845983	845921	0	0
T49	129923	129917	0	0
T90	241285	241230	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527459792	527351598	0	0
T1	100886	100880	0	0
T2	193268	193155	0	0
T3	55941	55883	0	0
T4	124483	124425	0	0
T5	653778	653723	0	0
T6	160292	160230	0	0
T7	881661	881048	0	0
T48	845983	845921	0	0
T49	129923	129917	0	0
T90	241285	241230	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	527459792	527351598	0	0
T1	100886	100880	0	0
T2	193268	193155	0	0
T3	55941	55883	0	0
T4	124483	124425	0	0
T5	653778	653723	0	0
T6	160292	160230	0	0
T7	881661	881048	0	0
T48	845983	845921	0	0
T49	129923	129917	0	0
T90	241285	241230	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1025	1025	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T48	1	1	0	0
T49	1	1	0	0
T90	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	604037446	96703	0	0
DepthKnown_A	604037446	603913702	0	0
RvalidKnown_A	604037446	603913702	0	0
WreadyKnown_A	604037446	603913702	0	0
gen_passthru_fifo.paramCheckPass	2934	2934	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604037446	96703	0	0
T1	100886	81	0	0
T2	193268	30	0	0
T3	55941	3	0	0
T4	124483	26	0	0
T5	653778	53	0	0
T6	160292	26	0	0
T7	881661	209	0	0
T48	845983	2	0	0
T49	129923	36	0	0
T90	241285	53	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604037446	603913702	0	0
T1	100886	100880	0	0
T2	193268	193155	0	0
T3	55941	55883	0	0
T4	124483	124425	0	0
T5	653778	653723	0	0
T6	160292	160230	0	0
T7	881661	881048	0	0
T48	845983	845921	0	0
T49	129923	129917	0	0
T90	241285	241230	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604037446	603913702	0	0
T1	100886	100880	0	0
T2	193268	193155	0	0
T3	55941	55883	0	0
T4	124483	124425	0	0
T5	653778	653723	0	0
T6	160292	160230	0	0
T7	881661	881048	0	0
T48	845983	845921	0	0
T49	129923	129917	0	0
T90	241285	241230	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604037446	603913702	0	0
T1	100886	100880	0	0
T2	193268	193155	0	0
T3	55941	55883	0	0
T4	124483	124425	0	0
T5	653778	653723	0	0
T6	160292	160230	0	0
T7	881661	881048	0	0
T48	845983	845921	0	0
T49	129923	129917	0	0
T90	241285	241230	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2934	2934	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T48	1	1	0	0
T49	1	1	0	0
T90	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	604037446	100244	0	0
DepthKnown_A	604037446	603913702	0	0
RvalidKnown_A	604037446	603913702	0	0
WreadyKnown_A	604037446	603913702	0	0
gen_passthru_fifo.paramCheckPass	2934	2934	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604037446	100244	0	0
T1	100886	81	0	0
T2	193268	30	0	0
T3	55941	3	0	0
T4	124483	26	0	0
T5	653778	53	0	0
T6	160292	26	0	0
T7	881661	209	0	0
T48	845983	2	0	0
T49	129923	36	0	0
T90	241285	53	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604037446	603913702	0	0
T1	100886	100880	0	0
T2	193268	193155	0	0
T3	55941	55883	0	0
T4	124483	124425	0	0
T5	653778	653723	0	0
T6	160292	160230	0	0
T7	881661	881048	0	0
T48	845983	845921	0	0
T49	129923	129917	0	0
T90	241285	241230	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604037446	603913702	0	0
T1	100886	100880	0	0
T2	193268	193155	0	0
T3	55941	55883	0	0
T4	124483	124425	0	0
T5	653778	653723	0	0
T6	160292	160230	0	0
T7	881661	881048	0	0
T48	845983	845921	0	0
T49	129923	129917	0	0
T90	241285	241230	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604037446	603913702	0	0
T1	100886	100880	0	0
T2	193268	193155	0	0
T3	55941	55883	0	0
T4	124483	124425	0	0
T5	653778	653723	0	0
T6	160292	160230	0	0
T7	881661	881048	0	0
T48	845983	845921	0	0
T49	129923	129917	0	0
T90	241285	241230	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2934	2934	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T48	1	1	0	0
T49	1	1	0	0
T90	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	604037446	53506	0	0
DepthKnown_A	604037446	603913702	0	0
RvalidKnown_A	604037446	603913702	0	0
WreadyKnown_A	604037446	603913702	0	0
gen_passthru_fifo.paramCheckPass	2934	2934	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604037446	53506	0	0
T1	100886	40	0	0
T2	193268	28	0	0
T3	55941	3	0	0
T4	124483	23	0	0
T5	653778	52	0	0
T6	160292	23	0	0
T7	881661	198	0	0
T48	845983	1	0	0
T49	129923	5	0	0
T90	241285	52	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604037446	603913702	0	0
T1	100886	100880	0	0
T2	193268	193155	0	0
T3	55941	55883	0	0
T4	124483	124425	0	0
T5	653778	653723	0	0
T6	160292	160230	0	0
T7	881661	881048	0	0
T48	845983	845921	0	0
T49	129923	129917	0	0
T90	241285	241230	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604037446	603913702	0	0
T1	100886	100880	0	0
T2	193268	193155	0	0
T3	55941	55883	0	0
T4	124483	124425	0	0
T5	653778	653723	0	0
T6	160292	160230	0	0
T7	881661	881048	0	0
T48	845983	845921	0	0
T49	129923	129917	0	0
T90	241285	241230	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604037446	603913702	0	0
T1	100886	100880	0	0
T2	193268	193155	0	0
T3	55941	55883	0	0
T4	124483	124425	0	0
T5	653778	653723	0	0
T6	160292	160230	0	0
T7	881661	881048	0	0
T48	845983	845921	0	0
T49	129923	129917	0	0
T90	241285	241230	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2934	2934	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T48	1	1	0	0
T49	1	1	0	0
T90	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	604037446	53506	0	0
DepthKnown_A	604037446	603913702	0	0
RvalidKnown_A	604037446	603913702	0	0
WreadyKnown_A	604037446	603913702	0	0
gen_passthru_fifo.paramCheckPass	2934	2934	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604037446	53506	0	0
T1	100886	40	0	0
T2	193268	28	0	0
T3	55941	3	0	0
T4	124483	23	0	0
T5	653778	52	0	0
T6	160292	23	0	0
T7	881661	198	0	0
T48	845983	1	0	0
T49	129923	5	0	0
T90	241285	52	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604037446	603913702	0	0
T1	100886	100880	0	0
T2	193268	193155	0	0
T3	55941	55883	0	0
T4	124483	124425	0	0
T5	653778	653723	0	0
T6	160292	160230	0	0
T7	881661	881048	0	0
T48	845983	845921	0	0
T49	129923	129917	0	0
T90	241285	241230	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604037446	603913702	0	0
T1	100886	100880	0	0
T2	193268	193155	0	0
T3	55941	55883	0	0
T4	124483	124425	0	0
T5	653778	653723	0	0
T6	160292	160230	0	0
T7	881661	881048	0	0
T48	845983	845921	0	0
T49	129923	129917	0	0
T90	241285	241230	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604037446	603913702	0	0
T1	100886	100880	0	0
T2	193268	193155	0	0
T3	55941	55883	0	0
T4	124483	124425	0	0
T5	653778	653723	0	0
T6	160292	160230	0	0
T7	881661	881048	0	0
T48	845983	845921	0	0
T49	129923	129917	0	0
T90	241285	241230	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2934	2934	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T48	1	1	0	0
T49	1	1	0	0
T90	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	604037446	43197	0	0
DepthKnown_A	604037446	603913702	0	0
RvalidKnown_A	604037446	603913702	0	0
WreadyKnown_A	604037446	603913702	0	0
gen_passthru_fifo.paramCheckPass	2934	2934	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604037446	43197	0	0
T1	100886	41	0	0
T2	193268	2	0	0
T3	55941	0	0	0
T4	124483	3	0	0
T5	653778	1	0	0
T6	160292	3	0	0
T7	881661	11	0	0
T48	845983	1	0	0
T49	129923	31	0	0
T90	241285	1	0	0
T134	0	44	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604037446	603913702	0	0
T1	100886	100880	0	0
T2	193268	193155	0	0
T3	55941	55883	0	0
T4	124483	124425	0	0
T5	653778	653723	0	0
T6	160292	160230	0	0
T7	881661	881048	0	0
T48	845983	845921	0	0
T49	129923	129917	0	0
T90	241285	241230	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604037446	603913702	0	0
T1	100886	100880	0	0
T2	193268	193155	0	0
T3	55941	55883	0	0
T4	124483	124425	0	0
T5	653778	653723	0	0
T6	160292	160230	0	0
T7	881661	881048	0	0
T48	845983	845921	0	0
T49	129923	129917	0	0
T90	241285	241230	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604037446	603913702	0	0
T1	100886	100880	0	0
T2	193268	193155	0	0
T3	55941	55883	0	0
T4	124483	124425	0	0
T5	653778	653723	0	0
T6	160292	160230	0	0
T7	881661	881048	0	0
T48	845983	845921	0	0
T49	129923	129917	0	0
T90	241285	241230	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2934	2934	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T48	1	1	0	0
T49	1	1	0	0
T90	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	604037446	46738	0	0
DepthKnown_A	604037446	603913702	0	0
RvalidKnown_A	604037446	603913702	0	0
WreadyKnown_A	604037446	603913702	0	0
gen_passthru_fifo.paramCheckPass	2934	2934	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604037446	46738	0	0
T1	100886	41	0	0
T2	193268	2	0	0
T3	55941	0	0	0
T4	124483	3	0	0
T5	653778	1	0	0
T6	160292	3	0	0
T7	881661	11	0	0
T48	845983	1	0	0
T49	129923	31	0	0
T90	241285	1	0	0
T134	0	44	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604037446	603913702	0	0
T1	100886	100880	0	0
T2	193268	193155	0	0
T3	55941	55883	0	0
T4	124483	124425	0	0
T5	653778	653723	0	0
T6	160292	160230	0	0
T7	881661	881048	0	0
T48	845983	845921	0	0
T49	129923	129917	0	0
T90	241285	241230	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604037446	603913702	0	0
T1	100886	100880	0	0
T2	193268	193155	0	0
T3	55941	55883	0	0
T4	124483	124425	0	0
T5	653778	653723	0	0
T6	160292	160230	0	0
T7	881661	881048	0	0
T48	845983	845921	0	0
T49	129923	129917	0	0
T90	241285	241230	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	604037446	603913702	0	0
T1	100886	100880	0	0
T2	193268	193155	0	0
T3	55941	55883	0	0
T4	124483	124425	0	0
T5	653778	653723	0	0
T6	160292	160230	0	0
T7	881661	881048	0	0
T48	845983	845921	0	0
T49	129923	129917	0	0
T90	241285	241230	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2934	2934	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T48	1	1	0	0
T49	1	1	0	0
T90	1	1	0	0