Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T2,T7,T36	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T2,T7,T36	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T2,T7,T36	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T2,T7,T36	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T2,T7,T36	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T82,T253,T254	Yes	T82,T253,T254	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T48,T163,T224	Yes	T48,T163,T224	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T48,T203,T163	Yes	T48,T203,T163	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T23,T73,T84	Yes	T23,T73,T84	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T84,T54,T82	Yes	T84,T54,T82	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T84,T54,T80	Yes	T84,T54,T80	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T48,T36,T68	Yes	T48,T36,T68	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T2,T7,T36	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T48,T23,T83	Yes	T48,T23,T83	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T2,T7,T48	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T2,T7,T36	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T48,T23,T83	Yes	T48,T23,T83	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T2,T7,T36	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T48,T23,T83	Yes	T48,T23,T83	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T2,T7,T48	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T48,T23,T73	Yes	T48,T23,T73	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T48,T23,T83	Yes	T48,T23,T83	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T48,T23,T73	Yes	T48,T23,T73	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T48,*T23,*T83	Yes	T48,T23,T83	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T48,T23,T83	Yes	T48,T23,T83	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T2,T7,T36	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T2,T7,T48	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T48,T23,T83	Yes	T48,T23,T83	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T48,T23,T83	Yes	T48,T23,T83	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T48,T23,T83	Yes	T48,T23,T83	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T48,T23,T83	Yes	T48,T23,T83	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T48,T23,T83	Yes	T48,T23,T83	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T48,*T83,*T259	Yes	T48,T83,T259	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T48,T23,T83	Yes	T48,T23,T83	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T2,T7,T48	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T48,T83,T259	Yes	T48,T83,T259	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T48,T23,T83	Yes	T48,T23,T83	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T2,T7,T48	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T48,*T83,*T259	Yes	T48,T83,T259	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T2,T7,T48	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T48,T23,T83	Yes	T48,T23,T83	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T49,T13,T9	Yes	T49,T13,T9	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T49,T13,T9	Yes	T49,T13,T9	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T81,*T82,*T85	Yes	T81,T82,T85	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T2,T7,T36	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T8,T411,T55	Yes	T8,T411,T55	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T8,T411,T55	Yes	T8,T411,T55	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T55,T56,T57	Yes	T55,T56,T57	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T8,T411,T55	Yes	T8,T411,T55	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T81,*T82,*T85	Yes	T81,T82,T85	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T8,T411,T55	Yes	T8,T411,T55	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T8,T411,T55	Yes	T8,T411,T55	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T8,T411,T412	Yes	T8,T411,T412	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T80,T81,T82	Yes	T55,T56,T57	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T8,T411,T412	Yes	T8,T411,T55	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	T81,*T82,*T85	Yes	T81,T82,T85	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T8,*T412,*T413	Yes	T8,T411,T412	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T8,T411,T55	Yes	T8,T411,T55	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T48,*T23,*T83	Yes	T48,T23,T83	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T23,T73,T84	Yes	T23,T73,T84	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T69,T263,T163	Yes	T69,T263,T163	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T48,*T23,*T73	Yes	T48,T23,T83	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T36,T13,T23	Yes	T36,T13,T23	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T36,T13,T23	Yes	T36,T13,T23	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T36,T13,T23	Yes	T36,T13,T23	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T36,T13,T23	Yes	T36,T13,T23	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T36,T13,T23	Yes	T36,T13,T23	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T36,T13,T23	Yes	T36,T13,T23	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T23,*T81,*T82	Yes	T23,T81,T82	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T15,T205,T209	Yes	T15,T205,T209	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T36,T13,T23	Yes	T36,T13,T23	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T36,T13,T23	Yes	T36,T13,T23	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T13,T23,T14	Yes	T13,T23,T14	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T36,T13,T23	Yes	T36,T13,T23	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T13,T23,T14	Yes	T13,T23,T14	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T23,*T81,*T82	Yes	T23,T81,T82	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T13,*T23,*T14	Yes	T13,T23,T14	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T36,T13,T23	Yes	T36,T13,T23	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T13,T23,T14	Yes	T13,T23,T14	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T13,T23,T14	Yes	T13,T23,T14	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T13,T23,T14	Yes	T13,T23,T14	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T13,T23,T14	Yes	T13,T23,T14	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T13,T23,T14	Yes	T13,T23,T14	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T13,T23,T14	Yes	T13,T23,T14	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T23,*T81,*T82	Yes	T23,T81,T82	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T13,T23,T14	Yes	T13,T23,T14	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T13,T23,T14	Yes	T13,T23,T14	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T13,T23,T14	Yes	T13,T23,T14	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T13,T23,T14	Yes	T13,T23,T14	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T13,T23,T14	Yes	T13,T23,T14	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T23,*T81,*T82	Yes	T23,T81,T82	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T13,*T23,*T14	Yes	T13,T23,T14	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T13,T23,T14	Yes	T13,T23,T14	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T81,*T82,*T85	Yes	T81,T82,T85	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	INPUT
tl_usbdev_i.d_error	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T19,T21,T395	Yes	T19,T21,T395	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T19,T21,T395	Yes	T19,T21,T395	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T81,*T82,*T85	Yes	T81,T82,T85	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T19,*T20,*T21	Yes	T19,T20,T21	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T73,*T54,*T81	Yes	T73,T54,T81	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T2,T7,T36	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T2,T7,T49	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T73,*T54,*T81	Yes	T73,T54,T81	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T2,T7,T36	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T73,T54,T80	Yes	T73,T54,T80	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T73,T54,T80	Yes	T73,T54,T80	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T73,T54,T80	Yes	T73,T54,T80	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T73,T54,T80	Yes	T73,T54,T80	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T73,T54,T80	Yes	T73,T54,T80	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T73,*T54,T81	Yes	T73,T54,T81	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T73,T54,T80	Yes	T73,T54,T80	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T73,T54,T80	Yes	T73,T54,T80	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T73,T54,T80	Yes	T73,T54,T80	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T73,T54,T80	Yes	T73,T54,T80	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T73,T54,T80	Yes	T73,T54,T80	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T73,*T54,T81	Yes	T73,T54,T81	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T73,*T54,*T80	Yes	T73,T54,T80	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T73,T54,T80	Yes	T73,T54,T80	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T4	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T2,T7,T36	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T81,*T82,*T85	Yes	T81,T82,T85	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_hmac_o.d_ready	Yes	Yes	T2,T7,T49	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T49,T13,T9	Yes	T49,T13,T9	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T49,T13,T9	Yes	T49,T13,T9	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T2,T49,T13	Yes	T2,T49,T13	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T49,T13,T9	Yes	T49,T13,T9	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T2,T49,T13	Yes	T2,T49,T13	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T73,*T54,*T81	Yes	T73,T54,T81	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T13,T125,T14	Yes	T13,T125,T14	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T2,T49,T13	Yes	T2,T49,T13	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T2,T49,T13	Yes	T2,T49,T13	INPUT
tl_hmac_i.d_error	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T2,T49,T13	Yes	T2,T49,T13	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T49,T13	Yes	T2,T49,T13	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T49,T13,T9	Yes	T49,T13,T9	INPUT
tl_hmac_i.d_sink	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T73,*T54,*T81	Yes	T73,T54,T81	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T49,*T13,*T9	Yes	T49,T13,T9	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T2,T49,T13	Yes	T2,T49,T13	INPUT
tl_kmac_o.d_ready	Yes	Yes	T2,T7,T36	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T13,T380,T112	Yes	T13,T380,T112	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T13,T158	Yes	T2,T13,T158	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T2,T13,T158	Yes	T2,T13,T158	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T13,T380,T112	Yes	T13,T380,T112	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T2,T13,T158	Yes	T2,T13,T158	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T23,*T73,*T54	Yes	T23,T73,T54	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T13,T380,T112	Yes	T13,T380,T112	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T2,T13,T158	Yes	T2,T13,T158	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T2,T13,T158	Yes	T2,T13,T158	INPUT
tl_kmac_i.d_error	Yes	Yes	T81,T82,T461	Yes	T81,T82,T461	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T2,T13,T158	Yes	T2,T13,T158	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T13,T158	Yes	T2,T13,T158	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T13,T158,T380	Yes	T13,T158,T380	INPUT
tl_kmac_i.d_sink	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T23,*T73,*T54	Yes	T23,T73,T54	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T13,*T158,*T380	Yes	T13,T158,T380	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T2,T13,T158	Yes	T2,T13,T158	INPUT
tl_aes_o.d_ready	Yes	Yes	T1,T2,T7	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T13,T718,T286	Yes	T13,T718,T286	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T13,T718,T286	Yes	T13,T718,T286	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T134	Yes	T1,T2,T134	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T13,T718,T286	Yes	T13,T718,T286	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T1,T2,T134	Yes	T1,T2,T134	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T81,*T82,*T85	Yes	T81,T82,T85	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T1,T2,T134	Yes	T1,T2,T134	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T1,T2,T134	Yes	T1,T2,T134	INPUT
tl_aes_i.d_error	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T134	Yes	T1,T2,T134	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T134,T13	Yes	T1,T134,T13	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T1,T2,T134	Yes	T1,T2,T134	INPUT
tl_aes_i.d_sink	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T81,*T82,*T85	Yes	T81,T82,T85	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T134	Yes	T1,T2,T134	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T1,T2,T134	Yes	T1,T2,T134	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T73,*T54,*T81	Yes	T73,T54,T81	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T1,T134,T13	Yes	T1,T134,T13	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T7	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T1,T2,T7	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T73,*T54,*T81	Yes	T73,T54,T81	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T1,*T134,*T13	Yes	T1,T49,T134	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T1,T134,T13	Yes	T1,T134,T13	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T73,*T54,*T81	Yes	T73,T54,T81	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T1,T134,T13	Yes	T1,T134,T13	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T7	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T1,T2,T7	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T73,*T54,*T81	Yes	T73,T54,T81	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T1,*T134,*T13	Yes	T1,T134,T13	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T1,T134,T13	Yes	T1,T134,T13	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T1,T134,T13	Yes	T1,T134,T13	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T73,*T54,*T81	Yes	T73,T54,T81	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	Yes	Yes	T81,T82,T253	Yes	T81,T82,T253	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T1,T134,T13	Yes	T1,T134,T13	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T7	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T1,T2,T7	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T73,*T54,*T81	Yes	T73,T54,T81	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T1,*T134,*T13	Yes	T1,T134,T13	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T1,T2,T7	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T1,T134,T13	Yes	T1,T134,T13	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T134,T13	Yes	T1,T134,T13	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T134,T13	Yes	T1,T134,T13	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T1,T134,T13	Yes	T1,T134,T13	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T1,T134,T13	Yes	T1,T134,T13	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T73,*T54,*T81	Yes	T73,T54,T81	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T1,T134,T13	Yes	T1,T134,T13	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T1,T134,T13	Yes	T1,T134,T13	INPUT
tl_edn1_i.d_error	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T1,T134,T13	Yes	T1,T134,T13	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T134,T13	Yes	T1,T134,T13	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T1,T134,T13	Yes	T1,T134,T13	INPUT
tl_edn1_i.d_sink	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T73,*T54,*T81	Yes	T73,T54,T81	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T1,*T134,*T13	Yes	T1,T134,T13	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T1,T134,T13	Yes	T1,T134,T13	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T23,*T81,*T82	Yes	T23,T81,T82	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T23,*T81,*T82	Yes	T23,T81,T82	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
tl_otbn_o.d_ready	Yes	Yes	T1,T2,T7	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T1,T49,T134	Yes	T1,T49,T134	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T49	Yes	T1,T2,T49	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T49	Yes	T1,T2,T49	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T1,T49,T134	Yes	T1,T49,T134	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T1,T2,T49	Yes	T1,T2,T49	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T23,*T84,*T54	Yes	T23,T84,T54	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T1,T2,T49	Yes	T1,T2,T49	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T1,T2,T49	Yes	T1,T2,T49	INPUT
tl_otbn_i.d_error	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T1,T49,T134	Yes	T1,T49,T134	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T49,T134	Yes	T1,T49,T134	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T1,T49,T134	Yes	T1,T49,T134	INPUT
tl_otbn_i.d_sink	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T23,*T84,*T54	Yes	T23,T84,T54	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T1,*T49,*T134	Yes	T1,T49,T134	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T1,T49,T134	Yes	T1,T49,T134	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T2,T7,T49	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T49,T158,T171	Yes	T49,T158,T171	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T49,T158,T171	Yes	T49,T158,T171	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T49,T158,T171	Yes	T49,T158,T171	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T49,T158,T50	Yes	T49,T158,T50	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T49,T158,T171	Yes	T49,T158,T171	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T73,*T54,*T81	Yes	T73,T54,T81	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T49,T158,T171	Yes	T49,T158,T171	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T49,T158,T171	Yes	T49,T158,T171	INPUT
tl_keymgr_i.d_error	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T49,T158,T50	Yes	T49,T158,T50	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T49,T158,T171	Yes	T49,T158,T171	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T49,T158,T171	Yes	T49,T158,T171	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T73,*T54,*T81	Yes	T73,T54,T81	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T49,*T158,*T171	Yes	T49,T158,T171	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T49,T158,T171	Yes	T49,T158,T171	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T260,*T261,*T81	Yes	T260,T261,T81	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T1,T4,T6	Yes	T1,T4,T6	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T1,T4,T6	Yes	T1,T4,T6	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T81,*T82,*T85	Yes	T260,T261,T81	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T4	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T2,T7,T48	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T48,T49,T9	Yes	T48,T49,T9	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T48,T49,T9	Yes	T48,T49,T9	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T48,T49,T9	Yes	T48,T49,T9	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T48,T49,T9	Yes	T48,T49,T9	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T48,T49,T9	Yes	T48,T49,T9	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T23,*T83,*T81	Yes	T23,T83,T81	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T48,T49,T9	Yes	T48,T49,T9	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T48,T49,T9	Yes	T48,T49,T9	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T23,T187,T189	Yes	T23,T187,T189	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T9,T46,T23	Yes	T48,T49,T9	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T9,T46,T23	Yes	T48,T49,T9	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T23,*T81,*T82	Yes	T23,T83,T81	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T23,*T187,*T99	Yes	T247,T23,T187	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T48,T49,T9	Yes	T48,T49,T9	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T2,T7,T48	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T81,T82,T85	Yes	T81,T82,T85	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range