Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3626534	1			T80	90		T81	7370		T82	157
values[2]	744622	1			T80	35		T81	1183		T82	41
values[3]	101801	1			T80	1		T81	160		T88	302
values[4]	55050	1			T81	39		T88	145		T520	185
values[5]	37490	1			T81	34		T88	74		T520	135
values[6]	27726	1			T81	28		T88	47		T520	87
values[7]	21905	1			T81	23		T88	40		T520	53
values[8]	18194	1			T81	29		T88	52		T520	43
values[9]	16176	1			T81	31		T88	46		T520	50
values[10]	15155	1			T81	27		T88	42		T520	55
values[11]	14067	1			T81	7		T88	11		T520	26
values[12]	13001	1			T81	4		T88	6		T520	35
values[13]	12319	1			T81	7		T88	21		T520	24
values[14]	11290	1			T81	10		T88	13		T520	20
values[15]	10680	1			T81	8		T88	19		T520	22
values[16]	10147	1			T81	3		T88	9		T520	21
values[17]	9688	1			T81	2		T88	4		T520	22
values[18]	9189	1			T81	3		T88	18		T520	13
values[19]	9304	1			T81	3		T88	8		T520	18
values[20]	9275	1			T81	3		T88	2		T520	30
values[21]	8936	1			T81	3		T88	4		T520	17
values[22]	8741	1			T81	3		T88	11		T520	23
values[23]	8403	1			T81	2		T88	5		T520	16
values[24]	8071	1			T81	2		T88	6		T520	22
values[25]	7891	1			T81	3		T88	6		T520	36
values[26]	7811	1			T81	4		T88	7		T520	31
values[27]	7372	1			T81	2		T88	5		T520	19
values[28]	6836	1			T81	6		T520	21		T516	2
values[29]	6432	1			T81	2		T520	20		T516	2
values[30]	5832	1			T81	2		T520	21		T516	2
values[31]	5395	1			T81	2		T520	13		T516	1
values[32]	5063	1			T81	4		T520	11		T516	4
values[33]	4755	1			T81	4		T520	9		T516	2
values[34]	4275	1			T81	6		T520	11		T516	4
values[35]	3964	1			T81	3		T520	10		T516	1
values[36]	3852	1			T81	2		T520	12		T516	1
values[37]	3661	1			T81	6		T520	20		T516	3
values[38]	3590	1			T81	4		T520	11		T516	1
values[39]	3421	1			T81	4		T520	11		T516	7
values[40]	3170	1			T81	2		T520	13		T516	8
values[41]	3077	1			T81	2		T520	7		T516	1
values[42]	3118	1			T81	3		T520	12		T516	2
values[43]	3098	1			T81	2		T520	13		T516	1
values[44]	2975	1			T81	3		T520	9		T516	1
values[45]	2994	1			T81	3		T520	8		T516	1
values[46]	2954	1			T81	4		T520	10		T516	2
values[47]	2952	1			T81	8		T520	12		T516	2
values[48]	2866	1			T81	7		T520	5		T516	3
values[49]	2826	1			T81	8		T520	6		T516	3
values[50]	2770	1			T81	3		T520	9		T516	1
values[51]	2659	1			T81	6		T520	13		T516	1
values[52]	2622	1			T81	11		T520	13		T516	1
values[53]	2546	1			T81	7		T520	9		T516	1
values[54]	2550	1			T81	5		T520	14		T516	1
values[55]	2400	1			T81	5		T520	12		T516	3
values[56]	2442	1			T81	6		T520	9		T516	1
values[57]	2436	1			T81	3		T520	8		T516	3
values[58]	2365	1			T81	2		T520	17		T516	4
values[59]	2356	1			T81	3		T520	13		T516	2
values[60]	2419	1			T81	2		T520	12		T516	1
values[61]	2665	1			T81	2		T520	13		T516	1
values[62]	3872	1			T81	5		T520	22		T516	1
values[63]	10880	1			T81	18		T520	121		T516	2
values[64]	218338	1			T81	106		T520	399		T516	125

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4627893	1			T80	116		T81	9120		T82	120
values[2]	794296	1			T80	32		T81	1357		T82	37
values[3]	82785	1			T80	6		T81	191		T88	82
values[4]	14608	1			T80	1		T81	7		T88	5
values[5]	5665	1			T88	2		T520	25		T516	3
values[6]	3470	1			T88	2		T520	25		T516	1
values[7]	2602	1			T88	1		T520	20		T516	1
values[8]	2405	1			T520	14		T516	3		T429	72
values[9]	2115	1			T520	10		T516	2		T429	80
values[10]	1860	1			T520	9		T516	1		T429	50
values[11]	1667	1			T520	17		T516	7		T429	20
values[12]	1502	1			T520	11		T516	1		T429	19
values[13]	1319	1			T520	5		T516	1		T429	16
values[14]	1223	1			T520	7		T516	1		T429	18
values[15]	1173	1			T520	26		T516	5		T429	33
values[16]	1255	1			T520	11		T516	3		T429	30
values[17]	1166	1			T520	5		T516	1		T429	38
values[18]	1053	1			T520	5		T516	3		T429	22
values[19]	999	1			T520	9		T516	2		T429	9
values[20]	881	1			T520	9		T516	3		T429	16
values[21]	920	1			T520	7		T516	2		T429	29
values[22]	882	1			T520	8		T516	2		T429	28
values[23]	874	1			T520	5		T516	3		T429	30
values[24]	821	1			T520	2		T516	1		T429	15
values[25]	739	1			T520	2		T516	1		T429	10
values[26]	750	1			T520	3		T516	2		T429	6
values[27]	741	1			T520	5		T516	2		T429	4
values[28]	649	1			T520	4		T516	1		T429	7
values[29]	646	1			T520	2		T516	1		T429	3
values[30]	595	1			T520	2		T516	4		T429	7
values[31]	542	1			T520	6		T516	1		T429	10
values[32]	553	1			T520	3		T516	3		T429	20
values[33]	547	1			T520	4		T516	1		T429	17
values[34]	516	1			T520	2		T516	1		T429	24
values[35]	479	1			T520	7		T516	1		T429	17
values[36]	468	1			T520	9		T516	1		T429	13
values[37]	471	1			T520	4		T516	1		T429	14
values[38]	421	1			T520	5		T516	2		T429	6
values[39]	416	1			T520	2		T516	1		T429	10
values[40]	443	1			T520	5		T516	1		T429	7
values[41]	430	1			T520	4		T516	1		T429	7
values[42]	439	1			T520	4		T516	1		T429	6
values[43]	436	1			T520	3		T516	1		T429	6
values[44]	437	1			T520	3		T516	1		T429	4
values[45]	427	1			T520	4		T516	3		T429	12
values[46]	390	1			T520	6		T516	5		T429	7
values[47]	375	1			T520	4		T516	2		T429	4
values[48]	390	1			T520	4		T516	2		T429	6
values[49]	384	1			T520	5		T516	1		T429	9
values[50]	353	1			T520	4		T516	2		T429	6
values[51]	360	1			T520	8		T516	1		T429	5
values[52]	386	1			T520	4		T516	2		T429	9
values[53]	350	1			T520	2		T516	5		T429	6
values[54]	371	1			T520	2		T516	1		T429	5
values[55]	334	1			T520	2		T516	3		T429	7
values[56]	356	1			T520	4		T516	2		T429	7
values[57]	362	1			T520	2		T516	1		T429	8
values[58]	343	1			T520	3		T516	1		T429	6
values[59]	344	1			T520	3		T516	2		T429	4
values[60]	328	1			T520	3		T516	6		T429	4
values[61]	363	1			T520	6		T516	2		T429	6
values[62]	655	1			T520	12		T516	1		T429	11
values[63]	2434	1			T520	42		T516	2		T429	56
values[64]	27397	1			T520	147		T516	134		T429	133

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	548590	1			T80	1		T81	947		T82	1
values[2]	2527180	1			T80	86		T81	3136		T82	118
values[3]	1200527	1			T80	64		T81	4263		T82	32
values[4]	147543	1			T80	4		T81	439		T88	107
values[5]	77189	1			T81	240		T88	51		T520	202
values[6]	50640	1			T81	171		T88	32		T520	134
values[7]	36521	1			T81	90		T88	19		T520	69
values[8]	28862	1			T81	78		T88	23		T520	37
values[9]	23681	1			T81	75		T88	7		T520	34
values[10]	20680	1			T81	50		T88	10		T520	32
values[11]	18828	1			T81	29		T88	13		T520	22
values[12]	17191	1			T81	16		T88	11		T520	36
values[13]	15887	1			T81	15		T88	10		T520	29
values[14]	14762	1			T81	9		T88	4		T520	28
values[15]	14188	1			T81	28		T88	15		T520	41
values[16]	13586	1			T81	32		T88	9		T520	62
values[17]	13074	1			T81	33		T88	1		T520	39
values[18]	12308	1			T81	20		T88	5		T520	33
values[19]	11696	1			T81	26		T88	2		T520	35
values[20]	11231	1			T81	16		T88	2		T520	27
values[21]	10819	1			T81	28		T88	3		T520	31
values[22]	10607	1			T81	26		T88	14		T520	30
values[23]	10176	1			T81	22		T88	22		T520	27
values[24]	9594	1			T81	7		T88	10		T520	13
values[25]	9246	1			T81	9		T88	5		T520	6
values[26]	9008	1			T81	15		T88	6		T520	10
values[27]	8285	1			T81	19		T88	4		T520	9
values[28]	7916	1			T81	36		T88	3		T520	18
values[29]	7357	1			T81	11		T88	1		T520	10
values[30]	6922	1			T81	9		T88	1		T520	11
values[31]	6342	1			T81	7		T520	14		T511	23
values[32]	5918	1			T81	6		T520	11		T511	35
values[33]	5377	1			T81	4		T520	15		T511	39
values[34]	5062	1			T81	4		T520	13		T511	31
values[35]	4729	1			T81	7		T520	6		T511	29
values[36]	4643	1			T81	11		T520	6		T511	56
values[37]	4371	1			T81	11		T520	14		T511	28
values[38]	4144	1			T81	9		T520	13		T511	35
values[39]	3871	1			T81	9		T520	12		T511	12
values[40]	3679	1			T81	4		T520	12		T511	9
values[41]	3638	1			T81	5		T520	11		T511	5
values[42]	3616	1			T81	3		T520	14		T511	11
values[43]	3456	1			T81	2		T520	13		T511	9
values[44]	3327	1			T81	3		T520	9		T511	6
values[45]	3303	1			T81	5		T520	19		T511	3
values[46]	3328	1			T81	8		T520	17		T511	8
values[47]	3228	1			T81	8		T520	10		T511	5
values[48]	3226	1			T81	7		T520	14		T511	8
values[49]	3262	1			T81	7		T520	14		T511	6
values[50]	3173	1			T81	8		T520	12		T511	2
values[51]	3091	1			T81	5		T520	10		T511	7
values[52]	2968	1			T81	8		T520	10		T511	3
values[53]	2939	1			T81	7		T520	12		T511	14
values[54]	2964	1			T81	7		T520	11		T511	1
values[55]	2949	1			T81	9		T520	11		T511	2
values[56]	2866	1			T81	6		T520	10		T511	4
values[57]	2816	1			T81	7		T520	11		T511	2
values[58]	2680	1			T81	4		T520	14		T517	8
values[59]	2625	1			T81	3		T520	10		T517	5
values[60]	2749	1			T81	2		T520	9		T517	4
values[61]	2757	1			T81	4		T520	13		T517	1
values[62]	3653	1			T81	14		T520	36		T517	6
values[63]	8936	1			T81	29		T520	81		T517	7
values[64]	209905	1			T81	71		T520	319		T517	13