Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2122094	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

37880687

1

T2

8950

T3

290382

T4

5246

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	28028716	1			T2	4444		T3	200337		T4	2043
values[0x0]	10538696	1			T2	4506		T3	90045		T4	3203
values[0x1]	1435369	1			T2	571		T3	7881		T4	311

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	785032	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

39217749

1

T2

9521

T3

298263

T4

5557

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	18643124	1			T2	4761		T3	149132		T4	2779
valid_sources[0x01]	18641234	1			T2	4760		T3	149131		T4	2778
valid_sources[0x02]	43395	1			T86	1		T360	3155		T421	6
valid_sources[0x03]	44684	1			T85	1		T360	3166		T421	482
valid_sources[0x04]	43705	1			T84	2		T360	3201		T147	355
valid_sources[0x05]	45742	1			T85	2		T86	1		T205	3
valid_sources[0x06]	43824	1			T205	1		T360	3209		T147	392
valid_sources[0x07]	43313	1			T205	2		T360	3207		T421	11
valid_sources[0x08]	44812	1			T84	1		T205	2		T360	3319
valid_sources[0x09]	43217	1			T84	3		T85	1		T86	1
valid_sources[0x0a]	43536	1			T86	1		T205	1		T360	3207
valid_sources[0x0b]	43157	1			T84	1		T85	1		T360	3199
valid_sources[0x0c]	44363	1			T86	1		T360	3244		T421	4
valid_sources[0x0d]	43673	1			T84	3		T360	3225		T421	11
valid_sources[0x0e]	45506	1			T205	1		T360	3304		T147	382
valid_sources[0x0f]	44496	1			T85	1		T360	3230		T147	455
valid_sources[0x10]	44044	1			T85	2		T86	1		T360	3236
valid_sources[0x11]	44236	1			T85	1		T205	2		T360	3191
valid_sources[0x12]	43220	1			T360	3216		T421	9		T147	385
valid_sources[0x13]	43788	1			T360	3197		T421	4		T147	406
valid_sources[0x14]	44714	1			T84	2		T85	1		T360	3363
valid_sources[0x15]	42868	1			T85	3		T360	3245		T147	436
valid_sources[0x16]	42503	1			T84	1		T205	2		T360	3219
valid_sources[0x17]	43332	1			T84	2		T205	1		T360	3221
valid_sources[0x18]	43678	1			T86	1		T360	3254		T421	1
valid_sources[0x19]	44633	1			T59	39		T205	2		T360	3254
valid_sources[0x1a]	43686	1			T85	1		T86	1		T360	3226
valid_sources[0x1b]	43854	1			T86	3		T360	3291		T421	2
valid_sources[0x1c]	43862	1			T360	3360		T421	11		T147	422
valid_sources[0x1d]	43127	1			T205	1		T360	3307		T421	1
valid_sources[0x1e]	43508	1			T84	1		T85	1		T86	1
valid_sources[0x1f]	48016	1			T86	1		T360	3298		T147	360
valid_sources[0x20]	43932	1			T205	2		T360	3265		T147	428

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27129472

1

T2

4444

T3

200337

T4

2043

values[0x0]

all_enables

biggest_size

10486921

1

T2

4506

T3

90045

T4

3203

values[0x1]

all_enables

biggest_size

264294

1

T84

19

T85

22

T86

13

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2885466	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

457086

1

T80

24

T81

38

T82

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1130801	1			T80	37		T81	179		T82	4
values[0x0]	1081253	1			T80	44		T81	31		T82	2
values[0x1]	1130498	1			T80	45		T81	192		T82	8

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2235835	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1106717

1

T80

42

T81

149

T82

7

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51971	1			T80	3		T81	5		T88	17
valid_sources[0x01]	52432	1			T80	2		T81	7		T88	13
valid_sources[0x02]	52426	1			T80	1		T81	2		T89	2
valid_sources[0x03]	52832	1			T80	1		T81	9		T82	1
valid_sources[0x04]	52635	1			T80	4		T81	4		T88	19
valid_sources[0x05]	52999	1			T80	3		T81	10		T89	1
valid_sources[0x06]	52816	1			T81	2		T88	16		T520	36
valid_sources[0x07]	52788	1			T81	3		T88	5		T520	34
valid_sources[0x08]	51382	1			T80	2		T81	6		T89	1
valid_sources[0x09]	52121	1			T81	3		T87	14		T88	21
valid_sources[0x0a]	52638	1			T80	1		T81	7		T89	6
valid_sources[0x0b]	52752	1			T80	2		T81	6		T89	1
valid_sources[0x0c]	52038	1			T80	3		T81	5		T89	13
valid_sources[0x0d]	53171	1			T81	5		T89	6		T87	14
valid_sources[0x0e]	52159	1			T80	5		T81	5		T87	17
valid_sources[0x0f]	51907	1			T81	6		T89	7		T88	6
valid_sources[0x10]	52807	1			T80	2		T81	6		T87	24
valid_sources[0x11]	51272	1			T80	1		T81	10		T89	1
valid_sources[0x12]	51916	1			T81	6		T87	10		T88	10
valid_sources[0x13]	51133	1			T80	3		T81	5		T88	6
valid_sources[0x14]	53077	1			T80	1		T81	13		T89	5
valid_sources[0x15]	52515	1			T80	2		T81	9		T88	9
valid_sources[0x16]	52240	1			T80	1		T81	4		T82	1
valid_sources[0x17]	51666	1			T80	2		T81	5		T87	18
valid_sources[0x18]	51803	1			T80	1		T81	5		T89	1
valid_sources[0x19]	52474	1			T80	1		T81	9		T89	6
valid_sources[0x1a]	51929	1			T81	7		T89	7		T88	20
valid_sources[0x1b]	50182	1			T80	2		T81	5		T89	1
valid_sources[0x1c]	53105	1			T81	6		T89	3		T87	7
valid_sources[0x1d]	52426	1			T80	8		T81	7		T82	2
valid_sources[0x1e]	51992	1			T80	1		T81	4		T89	4
valid_sources[0x1f]	50902	1			T80	6		T81	6		T89	2
valid_sources[0x20]	51486	1			T81	4		T89	4		T88	15

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47633

1

T80

3

T81

11

T82

1

values[0x0]

all_enables

biggest_size

361665

1

T80

19

T81

18

T82

1

values[0x1]

all_enables

biggest_size

47788

1

T80

2

T81

9

T89

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3078850	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

500912

1

T80

19

T81

42

T89

35

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1224087	1			T80	58		T81	221		T82	2
values[0x0]	1131524	1			T80	42		T81	33		T89	60
values[0x1]	1224151	1			T80	55		T81	257		T82	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2364013	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1215749

1

T80

51

T81

182

T82

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	56791	1			T80	1		T81	14		T88	10
valid_sources[0x01]	56756	1			T81	9		T88	11		T520	45
valid_sources[0x02]	55461	1			T81	2		T89	7		T88	13
valid_sources[0x03]	56510	1			T81	8		T89	3		T88	10
valid_sources[0x04]	55735	1			T80	1		T81	10		T89	1
valid_sources[0x05]	55601	1			T81	5		T88	12		T520	33
valid_sources[0x06]	56587	1			T81	8		T88	23		T520	36
valid_sources[0x07]	56230	1			T80	4		T81	15		T89	5
valid_sources[0x08]	55430	1			T80	1		T81	5		T89	4
valid_sources[0x09]	56636	1			T80	4		T81	2		T89	11
valid_sources[0x0a]	56162	1			T80	1		T81	9		T82	1
valid_sources[0x0b]	56605	1			T80	1		T81	14		T87	14
valid_sources[0x0c]	55944	1			T80	1		T81	5		T88	16
valid_sources[0x0d]	56392	1			T80	4		T81	5		T82	2
valid_sources[0x0e]	55433	1			T81	10		T89	19		T87	10
valid_sources[0x0f]	55211	1			T80	1		T81	3		T88	26
valid_sources[0x10]	55125	1			T80	4		T81	12		T89	6
valid_sources[0x11]	54357	1			T80	4		T81	16		T82	1
valid_sources[0x12]	56919	1			T80	1		T81	9		T89	1
valid_sources[0x13]	55445	1			T80	3		T81	11		T88	18
valid_sources[0x14]	56176	1			T80	2		T81	5		T87	12
valid_sources[0x15]	56343	1			T80	2		T81	6		T82	1
valid_sources[0x16]	56415	1			T80	6		T81	2		T89	1
valid_sources[0x17]	55963	1			T80	3		T81	8		T87	5
valid_sources[0x18]	55468	1			T80	2		T81	9		T89	19
valid_sources[0x19]	56716	1			T80	2		T81	8		T88	13
valid_sources[0x1a]	55733	1			T81	2		T88	11		T520	32
valid_sources[0x1b]	56020	1			T81	14		T88	23		T520	29
valid_sources[0x1c]	57142	1			T80	3		T81	7		T89	7
valid_sources[0x1d]	57021	1			T81	9		T87	10		T88	23
valid_sources[0x1e]	55481	1			T81	7		T89	1		T88	15
valid_sources[0x1f]	55411	1			T80	6		T81	9		T88	10
valid_sources[0x20]	55582	1			T80	6		T81	6		T88	15

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

52329

1

T80

4

T81

10

T89

3

values[0x0]

all_enables

biggest_size

396218

1

T80

14

T81

13

T89

27

values[0x1]

all_enables

biggest_size

52365

1

T80

1

T81

19

T89

5

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2901950	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

459203

1

T80

20

T81

45

T82

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1136494	1			T80	59		T81	216		T82	1
values[0x0]	1087162	1			T80	51		T81	30		T89	30
values[0x1]	1137497	1			T80	45		T81	211		T82	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2248439	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1112714

1

T80

48

T81

182

T82

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	51824	1			T80	5		T81	10		T88	9
valid_sources[0x01]	52300	1			T81	5		T89	4		T88	18
valid_sources[0x02]	52620	1			T81	4		T88	15		T520	54
valid_sources[0x03]	53296	1			T80	4		T81	7		T88	16
valid_sources[0x04]	52573	1			T80	3		T81	5		T89	11
valid_sources[0x05]	51938	1			T81	13		T89	2		T88	12
valid_sources[0x06]	52240	1			T80	8		T81	12		T88	17
valid_sources[0x07]	53023	1			T80	6		T81	8		T89	8
valid_sources[0x08]	52204	1			T80	1		T81	7		T88	12
valid_sources[0x09]	52201	1			T81	6		T89	5		T87	17
valid_sources[0x0a]	52617	1			T80	7		T81	2		T88	14
valid_sources[0x0b]	52953	1			T80	6		T81	5		T87	5
valid_sources[0x0c]	52595	1			T80	1		T81	8		T88	17
valid_sources[0x0d]	52947	1			T81	7		T87	12		T88	18
valid_sources[0x0e]	53341	1			T80	2		T81	5		T87	14
valid_sources[0x0f]	52392	1			T81	7		T88	14		T520	18
valid_sources[0x10]	52342	1			T80	6		T81	7		T87	27
valid_sources[0x11]	52258	1			T80	4		T81	10		T89	6
valid_sources[0x12]	52742	1			T81	6		T87	18		T88	10
valid_sources[0x13]	51814	1			T81	6		T88	15		T520	42
valid_sources[0x14]	52761	1			T81	10		T87	5		T88	15
valid_sources[0x15]	52394	1			T81	3		T88	18		T520	43
valid_sources[0x16]	52173	1			T80	6		T81	6		T88	19
valid_sources[0x17]	52792	1			T80	3		T81	8		T89	4
valid_sources[0x18]	52845	1			T80	3		T81	9		T87	19
valid_sources[0x19]	52486	1			T81	6		T88	14		T520	34
valid_sources[0x1a]	52228	1			T80	3		T81	7		T89	10
valid_sources[0x1b]	52221	1			T80	2		T81	11		T88	10
valid_sources[0x1c]	52830	1			T81	3		T87	18		T88	12
valid_sources[0x1d]	51750	1			T81	8		T87	14		T88	12
valid_sources[0x1e]	53324	1			T80	3		T81	7		T88	14
valid_sources[0x1f]	51226	1			T80	1		T81	12		T89	2
valid_sources[0x20]	52043	1			T80	2		T81	7		T82	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

48060

1

T80

1

T81

17

T82

1

values[0x0]

all_enables

biggest_size

363296

1

T80

18

T81

13

T89

6

values[0x1]

all_enables

biggest_size

47847

1

T80

1

T81

15

T89

1