Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	525059025	60211441	0	0
DepthKnown_A	525059025	524950152	0	0
RvalidKnown_A	525059025	524950152	0	0
WreadyKnown_A	525059025	524950152	0	0
gen_passthru_fifo.paramCheckPass	1029	1029	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525059025	60211441	0	0
T2	161720	21802	0	0
T3	237772	255541	0	0
T4	93767	10412	0	0
T5	125982	13659	0	0
T6	128844	17891	0	0
T16	83082	8242	0	0
T34	173880	14322	0	0
T35	216073	12198	0	0
T95	143326	43709	0	0
T96	94372	7962	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525059025	524950152	0	0
T1	38883	38821	0	0
T2	161720	161658	0	0
T3	237772	237766	0	0
T4	93767	93716	0	0
T5	125982	125920	0	0
T6	128844	128793	0	0
T16	83082	83020	0	0
T34	173880	173778	0	0
T95	143326	143321	0	0
T96	94372	94314	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525059025	524950152	0	0
T1	38883	38821	0	0
T2	161720	161658	0	0
T3	237772	237766	0	0
T4	93767	93716	0	0
T5	125982	125920	0	0
T6	128844	128793	0	0
T16	83082	83020	0	0
T34	173880	173778	0	0
T95	143326	143321	0	0
T96	94372	94314	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525059025	524950152	0	0
T1	38883	38821	0	0
T2	161720	161658	0	0
T3	237772	237766	0	0
T4	93767	93716	0	0
T5	125982	125920	0	0
T6	128844	128793	0	0
T16	83082	83020	0	0
T34	173880	173778	0	0
T95	143326	143321	0	0
T96	94372	94314	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1029	1029	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T34	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	525059025	46309732	0	0
DepthKnown_A	525059025	524950152	0	0
RvalidKnown_A	525059025	524950152	0	0
WreadyKnown_A	525059025	524950152	0	0
gen_passthru_fifo.paramCheckPass	1029	1029	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525059025	46309732	0	0
T2	161720	16575	0	0
T3	237772	235527	0	0
T4	93767	8294	0	0
T5	125982	9067	0	0
T6	128844	12594	0	0
T16	83082	6340	0	0
T34	173880	10562	0	0
T35	216073	8213	0	0
T95	143326	39688	0	0
T96	94372	5505	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525059025	524950152	0	0
T1	38883	38821	0	0
T2	161720	161658	0	0
T3	237772	237766	0	0
T4	93767	93716	0	0
T5	125982	125920	0	0
T6	128844	128793	0	0
T16	83082	83020	0	0
T34	173880	173778	0	0
T95	143326	143321	0	0
T96	94372	94314	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525059025	524950152	0	0
T1	38883	38821	0	0
T2	161720	161658	0	0
T3	237772	237766	0	0
T4	93767	93716	0	0
T5	125982	125920	0	0
T6	128844	128793	0	0
T16	83082	83020	0	0
T34	173880	173778	0	0
T95	143326	143321	0	0
T96	94372	94314	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525059025	524950152	0	0
T1	38883	38821	0	0
T2	161720	161658	0	0
T3	237772	237766	0	0
T4	93767	93716	0	0
T5	125982	125920	0	0
T6	128844	128793	0	0
T16	83082	83020	0	0
T34	173880	173778	0	0
T95	143326	143321	0	0
T96	94372	94314	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1029	1029	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T34	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	525059025	44295506	0	0
DepthKnown_A	525059025	524950152	0	0
RvalidKnown_A	525059025	524950152	0	0
WreadyKnown_A	525059025	524950152	0	0
gen_passthru_fifo.paramCheckPass	1029	1029	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525059025	44295506	0	0
T2	161720	9801	0	0
T3	237772	379287	0	0
T4	93767	5697	0	0
T5	125982	5678	0	0
T6	128844	6858	0	0
T16	83082	5747	0	0
T34	173880	8223	0	0
T35	216073	6410	0	0
T95	143326	33132	0	0
T96	94372	3920	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525059025	524950152	0	0
T1	38883	38821	0	0
T2	161720	161658	0	0
T3	237772	237766	0	0
T4	93767	93716	0	0
T5	125982	125920	0	0
T6	128844	128793	0	0
T16	83082	83020	0	0
T34	173880	173778	0	0
T95	143326	143321	0	0
T96	94372	94314	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525059025	524950152	0	0
T1	38883	38821	0	0
T2	161720	161658	0	0
T3	237772	237766	0	0
T4	93767	93716	0	0
T5	125982	125920	0	0
T6	128844	128793	0	0
T16	83082	83020	0	0
T34	173880	173778	0	0
T95	143326	143321	0	0
T96	94372	94314	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525059025	524950152	0	0
T1	38883	38821	0	0
T2	161720	161658	0	0
T3	237772	237766	0	0
T4	93767	93716	0	0
T5	125982	125920	0	0
T6	128844	128793	0	0
T16	83082	83020	0	0
T34	173880	173778	0	0
T95	143326	143321	0	0
T96	94372	94314	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1029	1029	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T34	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	525059025	37298587	0	0
DepthKnown_A	525059025	524950152	0	0
RvalidKnown_A	525059025	524950152	0	0
WreadyKnown_A	525059025	524950152	0	0
gen_passthru_fifo.paramCheckPass	1029	1029	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525059025	37298587	0	0
T2	161720	9521	0	0
T3	237772	298263	0	0
T4	93767	5557	0	0
T5	125982	5397	0	0
T6	128844	6574	0	0
T16	83082	5625	0	0
T34	173880	7978	0	0
T35	216073	6158	0	0
T95	143326	32957	0	0
T96	94372	3768	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525059025	524950152	0	0
T1	38883	38821	0	0
T2	161720	161658	0	0
T3	237772	237766	0	0
T4	93767	93716	0	0
T5	125982	125920	0	0
T6	128844	128793	0	0
T16	83082	83020	0	0
T34	173880	173778	0	0
T95	143326	143321	0	0
T96	94372	94314	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525059025	524950152	0	0
T1	38883	38821	0	0
T2	161720	161658	0	0
T3	237772	237766	0	0
T4	93767	93716	0	0
T5	125982	125920	0	0
T6	128844	128793	0	0
T16	83082	83020	0	0
T34	173880	173778	0	0
T95	143326	143321	0	0
T96	94372	94314	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	525059025	524950152	0	0
T1	38883	38821	0	0
T2	161720	161658	0	0
T3	237772	237766	0	0
T4	93767	93716	0	0
T5	125982	125920	0	0
T6	128844	128793	0	0
T16	83082	83020	0	0
T34	173880	173778	0	0
T95	143326	143321	0	0
T96	94372	94314	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1029	1029	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T34	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	614411823	90350	0	0
DepthKnown_A	614411823	614287375	0	0
RvalidKnown_A	614411823	614287375	0	0
WreadyKnown_A	614411823	614287375	0	0
gen_passthru_fifo.paramCheckPass	2940	2940	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614411823	90350	0	0
T2	161720	26	0	0
T3	237772	57	0	0
T4	93767	18	0	0
T5	125982	39	0	0
T6	128844	26	0	0
T16	83082	13	0	0
T34	173880	30	0	0
T35	216073	29	0	0
T95	143326	29	0	0
T96	94372	21	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614411823	614287375	0	0
T1	38883	38821	0	0
T2	161720	161658	0	0
T3	237772	237766	0	0
T4	93767	93716	0	0
T5	125982	125920	0	0
T6	128844	128793	0	0
T16	83082	83020	0	0
T34	173880	173778	0	0
T95	143326	143321	0	0
T96	94372	94314	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614411823	614287375	0	0
T1	38883	38821	0	0
T2	161720	161658	0	0
T3	237772	237766	0	0
T4	93767	93716	0	0
T5	125982	125920	0	0
T6	128844	128793	0	0
T16	83082	83020	0	0
T34	173880	173778	0	0
T95	143326	143321	0	0
T96	94372	94314	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614411823	614287375	0	0
T1	38883	38821	0	0
T2	161720	161658	0	0
T3	237772	237766	0	0
T4	93767	93716	0	0
T5	125982	125920	0	0
T6	128844	128793	0	0
T16	83082	83020	0	0
T34	173880	173778	0	0
T95	143326	143321	0	0
T96	94372	94314	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2940	2940	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T34	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	614411823	91096	0	0
DepthKnown_A	614411823	614287375	0	0
RvalidKnown_A	614411823	614287375	0	0
WreadyKnown_A	614411823	614287375	0	0
gen_passthru_fifo.paramCheckPass	2940	2940	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614411823	91096	0	0
T2	161720	26	0	0
T3	237772	57	0	0
T4	93767	18	0	0
T5	125982	39	0	0
T6	128844	26	0	0
T16	83082	13	0	0
T34	173880	30	0	0
T35	216073	29	0	0
T95	143326	29	0	0
T96	94372	21	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614411823	614287375	0	0
T1	38883	38821	0	0
T2	161720	161658	0	0
T3	237772	237766	0	0
T4	93767	93716	0	0
T5	125982	125920	0	0
T6	128844	128793	0	0
T16	83082	83020	0	0
T34	173880	173778	0	0
T95	143326	143321	0	0
T96	94372	94314	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614411823	614287375	0	0
T1	38883	38821	0	0
T2	161720	161658	0	0
T3	237772	237766	0	0
T4	93767	93716	0	0
T5	125982	125920	0	0
T6	128844	128793	0	0
T16	83082	83020	0	0
T34	173880	173778	0	0
T95	143326	143321	0	0
T96	94372	94314	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614411823	614287375	0	0
T1	38883	38821	0	0
T2	161720	161658	0	0
T3	237772	237766	0	0
T4	93767	93716	0	0
T5	125982	125920	0	0
T6	128844	128793	0	0
T16	83082	83020	0	0
T34	173880	173778	0	0
T95	143326	143321	0	0
T96	94372	94314	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2940	2940	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T34	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	614411823	51808	0	0
DepthKnown_A	614411823	614287375	0	0
RvalidKnown_A	614411823	614287375	0	0
WreadyKnown_A	614411823	614287375	0	0
gen_passthru_fifo.paramCheckPass	2940	2940	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614411823	51808	0	0
T2	161720	23	0	0
T3	237772	26	0	0
T4	93767	17	0	0
T5	125982	32	0	0
T6	128844	23	0	0
T16	83082	12	0	0
T34	173880	28	0	0
T35	216073	25	0	0
T95	143326	28	0	0
T96	94372	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614411823	614287375	0	0
T1	38883	38821	0	0
T2	161720	161658	0	0
T3	237772	237766	0	0
T4	93767	93716	0	0
T5	125982	125920	0	0
T6	128844	128793	0	0
T16	83082	83020	0	0
T34	173880	173778	0	0
T95	143326	143321	0	0
T96	94372	94314	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614411823	614287375	0	0
T1	38883	38821	0	0
T2	161720	161658	0	0
T3	237772	237766	0	0
T4	93767	93716	0	0
T5	125982	125920	0	0
T6	128844	128793	0	0
T16	83082	83020	0	0
T34	173880	173778	0	0
T95	143326	143321	0	0
T96	94372	94314	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614411823	614287375	0	0
T1	38883	38821	0	0
T2	161720	161658	0	0
T3	237772	237766	0	0
T4	93767	93716	0	0
T5	125982	125920	0	0
T6	128844	128793	0	0
T16	83082	83020	0	0
T34	173880	173778	0	0
T95	143326	143321	0	0
T96	94372	94314	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2940	2940	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T34	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	614411823	51811	0	0
DepthKnown_A	614411823	614287375	0	0
RvalidKnown_A	614411823	614287375	0	0
WreadyKnown_A	614411823	614287375	0	0
gen_passthru_fifo.paramCheckPass	2940	2940	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614411823	51811	0	0
T2	161720	23	0	0
T3	237772	26	0	0
T4	93767	17	0	0
T5	125982	32	0	0
T6	128844	23	0	0
T16	83082	12	0	0
T34	173880	28	0	0
T35	216073	25	0	0
T95	143326	28	0	0
T96	94372	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614411823	614287375	0	0
T1	38883	38821	0	0
T2	161720	161658	0	0
T3	237772	237766	0	0
T4	93767	93716	0	0
T5	125982	125920	0	0
T6	128844	128793	0	0
T16	83082	83020	0	0
T34	173880	173778	0	0
T95	143326	143321	0	0
T96	94372	94314	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614411823	614287375	0	0
T1	38883	38821	0	0
T2	161720	161658	0	0
T3	237772	237766	0	0
T4	93767	93716	0	0
T5	125982	125920	0	0
T6	128844	128793	0	0
T16	83082	83020	0	0
T34	173880	173778	0	0
T95	143326	143321	0	0
T96	94372	94314	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614411823	614287375	0	0
T1	38883	38821	0	0
T2	161720	161658	0	0
T3	237772	237766	0	0
T4	93767	93716	0	0
T5	125982	125920	0	0
T6	128844	128793	0	0
T16	83082	83020	0	0
T34	173880	173778	0	0
T95	143326	143321	0	0
T96	94372	94314	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2940	2940	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T34	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	614411823	38542	0	0
DepthKnown_A	614411823	614287375	0	0
RvalidKnown_A	614411823	614287375	0	0
WreadyKnown_A	614411823	614287375	0	0
gen_passthru_fifo.paramCheckPass	2940	2940	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614411823	38542	0	0
T2	161720	3	0	0
T3	237772	31	0	0
T4	93767	1	0	0
T5	125982	7	0	0
T6	128844	3	0	0
T16	83082	1	0	0
T34	173880	2	0	0
T35	216073	4	0	0
T95	143326	1	0	0
T96	94372	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614411823	614287375	0	0
T1	38883	38821	0	0
T2	161720	161658	0	0
T3	237772	237766	0	0
T4	93767	93716	0	0
T5	125982	125920	0	0
T6	128844	128793	0	0
T16	83082	83020	0	0
T34	173880	173778	0	0
T95	143326	143321	0	0
T96	94372	94314	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614411823	614287375	0	0
T1	38883	38821	0	0
T2	161720	161658	0	0
T3	237772	237766	0	0
T4	93767	93716	0	0
T5	125982	125920	0	0
T6	128844	128793	0	0
T16	83082	83020	0	0
T34	173880	173778	0	0
T95	143326	143321	0	0
T96	94372	94314	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614411823	614287375	0	0
T1	38883	38821	0	0
T2	161720	161658	0	0
T3	237772	237766	0	0
T4	93767	93716	0	0
T5	125982	125920	0	0
T6	128844	128793	0	0
T16	83082	83020	0	0
T34	173880	173778	0	0
T95	143326	143321	0	0
T96	94372	94314	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2940	2940	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T34	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	614411823	39285	0	0
DepthKnown_A	614411823	614287375	0	0
RvalidKnown_A	614411823	614287375	0	0
WreadyKnown_A	614411823	614287375	0	0
gen_passthru_fifo.paramCheckPass	2940	2940	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614411823	39285	0	0
T2	161720	3	0	0
T3	237772	31	0	0
T4	93767	1	0	0
T5	125982	7	0	0
T6	128844	3	0	0
T16	83082	1	0	0
T34	173880	2	0	0
T35	216073	4	0	0
T95	143326	1	0	0
T96	94372	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614411823	614287375	0	0
T1	38883	38821	0	0
T2	161720	161658	0	0
T3	237772	237766	0	0
T4	93767	93716	0	0
T5	125982	125920	0	0
T6	128844	128793	0	0
T16	83082	83020	0	0
T34	173880	173778	0	0
T95	143326	143321	0	0
T96	94372	94314	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614411823	614287375	0	0
T1	38883	38821	0	0
T2	161720	161658	0	0
T3	237772	237766	0	0
T4	93767	93716	0	0
T5	125982	125920	0	0
T6	128844	128793	0	0
T16	83082	83020	0	0
T34	173880	173778	0	0
T95	143326	143321	0	0
T96	94372	94314	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	614411823	614287375	0	0
T1	38883	38821	0	0
T2	161720	161658	0	0
T3	237772	237766	0	0
T4	93767	93716	0	0
T5	125982	125920	0	0
T6	128844	128793	0	0
T16	83082	83020	0	0
T34	173880	173778	0	0
T95	143326	143321	0	0
T96	94372	94314	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2940	2940	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T34	1	1	0	0
T95	1	1	0	0
T96	1	1	0	0