Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T34,T35,T36	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T3,T35,T121	Yes	T3,T35,T121	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T3,T35,T121	Yes	T3,T35,T121	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T51,*T69,*T83	Yes	T51,T69,T83	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
tl_i.a_valid	Yes	Yes	T3,T35,T121	Yes	T3,T35,T121	INPUT
tl_o.a_ready	Yes	Yes	T3,T121,T8	Yes	T3,T121,T8	OUTPUT
tl_o.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T3,T121,T8	Yes	T3,T121,T8	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T3,T121,T8	Yes	T3,T121,T8	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T3,T121,T8	Yes	T3,T121,T8	OUTPUT
tl_o.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T412,*T664,*T665	Yes	T412,T664,T665	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T3,*T121,*T8	Yes	T3,T121,T8	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T3,T121,T8	Yes	T3,T121,T8	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T90,T666,T300	Yes	T90,T666,T300	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T90,T92,T650	Yes	T90,T92,T159	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T90,T92,T159	Yes	T90,T92,T650	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T90,T666,T300	Yes	T90,T666,T300	OUTPUT
cio_rx_i	Yes	Yes	T34,T35,T36	Yes	T2,T4,T5	INPUT
cio_tx_o	Yes	Yes	T3,T121,T8	Yes	T3,T121,T8	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T121,T8,T151	Yes	T121,T8,T151	OUTPUT
intr_tx_empty_o	Yes	Yes	T121,T8,T151	Yes	T121,T8,T151	OUTPUT
intr_rx_watermark_o	Yes	Yes	T121,T8,T151	Yes	T121,T8,T151	OUTPUT
intr_tx_done_o	Yes	Yes	T121,T8,T151	Yes	T121,T8,T151	OUTPUT
intr_rx_overflow_o	Yes	Yes	T121,T8,T151	Yes	T121,T8,T151	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T316,T307,T302	Yes	T316,T307,T302	OUTPUT
intr_rx_break_err_o	Yes	Yes	T316,T307,T302	Yes	T316,T307,T302	OUTPUT
intr_rx_timeout_o	Yes	Yes	T316,T307,T302	Yes	T316,T307,T302	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T316,T307,T302	Yes	T316,T307,T302	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T34,T35,T36	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T3,T35,T121	Yes	T3,T35,T121	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T3,T35,T121	Yes	T3,T35,T121	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T51,*T69,*T83	Yes	T51,T69,T83	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
tl_i.a_valid	Yes	Yes	T3,T35,T121	Yes	T3,T35,T121	INPUT
tl_o.a_ready	Yes	Yes	T3,T121,T321	Yes	T3,T121,T321	OUTPUT
tl_o.d_error	Yes	Yes	T80,T81,T89	Yes	T80,T81,T89	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T3,T121,T49	Yes	T3,T121,T49	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T3,T121,T321	Yes	T3,T121,T321	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T3,T121,T321	Yes	T3,T121,T321	OUTPUT
tl_o.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T412,*T664,*T665	Yes	T412,T664,T665	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T3,*T121,*T321	Yes	T3,T121,T321	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T3,T121,T321	Yes	T3,T121,T321	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T90,T92,T161	Yes	T90,T92,T161	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T90,T92,T159	Yes	T90,T92,T159	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T90,T92,T159	Yes	T90,T92,T159	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T90,T92,T161	Yes	T90,T92,T161	OUTPUT
cio_rx_i	Yes	Yes	T34,T35,T36	Yes	T2,T4,T5	INPUT
cio_tx_o	Yes	Yes	T3,T121,T49	Yes	T3,T121,T49	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T121,T287,T288	Yes	T121,T287,T288	OUTPUT
intr_tx_empty_o	Yes	Yes	T121,T287,T314	Yes	T121,T287,T314	OUTPUT
intr_rx_watermark_o	Yes	Yes	T121,T287,T314	Yes	T121,T287,T314	OUTPUT
intr_tx_done_o	Yes	Yes	T121,T321,T287	Yes	T121,T321,T287	OUTPUT
intr_rx_overflow_o	Yes	Yes	T121,T321,T287	Yes	T121,T321,T287	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T316,T307,T302	Yes	T316,T307,T302	OUTPUT
intr_rx_break_err_o	Yes	Yes	T316,T307,T302	Yes	T316,T307,T302	OUTPUT
intr_rx_timeout_o	Yes	Yes	T316,T307,T302	Yes	T316,T307,T302	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T316,T307,T302	Yes	T316,T307,T302	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T34,T35,T36	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T214,T215,T216	Yes	T214,T215,T216	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T214,T215,T216	Yes	T214,T215,T216	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T51,*T69,*T83	Yes	T51,T69,T83	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
tl_i.a_valid	Yes	Yes	T214,T215,T216	Yes	T214,T215,T216	INPUT
tl_o.a_ready	Yes	Yes	T214,T215,T216	Yes	T214,T215,T216	OUTPUT
tl_o.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T214,T215,T216	Yes	T214,T215,T216	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T214,T215,T216	Yes	T214,T215,T216	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T214,T215,T216	Yes	T214,T215,T216	OUTPUT
tl_o.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T81,*T82,*T87	Yes	T80,T81,T82	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T81,T82,T89	Yes	T81,T82,T87	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T214,*T215,*T216	Yes	T214,T215,T216	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T214,T215,T216	Yes	T214,T215,T216	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T90,T300,T92	Yes	T90,T300,T92	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T90,T92,T650	Yes	T90,T92,T159	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T90,T92,T159	Yes	T90,T92,T650	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T90,T300,T92	Yes	T90,T300,T92	OUTPUT
cio_rx_i	Yes	Yes	T214,T215,T216	Yes	T214,T215,T216	INPUT
cio_tx_o	Yes	Yes	T214,T215,T216	Yes	T214,T215,T216	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T214,T215,T216	Yes	T214,T215,T216	OUTPUT
intr_tx_empty_o	Yes	Yes	T214,T215,T216	Yes	T214,T215,T216	OUTPUT
intr_rx_watermark_o	Yes	Yes	T214,T215,T216	Yes	T214,T215,T216	OUTPUT
intr_tx_done_o	Yes	Yes	T214,T215,T216	Yes	T214,T215,T216	OUTPUT
intr_rx_overflow_o	Yes	Yes	T214,T215,T216	Yes	T214,T215,T216	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T316,T307,T302	Yes	T316,T307,T302	OUTPUT
intr_rx_break_err_o	Yes	Yes	T316,T307,T302	Yes	T316,T307,T302	OUTPUT
intr_rx_timeout_o	Yes	Yes	T316,T307,T302	Yes	T316,T307,T302	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T316,T307,T302	Yes	T316,T307,T302	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T34,T35,T36	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T8,T151,T315	Yes	T8,T151,T315	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T8,T151,T315	Yes	T8,T151,T315	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T51,*T69,*T83	Yes	T51,T69,T83	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
tl_i.a_valid	Yes	Yes	T8,T151,T315	Yes	T8,T151,T315	INPUT
tl_o.a_ready	Yes	Yes	T8,T151,T315	Yes	T8,T151,T315	OUTPUT
tl_o.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T8,T151,T315	Yes	T8,T151,T315	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T8,T151,T315	Yes	T8,T151,T315	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T8,T151,T315	Yes	T8,T151,T315	OUTPUT
tl_o.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T81,*T82,*T87	Yes	T80,T81,T82	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T81,T82,T87	Yes	T81,T82,T87	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T8,*T151,*T315	Yes	T8,T151,T315	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T8,T151,T315	Yes	T8,T151,T315	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T90,T666,T92	Yes	T90,T666,T92	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T90,T92,T159	Yes	T90,T92,T159	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T90,T92,T159	Yes	T90,T92,T159	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T90,T666,T92	Yes	T90,T666,T92	OUTPUT
cio_rx_i	Yes	Yes	T8,T151,T315	Yes	T8,T151,T315	INPUT
cio_tx_o	Yes	Yes	T8,T151,T315	Yes	T8,T151,T315	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T8,T151,T315	Yes	T8,T151,T315	OUTPUT
intr_tx_empty_o	Yes	Yes	T8,T151,T315	Yes	T8,T151,T315	OUTPUT
intr_rx_watermark_o	Yes	Yes	T8,T151,T315	Yes	T8,T151,T315	OUTPUT
intr_tx_done_o	Yes	Yes	T8,T151,T315	Yes	T8,T151,T315	OUTPUT
intr_rx_overflow_o	Yes	Yes	T8,T151,T315	Yes	T8,T151,T315	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T316,T307,T302	Yes	T316,T307,T302	OUTPUT
intr_rx_break_err_o	Yes	Yes	T316,T307,T302	Yes	T316,T307,T302	OUTPUT
intr_rx_timeout_o	Yes	Yes	T316,T307,T302	Yes	T316,T307,T302	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T316,T307,T302	Yes	T316,T307,T302	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T34,T35,T36	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T18,T303,T304	Yes	T18,T303,T304	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T18,T303,T304	Yes	T18,T303,T304	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T51,*T69,*T83	Yes	T51,T69,T83	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
tl_i.a_valid	Yes	Yes	T18,T161,T303	Yes	T18,T161,T303	INPUT
tl_o.a_ready	Yes	Yes	T18,T161,T303	Yes	T18,T161,T303	OUTPUT
tl_o.d_error	Yes	Yes	T80,T81,T87	Yes	T80,T81,T87	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T18,T303,T304	Yes	T18,T303,T304	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T18,T161,T303	Yes	T18,T161,T303	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T18,T161,T303	Yes	T18,T161,T303	OUTPUT
tl_o.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T87	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T80,*T81,*T87	Yes	T80,T81,T89	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T18,*T303,*T304	Yes	T18,T303,T304	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T18,T161,T303	Yes	T18,T161,T303	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T90,T92,T667	Yes	T90,T92,T667	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T90,T92,T159	Yes	T90,T92,T159	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T90,T92,T159	Yes	T90,T92,T159	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T90,T92,T667	Yes	T90,T92,T667	OUTPUT
cio_rx_i	Yes	Yes	T18,T303,T304	Yes	T18,T303,T304	INPUT
cio_tx_o	Yes	Yes	T18,T303,T304	Yes	T18,T303,T304	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T18,T303,T304	Yes	T18,T303,T304	OUTPUT
intr_tx_empty_o	Yes	Yes	T18,T303,T304	Yes	T18,T303,T304	OUTPUT
intr_rx_watermark_o	Yes	Yes	T18,T303,T304	Yes	T18,T303,T304	OUTPUT
intr_tx_done_o	Yes	Yes	T18,T303,T304	Yes	T18,T303,T304	OUTPUT
intr_rx_overflow_o	Yes	Yes	T18,T303,T304	Yes	T18,T303,T304	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T316,T307,T302	Yes	T316,T307,T302	OUTPUT
intr_rx_break_err_o	Yes	Yes	T316,T307,T302	Yes	T316,T307,T302	OUTPUT
intr_rx_timeout_o	Yes	Yes	T316,T307,T302	Yes	T316,T307,T302	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T316,T307,T302	Yes	T316,T307,T302	OUTPUT

*Tests covering at least one bit in the range