Unified Coverage Report :: Module :: xbar_peri

Module : xbar_peri

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_peri	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_peri

	Total	Covered	Percent
Totals	562	562	100.00
Total Bits	7060	7060	100.00
Total Bits 0->1	3530	3530	100.00
Total Bits 1->0	3530	3530	100.00

Ports	562	562	100.00
Port Bits	7060	7060	100.00
Port Bits 0->1	3530	3530	100.00
Port Bits 1->0	3530	3530	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_peri_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_peri_ni	Yes	Yes	T34,T35,T36	Yes	T1,T2,T3	INPUT
tl_main_i.d_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_main_i.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_main_i.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_main_i.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_main_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_main_i.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_main_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_source[5:0]	Yes	Yes	*T51,*T69,*T83	Yes	T51,T69,T83	INPUT
tl_main_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_main_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_opcode[2:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	INPUT
tl_main_i.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_main_o.a_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_main_o.d_error	Yes	Yes	T195,T220,T666	Yes	T195,T220,T666	OUTPUT
tl_main_o.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_main_o.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_main_o.d_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_main_o.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_main_o.d_source[5:0]	Yes	Yes	*T51,*T69,*T83	Yes	T51,T69,T83	OUTPUT
tl_main_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_main_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_opcode[0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	OUTPUT
tl_main_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_uart0_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_uart0_o.a_user.data_intg[6:0]	Yes	Yes	T3,T35,T121	Yes	T3,T35,T121	OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_uart0_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_uart0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_data[31:0]	Yes	Yes	T3,T35,T121	Yes	T3,T35,T121	OUTPUT
tl_uart0_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_uart0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_source[5:0]	Yes	Yes	*T51,*T69,*T83	Yes	T51,T69,T83	OUTPUT
tl_uart0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_uart0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_opcode[2:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_uart0_o.a_valid	Yes	Yes	T3,T35,T121	Yes	T3,T35,T121	OUTPUT
tl_uart0_i.a_ready	Yes	Yes	T3,T121,T321	Yes	T3,T121,T321	INPUT
tl_uart0_i.d_error	Yes	Yes	T80,T81,T89	Yes	T80,T81,T89	INPUT
tl_uart0_i.d_user.data_intg[6:0]	Yes	Yes	T3,T121,T49	Yes	T3,T121,T49	INPUT
tl_uart0_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T121,T321	Yes	T3,T121,T321	INPUT
tl_uart0_i.d_data[31:0]	Yes	Yes	T3,T121,T321	Yes	T3,T121,T321	INPUT
tl_uart0_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_uart0_i.d_source[5:0]	Yes	Yes	*T412,*T664,*T665	Yes	T412,T664,T665	INPUT
tl_uart0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_uart0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_opcode[0]	Yes	Yes	*T3,*T121,*T321	Yes	T3,T121,T321	INPUT
tl_uart0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_valid	Yes	Yes	T3,T121,T321	Yes	T3,T121,T321	INPUT
tl_uart1_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_uart1_o.a_user.data_intg[6:0]	Yes	Yes	T214,T215,T216	Yes	T214,T215,T216	OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_uart1_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_uart1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_data[31:0]	Yes	Yes	T214,T215,T216	Yes	T214,T215,T216	OUTPUT
tl_uart1_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_uart1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_source[5:0]	Yes	Yes	*T51,*T69,*T83	Yes	T51,T69,T83	OUTPUT
tl_uart1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_uart1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_opcode[2:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_uart1_o.a_valid	Yes	Yes	T214,T215,T216	Yes	T214,T215,T216	OUTPUT
tl_uart1_i.a_ready	Yes	Yes	T214,T215,T216	Yes	T214,T215,T216	INPUT
tl_uart1_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_uart1_i.d_user.data_intg[6:0]	Yes	Yes	T214,T215,T216	Yes	T214,T215,T216	INPUT
tl_uart1_i.d_user.rsp_intg[6:0]	Yes	Yes	T214,T215,T216	Yes	T214,T215,T216	INPUT
tl_uart1_i.d_data[31:0]	Yes	Yes	T214,T215,T216	Yes	T214,T215,T216	INPUT
tl_uart1_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_uart1_i.d_source[5:0]	Yes	Yes	*T81,*T82,*T87	Yes	T80,T81,T82	INPUT
tl_uart1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_size[1:0]	Yes	Yes	T81,T82,T89	Yes	T81,T82,T87	INPUT
tl_uart1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_opcode[0]	Yes	Yes	*T214,*T215,*T216	Yes	T214,T215,T216	INPUT
tl_uart1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_valid	Yes	Yes	T214,T215,T216	Yes	T214,T215,T216	INPUT
tl_uart2_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_uart2_o.a_user.data_intg[6:0]	Yes	Yes	T8,T151,T315	Yes	T8,T151,T315	OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_uart2_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_uart2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_data[31:0]	Yes	Yes	T8,T151,T315	Yes	T8,T151,T315	OUTPUT
tl_uart2_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_uart2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_source[5:0]	Yes	Yes	*T51,*T69,*T83	Yes	T51,T69,T83	OUTPUT
tl_uart2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_uart2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_opcode[2:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_uart2_o.a_valid	Yes	Yes	T8,T151,T315	Yes	T8,T151,T315	OUTPUT
tl_uart2_i.a_ready	Yes	Yes	T8,T151,T315	Yes	T8,T151,T315	INPUT
tl_uart2_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_uart2_i.d_user.data_intg[6:0]	Yes	Yes	T8,T151,T315	Yes	T8,T151,T315	INPUT
tl_uart2_i.d_user.rsp_intg[6:0]	Yes	Yes	T8,T151,T315	Yes	T8,T151,T315	INPUT
tl_uart2_i.d_data[31:0]	Yes	Yes	T8,T151,T315	Yes	T8,T151,T315	INPUT
tl_uart2_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_uart2_i.d_source[5:0]	Yes	Yes	*T81,*T82,*T87	Yes	T80,T81,T82	INPUT
tl_uart2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_size[1:0]	Yes	Yes	T81,T82,T87	Yes	T81,T82,T87	INPUT
tl_uart2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_opcode[0]	Yes	Yes	*T8,*T151,*T315	Yes	T8,T151,T315	INPUT
tl_uart2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_valid	Yes	Yes	T8,T151,T315	Yes	T8,T151,T315	INPUT
tl_uart3_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_uart3_o.a_user.data_intg[6:0]	Yes	Yes	T18,T303,T304	Yes	T18,T303,T304	OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_uart3_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_uart3_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_data[31:0]	Yes	Yes	T18,T303,T304	Yes	T18,T303,T304	OUTPUT
tl_uart3_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_uart3_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_source[5:0]	Yes	Yes	*T51,*T69,*T83	Yes	T51,T69,T83	OUTPUT
tl_uart3_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_uart3_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_opcode[2:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_uart3_o.a_valid	Yes	Yes	T18,T161,T303	Yes	T18,T161,T303	OUTPUT
tl_uart3_i.a_ready	Yes	Yes	T18,T161,T303	Yes	T18,T161,T303	INPUT
tl_uart3_i.d_error	Yes	Yes	T80,T81,T87	Yes	T80,T81,T87	INPUT
tl_uart3_i.d_user.data_intg[6:0]	Yes	Yes	T18,T303,T304	Yes	T18,T303,T304	INPUT
tl_uart3_i.d_user.rsp_intg[6:0]	Yes	Yes	T18,T161,T303	Yes	T18,T161,T303	INPUT
tl_uart3_i.d_data[31:0]	Yes	Yes	T18,T161,T303	Yes	T18,T161,T303	INPUT
tl_uart3_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T87	INPUT
tl_uart3_i.d_source[5:0]	Yes	Yes	*T80,*T81,*T87	Yes	T80,T81,T89	INPUT
tl_uart3_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_uart3_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_opcode[0]	Yes	Yes	*T18,*T303,*T304	Yes	T18,T303,T304	INPUT
tl_uart3_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_valid	Yes	Yes	T18,T161,T303	Yes	T18,T161,T303	INPUT
tl_i2c0_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_i2c0_o.a_user.data_intg[6:0]	Yes	Yes	T308,T301,T85	Yes	T308,T301,T85	OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_i2c0_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_i2c0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_data[31:0]	Yes	Yes	T308,T301,T85	Yes	T308,T301,T85	OUTPUT
tl_i2c0_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_i2c0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_source[5:0]	Yes	Yes	*T51,*T69,*T83	Yes	T51,T69,T83	OUTPUT
tl_i2c0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_i2c0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_opcode[2:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_i2c0_o.a_valid	Yes	Yes	T308,T301,T85	Yes	T308,T301,T85	OUTPUT
tl_i2c0_i.a_ready	Yes	Yes	T308,T301,T85	Yes	T308,T301,T85	INPUT
tl_i2c0_i.d_error	Yes	Yes	T81,T82,T89	Yes	T80,T81,T82	INPUT
tl_i2c0_i.d_user.data_intg[6:0]	Yes	Yes	T308,T301,T85	Yes	T308,T301,T85	INPUT
tl_i2c0_i.d_user.rsp_intg[6:0]	Yes	Yes	T308,T301,T85	Yes	T308,T301,T85	INPUT
tl_i2c0_i.d_data[31:0]	Yes	Yes	T308,T301,T85	Yes	T308,T301,T85	INPUT
tl_i2c0_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_i2c0_i.d_source[5:0]	Yes	Yes	*T85,*T81,*T82	Yes	T85,T80,T81	INPUT
tl_i2c0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_i2c0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_opcode[0]	Yes	Yes	*T308,*T301,*T85	Yes	T308,T301,T85	INPUT
tl_i2c0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_valid	Yes	Yes	T308,T301,T85	Yes	T308,T301,T85	INPUT
tl_i2c1_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_i2c1_o.a_user.data_intg[6:0]	Yes	Yes	T217,T301,T85	Yes	T217,T301,T85	OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_i2c1_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_i2c1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_data[31:0]	Yes	Yes	T217,T301,T85	Yes	T217,T301,T85	OUTPUT
tl_i2c1_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_i2c1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_source[5:0]	Yes	Yes	*T51,*T69,*T83	Yes	T51,T69,T83	OUTPUT
tl_i2c1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_i2c1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_opcode[2:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_i2c1_o.a_valid	Yes	Yes	T217,T301,T85	Yes	T217,T301,T85	OUTPUT
tl_i2c1_i.a_ready	Yes	Yes	T217,T301,T85	Yes	T217,T301,T85	INPUT
tl_i2c1_i.d_error	Yes	Yes	T81,T82,T89	Yes	T81,T82,T89	INPUT
tl_i2c1_i.d_user.data_intg[6:0]	Yes	Yes	T217,T301,T85	Yes	T217,T301,T85	INPUT
tl_i2c1_i.d_user.rsp_intg[6:0]	Yes	Yes	T217,T301,T85	Yes	T217,T301,T85	INPUT
tl_i2c1_i.d_data[31:0]	Yes	Yes	T217,T301,T85	Yes	T217,T301,T85	INPUT
tl_i2c1_i.d_sink	Yes	Yes	T81,T82,T89	Yes	T81,T82,T89	INPUT
tl_i2c1_i.d_source[5:0]	Yes	Yes	*T85,*T81,*T82	Yes	T85,T81,T82	INPUT
tl_i2c1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_size[1:0]	Yes	Yes	T81,T82,T89	Yes	T81,T82,T89	INPUT
tl_i2c1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_opcode[0]	Yes	Yes	*T217,*T301,*T85	Yes	T217,T301,T85	INPUT
tl_i2c1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_valid	Yes	Yes	T217,T301,T85	Yes	T217,T301,T85	INPUT
tl_i2c2_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_i2c2_o.a_user.data_intg[6:0]	Yes	Yes	T301,T85,T306	Yes	T301,T85,T306	OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_i2c2_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_i2c2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_data[31:0]	Yes	Yes	T301,T85,T306	Yes	T301,T85,T306	OUTPUT
tl_i2c2_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_i2c2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_source[5:0]	Yes	Yes	*T51,*T69,*T83	Yes	T51,T69,T83	OUTPUT
tl_i2c2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_i2c2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_opcode[2:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_i2c2_o.a_valid	Yes	Yes	T301,T85,T161	Yes	T301,T85,T161	OUTPUT
tl_i2c2_i.a_ready	Yes	Yes	T301,T85,T161	Yes	T301,T85,T161	INPUT
tl_i2c2_i.d_error	Yes	Yes	T81,T89,T87	Yes	T81,T82,T89	INPUT
tl_i2c2_i.d_user.data_intg[6:0]	Yes	Yes	T301,T85,T306	Yes	T301,T85,T306	INPUT
tl_i2c2_i.d_user.rsp_intg[6:0]	Yes	Yes	T301,T85,T161	Yes	T301,T85,T161	INPUT
tl_i2c2_i.d_data[31:0]	Yes	Yes	T301,T85,T161	Yes	T301,T85,T161	INPUT
tl_i2c2_i.d_sink	Yes	Yes	T81,T82,T87	Yes	T81,T82,T87	INPUT
tl_i2c2_i.d_source[5:0]	Yes	Yes	*T85,*T81,*T82	Yes	T85,T81,T82	INPUT
tl_i2c2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_size[1:0]	Yes	Yes	T81,T82,T89	Yes	T80,T81,T82	INPUT
tl_i2c2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_opcode[0]	Yes	Yes	*T301,*T85,*T306	Yes	T301,T85,T306	INPUT
tl_i2c2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_valid	Yes	Yes	T301,T85,T161	Yes	T301,T85,T161	INPUT
tl_pattgen_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_pattgen_o.a_user.data_intg[6:0]	Yes	Yes	T218,T331,T156	Yes	T218,T331,T156	OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_pattgen_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_pattgen_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_data[31:0]	Yes	Yes	T218,T331,T156	Yes	T218,T331,T156	OUTPUT
tl_pattgen_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_pattgen_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_source[5:0]	Yes	Yes	*T51,*T69,*T83	Yes	T51,T69,T83	OUTPUT
tl_pattgen_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_pattgen_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_opcode[2:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_pattgen_o.a_valid	Yes	Yes	T218,T331,T156	Yes	T218,T331,T156	OUTPUT
tl_pattgen_i.a_ready	Yes	Yes	T218,T331,T156	Yes	T218,T331,T156	INPUT
tl_pattgen_i.d_error	Yes	Yes	T80,T81,T89	Yes	T80,T81,T82	INPUT
tl_pattgen_i.d_user.data_intg[6:0]	Yes	Yes	T218,T331,T156	Yes	T218,T331,T156	INPUT
tl_pattgen_i.d_user.rsp_intg[6:0]	Yes	Yes	T218,T331,T156	Yes	T218,T331,T156	INPUT
tl_pattgen_i.d_data[31:0]	Yes	Yes	T218,T331,T156	Yes	T218,T331,T156	INPUT
tl_pattgen_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_pattgen_i.d_source[5:0]	Yes	Yes	T80,*T81,*T82	Yes	T80,T81,T82	INPUT
tl_pattgen_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_pattgen_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_opcode[0]	Yes	Yes	*T218,*T331,*T156	Yes	T218,T331,T156	INPUT
tl_pattgen_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_valid	Yes	Yes	T218,T331,T156	Yes	T218,T331,T156	INPUT
tl_pwm_aon_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0]	Yes	Yes	T5,T653,T654	Yes	T5,T653,T654	OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_pwm_aon_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_data[31:0]	Yes	Yes	T5,T653,T654	Yes	T5,T653,T654	OUTPUT
tl_pwm_aon_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_pwm_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_source[5:0]	Yes	Yes	*T51,*T69,*T83	Yes	T51,T69,T83	OUTPUT
tl_pwm_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_pwm_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_opcode[2:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_pwm_aon_o.a_valid	Yes	Yes	T5,T653,T654	Yes	T5,T653,T654	OUTPUT
tl_pwm_aon_i.a_ready	Yes	Yes	T5,T653,T654	Yes	T5,T653,T654	INPUT
tl_pwm_aon_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_pwm_aon_i.d_user.data_intg[6:0]	Yes	Yes	T5,T653,T654	Yes	T5,T653,T654	INPUT
tl_pwm_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T653,T654	Yes	T5,T653,T654	INPUT
tl_pwm_aon_i.d_data[31:0]	Yes	Yes	T5,T653,T654	Yes	T5,T653,T654	INPUT
tl_pwm_aon_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_pwm_aon_i.d_source[5:0]	Yes	Yes	*T55,*T59,*T80	Yes	T55,T59,T80	INPUT
tl_pwm_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_pwm_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_opcode[0]	Yes	Yes	*T5,*T653,*T654	Yes	T5,T653,T654	INPUT
tl_pwm_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_valid	Yes	Yes	T5,T653,T654	Yes	T5,T653,T654	INPUT
tl_gpio_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_gpio_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_gpio_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_gpio_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_gpio_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_gpio_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_source[5:0]	Yes	Yes	*T51,*T69,*T83	Yes	T51,T69,T83	OUTPUT
tl_gpio_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_gpio_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_opcode[2:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_gpio_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_gpio_i.a_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_gpio_i.d_error	Yes	Yes	T81,T82,T89	Yes	T80,T81,T82	INPUT
tl_gpio_i.d_user.data_intg[6:0]	Yes	Yes	T16,T28,T94	Yes	T16,T28,T94	INPUT
tl_gpio_i.d_user.rsp_intg[6:0]	Yes	Yes	T16,T28,T94	Yes	T5,T16,T17	INPUT
tl_gpio_i.d_data[31:0]	Yes	Yes	T16,T28,T94	Yes	T5,T16,T17	INPUT
tl_gpio_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_gpio_i.d_source[5:0]	Yes	Yes	*T85,*T81,*T82	Yes	T85,T80,T81	INPUT
tl_gpio_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_gpio_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_opcode[0]	Yes	Yes	*T5,*T34,*T16	Yes	T2,T3,T4	INPUT
tl_gpio_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_spi_device_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_spi_device_o.a_user.data_intg[6:0]	Yes	Yes	T8,T13,T51	Yes	T8,T13,T51	OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_spi_device_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_spi_device_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_data[31:0]	Yes	Yes	T8,T13,T51	Yes	T8,T13,T51	OUTPUT
tl_spi_device_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_spi_device_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_source[5:0]	Yes	Yes	*T51,*T69,*T83	Yes	T51,T69,T83	OUTPUT
tl_spi_device_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_spi_device_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_opcode[2:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_spi_device_o.a_valid	Yes	Yes	T8,T13,T51	Yes	T8,T13,T51	OUTPUT
tl_spi_device_i.a_ready	Yes	Yes	T8,T13,T51	Yes	T8,T13,T51	INPUT
tl_spi_device_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_spi_device_i.d_user.data_intg[6:0]	Yes	Yes	T8,T13,T51	Yes	T8,T13,T51	INPUT
tl_spi_device_i.d_user.rsp_intg[6:0]	Yes	Yes	T8,T13,T51	Yes	T8,T13,T51	INPUT
tl_spi_device_i.d_data[31:0]	Yes	Yes	T8,T13,T51	Yes	T8,T13,T51	INPUT
tl_spi_device_i.d_sink	Yes	Yes	T80,T81,T89	Yes	T80,T81,T82	INPUT
tl_spi_device_i.d_source[5:0]	Yes	Yes	*T80,*T81,*T89	Yes	T80,T81,T82	INPUT
tl_spi_device_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_spi_device_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_opcode[0]	Yes	Yes	*T8,*T13,*T51	Yes	T8,T13,T51	INPUT
tl_spi_device_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_valid	Yes	Yes	T8,T13,T51	Yes	T8,T13,T51	INPUT
tl_rv_timer_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0]	Yes	Yes	T5,T231,T672	Yes	T5,T231,T672	OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_rv_timer_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_data[31:0]	Yes	Yes	T5,T231,T672	Yes	T5,T231,T672	OUTPUT
tl_rv_timer_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_rv_timer_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_source[5:0]	Yes	Yes	*T51,*T69,*T83	Yes	T51,T69,T83	OUTPUT
tl_rv_timer_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rv_timer_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_opcode[2:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_rv_timer_o.a_valid	Yes	Yes	T5,T231,T672	Yes	T5,T231,T672	OUTPUT
tl_rv_timer_i.a_ready	Yes	Yes	T5,T231,T672	Yes	T5,T231,T672	INPUT
tl_rv_timer_i.d_error	Yes	Yes	T81,T82,T87	Yes	T81,T82,T89	INPUT
tl_rv_timer_i.d_user.data_intg[6:0]	Yes	Yes	T231,T672,T156	Yes	T231,T672,T156	INPUT
tl_rv_timer_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T231,T672	Yes	T5,T231,T672	INPUT
tl_rv_timer_i.d_data[31:0]	Yes	Yes	T5,T231,T672	Yes	T5,T231,T672	INPUT
tl_rv_timer_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_timer_i.d_source[5:0]	Yes	Yes	*T81,*T82,*T87	Yes	T80,T81,T82	INPUT
tl_rv_timer_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_rv_timer_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_opcode[0]	Yes	Yes	*T5,*T231,*T672	Yes	T5,T231,T672	INPUT
tl_rv_timer_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_valid	Yes	Yes	T5,T231,T672	Yes	T5,T231,T672	INPUT
tl_pwrmgr_aon_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_data[31:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_pwrmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_source[5:0]	Yes	Yes	*T51,*T69,*T83	Yes	T51,T69,T83	OUTPUT
tl_pwrmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_pwrmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_opcode[2:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_pwrmgr_aon_o.a_valid	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	OUTPUT
tl_pwrmgr_aon_i.a_ready	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	INPUT
tl_pwrmgr_aon_i.d_error	Yes	Yes	T81,T82,T89	Yes	T81,T87,T88	INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	INPUT
tl_pwrmgr_aon_i.d_data[31:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	INPUT
tl_pwrmgr_aon_i.d_sink	Yes	Yes	T80,T81,T89	Yes	T80,T81,T82	INPUT
tl_pwrmgr_aon_i.d_source[5:0]	Yes	Yes	*T55,*T59,*T81	Yes	T55,T59,T80	INPUT
tl_pwrmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_pwrmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T5	Yes	T2,T3,T5	INPUT
tl_pwrmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_valid	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	INPUT
tl_rstmgr_aon_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_rstmgr_aon_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_rstmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_source[5:0]	Yes	Yes	*T51,*T69,*T83	Yes	T51,T69,T83	OUTPUT
tl_rstmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_rstmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_opcode[2:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_rstmgr_aon_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_rstmgr_aon_i.a_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_rstmgr_aon_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T89	INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T34,T35	Yes	T2,T3,T4	INPUT
tl_rstmgr_aon_i.d_data[31:0]	Yes	Yes	T3,T34,T35	Yes	T2,T3,T4	INPUT
tl_rstmgr_aon_i.d_sink	Yes	Yes	T81,T82,T89	Yes	T81,T82,T89	INPUT
tl_rstmgr_aon_i.d_source[5:0]	Yes	Yes	*T55,*T59,*T81	Yes	T55,T59,T80	INPUT
tl_rstmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_size[1:0]	Yes	Yes	T81,T89,T88	Yes	T81,T82,T89	INPUT
tl_rstmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_rstmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_clkmgr_aon_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T35,T52,T170	Yes	T35,T52,T170	OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_data[31:0]	Yes	Yes	T95,T35,T52	Yes	T95,T35,T52	OUTPUT
tl_clkmgr_aon_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_clkmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_source[5:0]	Yes	Yes	*T51,*T69,*T83	Yes	T51,T69,T83	OUTPUT
tl_clkmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_clkmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_opcode[2:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_clkmgr_aon_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_clkmgr_aon_i.a_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_clkmgr_aon_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T52,T626,T121	Yes	T52,T626,T121	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T34,T35,T36	Yes	T2,T3,T4	INPUT
tl_clkmgr_aon_i.d_data[31:0]	Yes	Yes	T34,T35,T36	Yes	T2,T3,T4	INPUT
tl_clkmgr_aon_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_clkmgr_aon_i.d_source[5:0]	Yes	Yes	*T55,*T81,*T82	Yes	T83,T659,T660	INPUT
tl_clkmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_clkmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_opcode[0]	Yes	Yes	*T35,*T52,*T170	Yes	T35,T52,T170	INPUT
tl_clkmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_pinmux_aon_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_pinmux_aon_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_pinmux_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_source[5:0]	Yes	Yes	*T51,*T69,*T83	Yes	T51,T69,T83	OUTPUT
tl_pinmux_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_pinmux_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_opcode[2:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_pinmux_aon_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_pinmux_aon_i.a_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_pinmux_aon_i.d_error	Yes	Yes	T81,T87,T88	Yes	T81,T87,T88	INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T4,T5	Yes	T2,T3,T4	INPUT
tl_pinmux_aon_i.d_data[31:0]	Yes	Yes	T2,T4,T5	Yes	T2,T3,T4	INPUT
tl_pinmux_aon_i.d_sink	Yes	Yes	T81,T89,T87	Yes	T81,T89,T87	INPUT
tl_pinmux_aon_i.d_source[5:0]	Yes	Yes	*T55,*T59,*T81	Yes	T55,T59,T80	INPUT
tl_pinmux_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_size[1:0]	Yes	Yes	T81,T89,T87	Yes	T80,T81,T89	INPUT
tl_pinmux_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_opcode[0]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T5	INPUT
tl_pinmux_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_otp_ctrl__core_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_otp_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_source[5:0]	Yes	Yes	*T51,*T69,*T83	Yes	T51,T69,T83	OUTPUT
tl_otp_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_otp_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_otp_ctrl__core_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_otp_ctrl__core_i.a_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_otp_ctrl__core_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_otp_ctrl__core_i.d_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_otp_ctrl__core_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T81,T82,T89	INPUT
tl_otp_ctrl__core_i.d_source[5:0]	Yes	Yes	*T51,*T69,*T83	Yes	T51,T69,T83	INPUT
tl_otp_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_otp_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_opcode[0]	Yes	Yes	*T4,*T5,*T75	Yes	T4,T154,T155	INPUT
tl_otp_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_otp_ctrl__prim_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_otp_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T51,*T69,*T83	Yes	T51,T69,T83	OUTPUT
tl_otp_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_otp_ctrl__prim_o.a_valid	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_otp_ctrl__prim_i.a_ready	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	INPUT
tl_otp_ctrl__prim_i.d_error	Yes	Yes	T2,T4,T5	Yes	T34,T35,T36	INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_otp_ctrl__prim_i.d_data[31:0]	Yes	Yes	T2,T4,T5	Yes	T34,T35,T36	INPUT
tl_otp_ctrl__prim_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T81,T82,T89	INPUT
tl_otp_ctrl__prim_i.d_source[5:0]	Yes	Yes	T81,*T82,T89	Yes	T80,T81,T82	INPUT
tl_otp_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_otp_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T2,*T4,*T5	Yes	T34,T35,T36	INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_valid	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_lc_ctrl_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0]	Yes	Yes	T3,T121,T7	Yes	T3,T121,T7	OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_data[31:0]	Yes	Yes	T3,T121,T7	Yes	T3,T121,T7	OUTPUT
tl_lc_ctrl_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_lc_ctrl_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_source[5:0]	Yes	Yes	*T51,*T69,*T83	Yes	T51,T69,T83	OUTPUT
tl_lc_ctrl_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_lc_ctrl_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_opcode[2:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_lc_ctrl_o.a_valid	Yes	Yes	T3,T121,T7	Yes	T3,T121,T7	OUTPUT
tl_lc_ctrl_i.a_ready	Yes	Yes	T3,T121,T7	Yes	T3,T121,T7	INPUT
tl_lc_ctrl_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T89	INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0]	Yes	Yes	T3,T8,T9	Yes	T3,T8,T9	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6:0]	Yes	Yes	T164,T175,T176	Yes	T164,T175,T176	INPUT
tl_lc_ctrl_i.d_data[31:0]	Yes	Yes	T3,T7,T8	Yes	T3,T121,T7	INPUT
tl_lc_ctrl_i.d_sink	Yes	Yes	T81,T82,T89	Yes	T80,T81,T82	INPUT
tl_lc_ctrl_i.d_source[5:0]	Yes	Yes	*T296,*T297,*T298	Yes	T296,T297,T298	INPUT
tl_lc_ctrl_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_size[1:0]	Yes	Yes	T80,T81,T87	Yes	T80,T81,T82	INPUT
tl_lc_ctrl_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_opcode[0]	Yes	Yes	*T7,*T8,*T155	Yes	T3,T121,T7	INPUT
tl_lc_ctrl_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_valid	Yes	Yes	T3,T121,T7	Yes	T3,T121,T7	INPUT
tl_sensor_ctrl_aon_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_sensor_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T51,*T69,*T83	Yes	T51,T69,T83	OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_sensor_ctrl_aon_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_sensor_ctrl_aon_i.a_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_sensor_ctrl_aon_i.d_error	Yes	Yes	T81,T82,T89	Yes	T81,T82,T89	INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T3,T143,T140	Yes	T3,T143,T140	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T3,T143,T140	Yes	T3,T143,T140	INPUT
tl_sensor_ctrl_aon_i.d_data[31:0]	Yes	Yes	T3,T34,T35	Yes	T2,T3,T4	INPUT
tl_sensor_ctrl_aon_i.d_sink	Yes	Yes	T81,T82,T89	Yes	T81,T82,T89	INPUT
tl_sensor_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T81,*T82,*T87	Yes	T81,T82,T89	INPUT
tl_sensor_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_sensor_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T3,*T34,*T35	Yes	T2,T3,T4	INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_alert_handler_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_alert_handler_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_data[31:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	OUTPUT
tl_alert_handler_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_alert_handler_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_source[5:0]	Yes	Yes	*T51,*T69,*T83	Yes	T51,T69,T83	OUTPUT
tl_alert_handler_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_alert_handler_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_opcode[2:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_alert_handler_o.a_valid	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	OUTPUT
tl_alert_handler_i.a_ready	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	INPUT
tl_alert_handler_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_alert_handler_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	INPUT
tl_alert_handler_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	INPUT
tl_alert_handler_i.d_data[31:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	INPUT
tl_alert_handler_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_alert_handler_i.d_source[5:0]	Yes	Yes	*T55,*T81,*T82	Yes	T55,T80,T81	INPUT
tl_alert_handler_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_alert_handler_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_opcode[0]	Yes	Yes	*T2,*T5,*T6	Yes	T2,T3,T5	INPUT
tl_alert_handler_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_valid	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0]	Yes	Yes	T3,T49,T120	Yes	T3,T49,T120	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0]	Yes	Yes	T3,T49,T120	Yes	T3,T49,T120	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[5:0]	Yes	Yes	*T51,*T69,*T83	Yes	T51,T69,T83	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid	Yes	Yes	T3,T49,T120	Yes	T3,T49,T120	OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready	Yes	Yes	T3,T49,T120	Yes	T3,T49,T120	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6:0]	Yes	Yes	T120,T177,T178	Yes	T120,T177,T178	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T120,T46,T47	Yes	T3,T49,T120	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0]	Yes	Yes	T120,T46,T47	Yes	T3,T49,T120	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[5:0]	Yes	Yes	*T80,*T81,*T82	Yes	T80,T81,T82	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0]	Yes	Yes	*T120,*T177,*T178	Yes	T120,T177,T407	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid	Yes	Yes	T3,T49,T120	Yes	T3,T49,T120	INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T34	Yes	T2,T3,T34	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[5:0]	Yes	Yes	*T51,*T69,*T83	Yes	T51,T69,T83	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T34,T35,T36	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T34	Yes	T2,T3,T34	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T34	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0]	Yes	Yes	T2,T3,T34	Yes	T2,T3,T34	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink	Yes	Yes	T81,T82,T87	Yes	T81,T82,T87	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[5:0]	Yes	Yes	*T84,*T86,*T412	Yes	T84,T86,T412	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1:0]	Yes	Yes	T81,T82,T87	Yes	T81,T82,T87	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_aon_timer_aon_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_data[31:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	OUTPUT
tl_aon_timer_aon_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_aon_timer_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_source[5:0]	Yes	Yes	*T51,*T69,*T83	Yes	T51,T69,T83	OUTPUT
tl_aon_timer_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_aon_timer_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_opcode[2:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_aon_timer_aon_o.a_valid	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	OUTPUT
tl_aon_timer_aon_i.a_ready	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	INPUT
tl_aon_timer_aon_i.d_error	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:0]	Yes	Yes	T2,T5,T6	Yes	T2,T5,T6	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	INPUT
tl_aon_timer_aon_i.d_data[31:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	INPUT
tl_aon_timer_aon_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T81,T82,T89	INPUT
tl_aon_timer_aon_i.d_source[5:0]	Yes	Yes	*T55,*T81,*T82	Yes	T232,T233,T234	INPUT
tl_aon_timer_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_aon_timer_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T5	Yes	T2,T3,T5	INPUT
tl_aon_timer_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_valid	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	INPUT
tl_sysrst_ctrl_aon_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T71,T169,T19	Yes	T71,T169,T19	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0]	Yes	Yes	T71,T169,T19	Yes	T71,T169,T19	OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T51,*T69,*T83	Yes	T51,T69,T83	OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_sysrst_ctrl_aon_o.a_valid	Yes	Yes	T71,T169,T19	Yes	T71,T169,T19	OUTPUT
tl_sysrst_ctrl_aon_i.a_ready	Yes	Yes	T71,T169,T19	Yes	T71,T169,T19	INPUT
tl_sysrst_ctrl_aon_i.d_error	Yes	Yes	T81,T82,T89	Yes	T80,T81,T82	INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T71,T169,T19	Yes	T71,T169,T19	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T71,T169,T19	Yes	T71,T169,T19	INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0]	Yes	Yes	T71,T169,T53	Yes	T71,T169,T19	INPUT
tl_sysrst_ctrl_aon_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_sysrst_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T81,*T82,*T87	Yes	T80,T81,T82	INPUT
tl_sysrst_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T71,*T169,*T19	Yes	T71,T169,T19	INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_valid	Yes	Yes	T71,T169,T19	Yes	T71,T169,T19	INPUT
tl_adc_ctrl_aon_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T5,T19,T53	Yes	T5,T19,T53	OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0]	Yes	Yes	T5,T19,T53	Yes	T5,T19,T53	OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_adc_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T51,*T69,*T83	Yes	T51,T69,T83	OUTPUT
tl_adc_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_adc_ctrl_aon_o.a_valid	Yes	Yes	T5,T19,T53	Yes	T5,T19,T53	OUTPUT
tl_adc_ctrl_aon_i.a_ready	Yes	Yes	T5,T19,T53	Yes	T5,T19,T53	INPUT
tl_adc_ctrl_aon_i.d_error	Yes	Yes	T81,T82,T89	Yes	T81,T82,T89	INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T19,T116,T301	Yes	T19,T53,T54	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T19,T53	Yes	T5,T19,T53	INPUT
tl_adc_ctrl_aon_i.d_data[31:0]	Yes	Yes	T5,T19,T53	Yes	T5,T19,T53	INPUT
tl_adc_ctrl_aon_i.d_sink	Yes	Yes	T80,T81,T89	Yes	T80,T81,T82	INPUT
tl_adc_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T55,*T81,*T82	Yes	T55,T80,T81	INPUT
tl_adc_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_adc_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T5,*T19,*T116	Yes	T5,T19,T53	INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_valid	Yes	Yes	T5,T19,T53	Yes	T5,T19,T53	INPUT
tl_ast_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_ast_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_ast_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_ast_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_ast_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_ast_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_ast_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_source[5:0]	Yes	Yes	*T51,*T69,*T83	Yes	T51,T69,T83	OUTPUT
tl_ast_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	OUTPUT
tl_ast_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_opcode[2:0]	Yes	Yes	T84,T85,T86	Yes	T84,T85,T86	OUTPUT
tl_ast_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_ast_i.a_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_ast_i.d_error	Yes	Yes	T81,T82,T87	Yes	T81,T82,T87	INPUT
tl_ast_i.d_user.data_intg[6:0]	Yes	Yes	T80,T81,T82	Yes	T80,T81,T82	INPUT
tl_ast_i.d_user.rsp_intg[6:0]	Yes	Yes	T34,T35,T36	Yes	T2,T3,T4	INPUT
tl_ast_i.d_data[31:0]	Yes	Yes	T34,T35,T36	Yes	T2,T3,T4	INPUT
tl_ast_i.d_sink	Yes	Yes	T80,T81,T82	Yes	T81,T87,T88	INPUT
tl_ast_i.d_source[5:0]	Yes	Yes	*T81,*T82,*T87	Yes	T80,T81,T89	INPUT
tl_ast_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_size[1:0]	Yes	Yes	T80,T81,T82	Yes	T81,T82,T87	INPUT
tl_ast_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_opcode[0]	Yes	Yes	*T80,*T81,*T82	Yes	T81,T82,T87	INPUT
tl_ast_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range