Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3653239	1			T75	5		T77	7476		T82	226
values[2]	737751	1			T75	7		T77	1262		T82	75
values[3]	100858	1			T75	4		T77	16		T82	3
values[4]	52564	1			T75	6		T566	1		T564	2
values[5]	34877	1			T75	8		T464	16		T453	22
values[6]	25653	1			T75	7		T464	15		T453	14
values[7]	20528	1			T75	10		T464	15		T453	20
values[8]	17296	1			T75	3		T464	16		T453	13
values[9]	15575	1			T75	3		T464	15		T453	13
values[10]	14360	1			T75	6		T464	15		T453	16
values[11]	13260	1			T75	9		T464	15		T453	10
values[12]	12401	1			T75	16		T464	15		T453	2
values[13]	11547	1			T75	6		T464	16		T453	2
values[14]	11067	1			T75	1		T464	15		T551	20
values[15]	10453	1			T75	4		T464	15		T551	26
values[16]	9837	1			T75	7		T464	16		T551	29
values[17]	9269	1			T75	4		T464	15		T551	27
values[18]	9116	1			T75	6		T464	15		T551	22
values[19]	8752	1			T75	2		T464	15		T551	34
values[20]	8347	1			T75	2		T464	15		T551	31
values[21]	8100	1			T75	1		T464	15		T551	23
values[22]	8132	1			T75	2		T464	15		T551	17
values[23]	7649	1			T75	5		T464	15		T551	6
values[24]	7085	1			T75	3		T464	15		T551	4
values[25]	7026	1			T75	2		T464	16		T551	4
values[26]	6720	1			T75	1		T464	17		T551	8
values[27]	6651	1			T75	4		T464	15		T551	10
values[28]	6311	1			T75	3		T464	15		T551	12
values[29]	5952	1			T75	1		T464	16		T551	8
values[30]	5462	1			T75	2		T464	15		T551	4
values[31]	5145	1			T75	1		T464	15		T551	7
values[32]	4863	1			T75	1		T464	15		T551	7
values[33]	4682	1			T75	3		T464	16		T551	17
values[34]	4387	1			T75	1		T464	15		T551	6
values[35]	4065	1			T75	7		T464	15		T551	6
values[36]	3943	1			T75	5		T464	15		T551	4
values[37]	3738	1			T75	6		T464	15		T551	9
values[38]	3520	1			T75	4		T464	15		T551	8
values[39]	3311	1			T75	3		T464	15		T551	3
values[40]	3219	1			T75	1		T464	15		T551	5
values[41]	3122	1			T75	2		T464	15		T551	6
values[42]	3092	1			T464	15		T551	8		T553	21
values[43]	2959	1			T464	15		T551	7		T553	22
values[44]	2899	1			T464	15		T551	3		T553	2
values[45]	2892	1			T464	17		T551	4		T553	2
values[46]	2797	1			T464	15		T551	2		T553	2
values[47]	2815	1			T464	15		T551	2		T553	4
values[48]	2752	1			T464	15		T551	4		T553	2
values[49]	2668	1			T464	16		T551	8		T553	2
values[50]	2556	1			T464	15		T551	3		T553	2
values[51]	2509	1			T464	15		T551	7		T553	2
values[52]	2506	1			T464	15		T551	5		T553	4
values[53]	2574	1			T464	15		T551	4		T553	6
values[54]	2578	1			T464	15		T551	3		T553	2
values[55]	2497	1			T464	15		T551	3		T553	2
values[56]	2318	1			T464	15		T551	3		T553	3
values[57]	2338	1			T464	16		T551	3		T553	2
values[58]	2295	1			T464	15		T551	3		T553	5
values[59]	2132	1			T464	15		T551	2		T553	4
values[60]	2244	1			T464	15		T551	1		T553	3
values[61]	2368	1			T464	16		T553	3		T565	22
values[62]	3671	1			T464	15		T553	3		T565	39
values[63]	9567	1			T464	17		T553	20		T565	81
values[64]	209658	1			T464	2633		T553	184		T565	540

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4647689	1			T75	227		T77	7674		T82	240
values[2]	780030	1			T75	57		T77	1075		T82	57
values[3]	83500	1			T75	2		T77	19		T82	7
values[4]	14847	1			T83	4		T452	2		T566	1
values[5]	5750	1			T564	3		T464	24		T553	2
values[6]	3656	1			T564	1		T464	5		T553	2
values[7]	2740	1			T464	1		T553	1		T737	1
values[8]	2321	1			T553	2		T561	3		T644	1
values[9]	1942	1			T553	1		T561	2		T710	1
values[10]	1783	1			T553	1		T561	1		T710	2
values[11]	1574	1			T553	1		T561	1		T710	1
values[12]	1419	1			T553	1		T710	1		T465	12
values[13]	1310	1			T553	3		T710	2		T465	5
values[14]	1194	1			T553	4		T710	2		T465	3
values[15]	1208	1			T553	4		T710	3		T465	2
values[16]	1170	1			T553	4		T710	2		T465	3
values[17]	1051	1			T553	1		T710	4		T465	2
values[18]	991	1			T553	2		T710	4		T465	2
values[19]	863	1			T553	8		T710	6		T465	4
values[20]	793	1			T553	2		T710	2		T465	3
values[21]	738	1			T553	1		T710	3		T465	3
values[22]	749	1			T553	3		T710	5		T465	4
values[23]	734	1			T553	3		T710	4		T465	2
values[24]	678	1			T553	2		T710	5		T465	3
values[25]	697	1			T553	3		T710	1		T465	5
values[26]	633	1			T553	1		T710	1		T465	5
values[27]	619	1			T553	1		T710	1		T465	9
values[28]	547	1			T553	1		T710	1		T465	6
values[29]	610	1			T553	1		T710	3		T465	6
values[30]	528	1			T553	1		T710	1		T465	3
values[31]	522	1			T553	2		T710	2		T465	3
values[32]	468	1			T553	9		T710	1		T465	3
values[33]	458	1			T553	5		T710	3		T465	2
values[34]	447	1			T553	3		T710	2		T465	5
values[35]	466	1			T553	2		T710	1		T465	5
values[36]	423	1			T553	1		T710	5		T465	5
values[37]	418	1			T553	3		T710	2		T465	7
values[38]	434	1			T553	1		T710	2		T465	3
values[39]	433	1			T553	2		T710	1		T465	2
values[40]	456	1			T553	4		T710	1		T465	4
values[41]	455	1			T553	2		T710	1		T465	4
values[42]	449	1			T553	1		T710	1		T465	4
values[43]	432	1			T553	1		T710	1		T465	6
values[44]	420	1			T553	1		T710	1		T465	2
values[45]	398	1			T553	1		T710	1		T465	2
values[46]	383	1			T553	4		T710	5		T465	3
values[47]	365	1			T553	1		T710	1		T465	6
values[48]	369	1			T553	2		T710	2		T465	3
values[49]	348	1			T553	1		T710	1		T465	2
values[50]	317	1			T553	2		T710	1		T465	2
values[51]	300	1			T553	1		T710	1		T465	3
values[52]	334	1			T553	3		T710	1		T465	3
values[53]	309	1			T553	3		T710	1		T465	5
values[54]	346	1			T553	2		T710	2		T465	8
values[55]	355	1			T553	1		T710	1		T465	3
values[56]	308	1			T553	2		T710	1		T465	3
values[57]	303	1			T553	2		T710	1		T465	2
values[58]	307	1			T553	3		T710	3		T465	2
values[59]	304	1			T553	2		T710	1		T465	3
values[60]	299	1			T553	2		T710	3		T465	5
values[61]	342	1			T553	5		T710	3		T465	8
values[62]	579	1			T553	10		T710	1		T465	16
values[63]	2285	1			T553	25		T710	13		T465	80
values[64]	20082	1			T553	64		T710	141		T465	222

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	560356	1			T75	1		T77	1853		T82	2
values[2]	2595289	1			T75	4		T77	5745		T82	154
values[3]	1166099	1			T75	4		T77	990		T82	110
values[4]	144814	1			T75	7		T77	23		T82	4
values[5]	73809	1			T75	6		T77	14		T82	1
values[6]	48236	1			T75	5		T77	14		T83	1
values[7]	34747	1			T75	12		T77	17		T464	15
values[8]	27031	1			T75	5		T77	14		T464	15
values[9]	22522	1			T75	7		T77	6		T464	15
values[10]	19999	1			T75	5		T77	31		T464	15
values[11]	17849	1			T75	6		T77	25		T464	15
values[12]	15757	1			T75	5		T77	11		T464	15
values[13]	14467	1			T75	1		T77	27		T464	16
values[14]	14089	1			T75	1		T77	18		T464	15
values[15]	13378	1			T75	9		T77	32		T464	15
values[16]	12781	1			T75	22		T77	14		T464	15
values[17]	11955	1			T75	15		T77	16		T464	15
values[18]	11369	1			T75	7		T77	14		T464	15
values[19]	10600	1			T75	2		T77	15		T464	16
values[20]	10175	1			T75	1		T77	23		T464	15
values[21]	9602	1			T77	12		T464	15		T551	19
values[22]	9134	1			T77	7		T464	15		T551	14
values[23]	8876	1			T77	10		T464	15		T551	15
values[24]	8775	1			T77	6		T464	15		T551	17
values[25]	8369	1			T77	22		T464	15		T551	16
values[26]	7979	1			T77	16		T464	15		T551	22
values[27]	7450	1			T77	7		T464	15		T551	22
values[28]	7024	1			T77	6		T464	16		T551	13
values[29]	6582	1			T77	11		T464	15		T551	13
values[30]	6261	1			T77	8		T464	15		T551	15
values[31]	5862	1			T77	6		T464	15		T551	11
values[32]	5587	1			T77	11		T464	15		T551	7
values[33]	5248	1			T77	6		T464	15		T551	13
values[34]	4901	1			T464	16		T551	34		T553	7
values[35]	4354	1			T464	15		T551	15		T553	4
values[36]	4143	1			T464	15		T551	10		T553	13
values[37]	3945	1			T464	15		T551	11		T553	9
values[38]	3744	1			T464	15		T551	12		T553	12
values[39]	3580	1			T464	15		T551	11		T553	10
values[40]	3520	1			T464	15		T551	13		T553	4
values[41]	3447	1			T464	15		T551	7		T553	6
values[42]	3376	1			T464	15		T551	8		T553	10
values[43]	3243	1			T464	15		T551	6		T553	15
values[44]	3164	1			T464	15		T551	6		T553	16
values[45]	3131	1			T464	15		T551	5		T553	13
values[46]	3172	1			T464	15		T551	3		T553	11
values[47]	3101	1			T464	15		T551	5		T553	8
values[48]	2968	1			T464	15		T551	3		T553	3
values[49]	2858	1			T464	15		T551	2		T553	9
values[50]	2783	1			T464	15		T551	4		T553	11
values[51]	2758	1			T464	15		T551	4		T553	12
values[52]	2860	1			T464	15		T551	9		T553	15
values[53]	2814	1			T464	15		T551	10		T553	23
values[54]	2600	1			T464	16		T551	8		T553	10
values[55]	2641	1			T464	15		T551	9		T553	4
values[56]	2605	1			T464	15		T551	9		T553	8
values[57]	2619	1			T464	15		T551	3		T553	3
values[58]	2493	1			T464	16		T551	4		T553	7
values[59]	2406	1			T464	15		T551	12		T553	6
values[60]	2460	1			T464	15		T551	12		T553	8
values[61]	2576	1			T464	15		T551	6		T553	6
values[62]	3312	1			T464	15		T551	8		T553	19
values[63]	8376	1			T464	17		T551	6		T553	40
values[64]	203967	1			T464	2732		T551	37		T553	135