Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2087926	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

38920048

1

T1

3093

T2

4307

T3

7574

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	28759803	1			T1	582		T2	1400		T3	3462
values[0x0]	10728279	1			T1	2511		T2	2907		T3	4112
values[0x1]	1519892	1			T1	66		T2	216		T3	375

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	722472	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

40285502

1

T1

3159

T2

4523

T3

7949

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	19190172	1			T1	1580		T2	2262		T3	3975
valid_sources[0x01]	19192539	1			T1	1579		T2	2261		T3	3974
valid_sources[0x02]	41496	1			T7	1		T76	22		T133	374
valid_sources[0x03]	42320	1			T76	18		T133	438		T152	110
valid_sources[0x04]	42760	1			T7	1		T76	13		T133	339
valid_sources[0x05]	41773	1			T7	1		T76	21		T133	379
valid_sources[0x06]	41549	1			T7	2		T211	3		T76	15
valid_sources[0x07]	43848	1			T211	1		T76	24		T133	408
valid_sources[0x08]	42528	1			T7	3		T211	1		T76	21
valid_sources[0x09]	42458	1			T211	1		T76	18		T133	502
valid_sources[0x0a]	42374	1			T7	1		T211	1		T76	18
valid_sources[0x0b]	42289	1			T211	4		T76	22		T133	396
valid_sources[0x0c]	41863	1			T7	1		T210	3		T76	10
valid_sources[0x0d]	41411	1			T210	2		T211	2		T76	8
valid_sources[0x0e]	44663	1			T76	20		T133	508		T152	63
valid_sources[0x0f]	43670	1			T211	1		T76	12		T133	444
valid_sources[0x10]	41923	1			T210	4		T211	1		T76	15
valid_sources[0x11]	41985	1			T210	3		T76	15		T133	422
valid_sources[0x12]	44298	1			T76	9		T133	406		T152	59
valid_sources[0x13]	42823	1			T7	1		T76	19		T133	408
valid_sources[0x14]	43147	1			T7	1		T210	1		T211	1
valid_sources[0x15]	42295	1			T76	18		T133	392		T152	131
valid_sources[0x16]	42581	1			T76	17		T133	439		T152	49
valid_sources[0x17]	41320	1			T211	1		T76	15		T133	393
valid_sources[0x18]	42002	1			T7	2		T76	16		T133	403
valid_sources[0x19]	42320	1			T80	11		T76	22		T133	550
valid_sources[0x1a]	42106	1			T7	2		T76	15		T133	437
valid_sources[0x1b]	43134	1			T211	1		T76	10		T133	420
valid_sources[0x1c]	41325	1			T76	16		T133	328		T152	79
valid_sources[0x1d]	41031	1			T7	3		T76	17		T133	375
valid_sources[0x1e]	42254	1			T76	16		T133	465		T152	75
valid_sources[0x1f]	41052	1			T7	1		T76	19		T133	323
valid_sources[0x20]	42078	1			T7	4		T210	1		T76	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

27957281

1

T1

582

T2

1400

T3

3462

values[0x0]

all_enables

biggest_size

10674753

1

T1

2511

T2

2907

T3

4112

values[0x1]

all_enables

biggest_size

288014

1

T7

22

T80

22

T81

15

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2748596	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

434797

1

T75

25

T77

1200

T82

29

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1078958	1			T75	69		T77	2965		T82	110
values[0x0]	1025902	1			T75	49		T77	2902		T82	84
values[0x1]	1078533	1			T75	56		T77	2887		T82	110

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2126117	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1057276

1

T75

59

T77

2876

T82

94

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	50093	1			T75	2		T77	78		T82	1
valid_sources[0x01]	50865	1			T75	7		T77	114		T82	4
valid_sources[0x02]	49318	1			T75	4		T77	155		T82	6
valid_sources[0x03]	50646	1			T75	3		T77	182		T82	2
valid_sources[0x04]	49668	1			T75	3		T77	93		T84	5
valid_sources[0x05]	49362	1			T75	1		T77	153		T82	16
valid_sources[0x06]	49922	1			T75	3		T77	97		T82	5
valid_sources[0x07]	49534	1			T77	91		T82	5		T452	69
valid_sources[0x08]	49450	1			T75	3		T77	521		T82	7
valid_sources[0x09]	49752	1			T75	1		T77	109		T82	8
valid_sources[0x0a]	49865	1			T77	134		T82	4		T84	1
valid_sources[0x0b]	49204	1			T75	10		T77	144		T452	35
valid_sources[0x0c]	49346	1			T75	3		T77	142		T82	3
valid_sources[0x0d]	50016	1			T75	5		T77	156		T82	7
valid_sources[0x0e]	49811	1			T77	211		T82	3		T84	6
valid_sources[0x0f]	50225	1			T75	1		T77	80		T84	1
valid_sources[0x10]	49044	1			T75	5		T77	121		T82	2
valid_sources[0x11]	49226	1			T75	1		T77	117		T82	3
valid_sources[0x12]	49771	1			T77	260		T82	4		T84	1
valid_sources[0x13]	49288	1			T75	1		T77	110		T84	3
valid_sources[0x14]	49986	1			T75	4		T77	100		T82	7
valid_sources[0x15]	49929	1			T75	1		T77	69		T84	6
valid_sources[0x16]	49768	1			T77	55		T82	3		T84	2
valid_sources[0x17]	50805	1			T75	1		T77	104		T84	1
valid_sources[0x18]	50380	1			T77	270		T82	8		T84	3
valid_sources[0x19]	50706	1			T75	6		T77	121		T82	4
valid_sources[0x1a]	49782	1			T75	1		T77	128		T84	1
valid_sources[0x1b]	50321	1			T75	1		T77	161		T82	16
valid_sources[0x1c]	49518	1			T75	7		T77	113		T82	3
valid_sources[0x1d]	49425	1			T75	6		T77	151		T82	11
valid_sources[0x1e]	49729	1			T75	1		T77	117		T82	1
valid_sources[0x1f]	50800	1			T75	5		T77	185		T82	3
valid_sources[0x20]	49490	1			T77	91		T82	8		T84	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

46012

1

T75

2

T77

122

T82

3

values[0x0]

all_enables

biggest_size

343071

1

T75

20

T77

957

T82

22

values[0x1]

all_enables

biggest_size

45714

1

T75

3

T77

121

T82

4

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2937148	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

477533

1

T75

40

T77

1248

T82

49

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1169011	1			T75	95		T77	2969		T82	73
values[0x0]	1075088	1			T75	103		T77	2837		T82	109
values[0x1]	1170582	1			T75	88		T77	2962		T82	122

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2254408	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1160273

1

T75

87

T77

2993

T82

114

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	54309	1			T75	5		T77	108		T82	1
valid_sources[0x01]	53916	1			T75	2		T77	128		T82	4
valid_sources[0x02]	52811	1			T75	8		T77	164		T82	12
valid_sources[0x03]	53695	1			T75	4		T77	107		T82	13
valid_sources[0x04]	53865	1			T75	7		T77	123		T82	7
valid_sources[0x05]	52919	1			T75	4		T77	83		T82	10
valid_sources[0x06]	53405	1			T75	4		T77	100		T84	4
valid_sources[0x07]	54157	1			T75	2		T77	103		T84	2
valid_sources[0x08]	53874	1			T75	1		T77	160		T82	14
valid_sources[0x09]	53710	1			T75	2		T77	107		T84	2
valid_sources[0x0a]	53690	1			T75	7		T77	140		T82	4
valid_sources[0x0b]	52818	1			T75	1		T77	141		T82	2
valid_sources[0x0c]	53829	1			T75	2		T77	135		T82	1
valid_sources[0x0d]	54043	1			T75	3		T77	140		T84	1
valid_sources[0x0e]	53502	1			T75	13		T77	137		T84	4
valid_sources[0x0f]	53090	1			T75	3		T77	124		T84	1
valid_sources[0x10]	53503	1			T75	6		T77	111		T452	40
valid_sources[0x11]	52787	1			T75	2		T77	95		T84	1
valid_sources[0x12]	53129	1			T75	6		T77	106		T82	1
valid_sources[0x13]	53101	1			T75	4		T77	173		T82	4
valid_sources[0x14]	53591	1			T75	1		T77	163		T82	12
valid_sources[0x15]	53304	1			T75	2		T77	100		T82	7
valid_sources[0x16]	52102	1			T75	5		T77	92		T82	8
valid_sources[0x17]	53501	1			T75	3		T77	104		T82	4
valid_sources[0x18]	53983	1			T75	7		T77	84		T84	1
valid_sources[0x19]	54949	1			T75	5		T77	141		T83	2
valid_sources[0x1a]	53655	1			T75	6		T77	156		T82	11
valid_sources[0x1b]	53562	1			T75	8		T77	254		T84	5
valid_sources[0x1c]	53198	1			T75	6		T77	149		T82	3
valid_sources[0x1d]	53838	1			T75	5		T77	114		T84	2
valid_sources[0x1e]	53238	1			T75	8		T77	117		T84	1
valid_sources[0x1f]	53326	1			T75	5		T77	157		T82	5
valid_sources[0x20]	52903	1			T75	5		T77	142		T452	39

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

50379

1

T75

2

T77

134

T82

2

values[0x0]

all_enables

biggest_size

376708

1

T75

35

T77

990

T82

44

values[0x1]

all_enables

biggest_size

50446

1

T75

3

T77

124

T82

3

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2775679	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

439007

1

T75

21

T77

1209

T82

34

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1089896	1			T75	37		T77	2994		T82	93
values[0x0]	1036036	1			T75	39		T77	2971		T82	86
values[0x1]	1088754	1			T75	49		T77	3065		T82	92

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2149682	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1065004

1

T75

44

T77

2954

T82

79

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	49709	1			T77	138		T84	10		T452	54
valid_sources[0x01]	50987	1			T75	1		T77	130		T82	3
valid_sources[0x02]	50508	1			T77	127		T82	1		T452	48
valid_sources[0x03]	50529	1			T75	2		T77	74		T82	5
valid_sources[0x04]	50388	1			T77	72		T82	10		T84	4
valid_sources[0x05]	49846	1			T75	3		T77	122		T82	1
valid_sources[0x06]	50982	1			T75	3		T77	180		T82	7
valid_sources[0x07]	51633	1			T75	3		T77	78		T82	3
valid_sources[0x08]	51208	1			T75	2		T77	133		T84	29
valid_sources[0x09]	49795	1			T75	2		T77	90		T84	13
valid_sources[0x0a]	50224	1			T75	6		T77	93		T82	10
valid_sources[0x0b]	50608	1			T77	113		T82	3		T452	24
valid_sources[0x0c]	49606	1			T77	133		T83	1		T452	36
valid_sources[0x0d]	51408	1			T75	3		T77	144		T82	3
valid_sources[0x0e]	50497	1			T75	1		T77	174		T82	4
valid_sources[0x0f]	49925	1			T75	1		T77	184		T82	3
valid_sources[0x10]	50260	1			T77	136		T82	5		T83	2
valid_sources[0x11]	50345	1			T75	1		T77	117		T82	6
valid_sources[0x12]	50237	1			T77	161		T82	5		T83	1
valid_sources[0x13]	50695	1			T75	5		T77	149		T82	1
valid_sources[0x14]	49653	1			T75	2		T77	129		T82	6
valid_sources[0x15]	49984	1			T75	5		T77	117		T82	1
valid_sources[0x16]	49710	1			T77	209		T452	47		T559	4
valid_sources[0x17]	51520	1			T75	7		T77	106		T82	4
valid_sources[0x18]	49560	1			T75	1		T77	120		T82	3
valid_sources[0x19]	50665	1			T75	1		T77	77		T83	1
valid_sources[0x1a]	49679	1			T75	4		T77	142		T452	45
valid_sources[0x1b]	50288	1			T75	4		T77	180		T82	3
valid_sources[0x1c]	50171	1			T77	80		T82	5		T83	1
valid_sources[0x1d]	49769	1			T75	1		T77	189		T82	9
valid_sources[0x1e]	51097	1			T75	2		T77	141		T82	4
valid_sources[0x1f]	49931	1			T75	1		T77	186		T82	2
valid_sources[0x20]	50099	1			T77	99		T82	2		T84	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

46227

1

T75

1

T77

120

T82

2

values[0x0]

all_enables

biggest_size

346597

1

T75

16

T77

964

T82

30

values[0x1]

all_enables

biggest_size

46183

1

T75

4

T77

125

T82

2