Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	528837094	62528539	0	0
DepthKnown_A	528837094	528729955	0	0
RvalidKnown_A	528837094	528729955	0	0
WreadyKnown_A	528837094	528729955	0	0
gen_passthru_fifo.paramCheckPass	1025	1025	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	528837094	62528539	0	0
T1	60765	5665	0	0
T2	90758	8916	0	0
T3	145373	19554	0	0
T4	286885	30529	0	0
T5	101903	578492	0	0
T30	220460	19863	0	0
T59	569859	82614	0	0
T63	293856	38871	0	0
T90	87223	11705	0	0
T91	211718	21210	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	528837094	528729955	0	0
T1	60765	60707	0	0
T2	90758	90707	0	0
T3	145373	145315	0	0
T4	286885	286779	0	0
T5	101903	101843	0	0
T30	220460	220354	0	0
T59	569859	569757	0	0
T63	293856	293736	0	0
T90	87223	87172	0	0
T91	211718	211663	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	528837094	528729955	0	0
T1	60765	60707	0	0
T2	90758	90707	0	0
T3	145373	145315	0	0
T4	286885	286779	0	0
T5	101903	101843	0	0
T30	220460	220354	0	0
T59	569859	569757	0	0
T63	293856	293736	0	0
T90	87223	87172	0	0
T91	211718	211663	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	528837094	528729955	0	0
T1	60765	60707	0	0
T2	90758	90707	0	0
T3	145373	145315	0	0
T4	286885	286779	0	0
T5	101903	101843	0	0
T30	220460	220354	0	0
T59	569859	569757	0	0
T63	293856	293736	0	0
T90	87223	87172	0	0
T91	211718	211663	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1025	1025	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T30	1	1	0	0
T59	1	1	0	0
T63	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	528837094	47986435	0	0
DepthKnown_A	528837094	528729955	0	0
RvalidKnown_A	528837094	528729955	0	0
WreadyKnown_A	528837094	528729955	0	0
gen_passthru_fifo.paramCheckPass	1025	1025	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	528837094	47986435	0	0
T1	60765	3998	0	0
T2	90758	6719	0	0
T3	145373	14371	0	0
T4	286885	23521	0	0
T5	101903	293137	0	0
T30	220460	15656	0	0
T59	569859	57637	0	0
T63	293856	29083	0	0
T90	87223	8507	0	0
T91	211718	17298	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	528837094	528729955	0	0
T1	60765	60707	0	0
T2	90758	90707	0	0
T3	145373	145315	0	0
T4	286885	286779	0	0
T5	101903	101843	0	0
T30	220460	220354	0	0
T59	569859	569757	0	0
T63	293856	293736	0	0
T90	87223	87172	0	0
T91	211718	211663	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	528837094	528729955	0	0
T1	60765	60707	0	0
T2	90758	90707	0	0
T3	145373	145315	0	0
T4	286885	286779	0	0
T5	101903	101843	0	0
T30	220460	220354	0	0
T59	569859	569757	0	0
T63	293856	293736	0	0
T90	87223	87172	0	0
T91	211718	211663	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	528837094	528729955	0	0
T1	60765	60707	0	0
T2	90758	90707	0	0
T3	145373	145315	0	0
T4	286885	286779	0	0
T5	101903	101843	0	0
T30	220460	220354	0	0
T59	569859	569757	0	0
T63	293856	293736	0	0
T90	87223	87172	0	0
T91	211718	211663	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1025	1025	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T30	1	1	0	0
T59	1	1	0	0
T63	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	528837094	45592276	0	0
DepthKnown_A	528837094	528729955	0	0
RvalidKnown_A	528837094	528729955	0	0
WreadyKnown_A	528837094	528729955	0	0
gen_passthru_fifo.paramCheckPass	1025	1025	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	528837094	45592276	0	0
T1	60765	3273	0	0
T2	90758	4663	0	0
T3	145373	8227	0	0
T4	286885	16247	0	0
T5	101903	50969	0	0
T30	220460	11468	0	0
T59	569859	31965	0	0
T63	293856	20688	0	0
T90	87223	5484	0	0
T91	211718	20091	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	528837094	528729955	0	0
T1	60765	60707	0	0
T2	90758	90707	0	0
T3	145373	145315	0	0
T4	286885	286779	0	0
T5	101903	101843	0	0
T30	220460	220354	0	0
T59	569859	569757	0	0
T63	293856	293736	0	0
T90	87223	87172	0	0
T91	211718	211663	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	528837094	528729955	0	0
T1	60765	60707	0	0
T2	90758	90707	0	0
T3	145373	145315	0	0
T4	286885	286779	0	0
T5	101903	101843	0	0
T30	220460	220354	0	0
T59	569859	569757	0	0
T63	293856	293736	0	0
T90	87223	87172	0	0
T91	211718	211663	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	528837094	528729955	0	0
T1	60765	60707	0	0
T2	90758	90707	0	0
T3	145373	145315	0	0
T4	286885	286779	0	0
T5	101903	101843	0	0
T30	220460	220354	0	0
T59	569859	569757	0	0
T63	293856	293736	0	0
T90	87223	87172	0	0
T91	211718	211663	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1025	1025	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T30	1	1	0	0
T59	1	1	0	0
T63	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	528837094	38377655	0	0
DepthKnown_A	528837094	528729955	0	0
RvalidKnown_A	528837094	528729955	0	0
WreadyKnown_A	528837094	528729955	0	0
gen_passthru_fifo.paramCheckPass	1025	1025	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	528837094	38377655	0	0
T1	60765	3159	0	0
T2	90758	4523	0	0
T3	145373	7949	0	0
T4	286885	15894	0	0
T5	101903	47818	0	0
T30	220460	11223	0	0
T59	569859	31062	0	0
T63	293856	20296	0	0
T90	87223	5362	0	0
T91	211718	19887	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	528837094	528729955	0	0
T1	60765	60707	0	0
T2	90758	90707	0	0
T3	145373	145315	0	0
T4	286885	286779	0	0
T5	101903	101843	0	0
T30	220460	220354	0	0
T59	569859	569757	0	0
T63	293856	293736	0	0
T90	87223	87172	0	0
T91	211718	211663	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	528837094	528729955	0	0
T1	60765	60707	0	0
T2	90758	90707	0	0
T3	145373	145315	0	0
T4	286885	286779	0	0
T5	101903	101843	0	0
T30	220460	220354	0	0
T59	569859	569757	0	0
T63	293856	293736	0	0
T90	87223	87172	0	0
T91	211718	211663	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	528837094	528729955	0	0
T1	60765	60707	0	0
T2	90758	90707	0	0
T3	145373	145315	0	0
T4	286885	286779	0	0
T5	101903	101843	0	0
T30	220460	220354	0	0
T59	569859	569757	0	0
T63	293856	293736	0	0
T90	87223	87172	0	0
T91	211718	211663	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1025	1025	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T30	1	1	0	0
T59	1	1	0	0
T63	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	629400105	99829	0	0
DepthKnown_A	629400105	629277000	0	0
RvalidKnown_A	629400105	629277000	0	0
WreadyKnown_A	629400105	629277000	0	0
gen_passthru_fifo.paramCheckPass	2935	2935	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	629400105	99829	0	0
T1	60765	13	0	0
T2	90758	19	0	0
T3	145373	26	0	0
T4	286885	102	0	0
T5	101903	98	0	0
T30	220460	30	0	0
T59	569859	87	0	0
T63	293856	151	0	0
T90	87223	13	0	0
T91	211718	53	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	629400105	629277000	0	0
T1	60765	60707	0	0
T2	90758	90707	0	0
T3	145373	145315	0	0
T4	286885	286779	0	0
T5	101903	101843	0	0
T30	220460	220354	0	0
T59	569859	569757	0	0
T63	293856	293736	0	0
T90	87223	87172	0	0
T91	211718	211663	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	629400105	629277000	0	0
T1	60765	60707	0	0
T2	90758	90707	0	0
T3	145373	145315	0	0
T4	286885	286779	0	0
T5	101903	101843	0	0
T30	220460	220354	0	0
T59	569859	569757	0	0
T63	293856	293736	0	0
T90	87223	87172	0	0
T91	211718	211663	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	629400105	629277000	0	0
T1	60765	60707	0	0
T2	90758	90707	0	0
T3	145373	145315	0	0
T4	286885	286779	0	0
T5	101903	101843	0	0
T30	220460	220354	0	0
T59	569859	569757	0	0
T63	293856	293736	0	0
T90	87223	87172	0	0
T91	211718	211663	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2935	2935	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T30	1	1	0	0
T59	1	1	0	0
T63	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	629400105	103263	0	0
DepthKnown_A	629400105	629277000	0	0
RvalidKnown_A	629400105	629277000	0	0
WreadyKnown_A	629400105	629277000	0	0
gen_passthru_fifo.paramCheckPass	2935	2935	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	629400105	103263	0	0
T1	60765	13	0	0
T2	90758	19	0	0
T3	145373	26	0	0
T4	286885	102	0	0
T5	101903	98	0	0
T30	220460	30	0	0
T59	569859	87	0	0
T63	293856	151	0	0
T90	87223	13	0	0
T91	211718	53	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	629400105	629277000	0	0
T1	60765	60707	0	0
T2	90758	90707	0	0
T3	145373	145315	0	0
T4	286885	286779	0	0
T5	101903	101843	0	0
T30	220460	220354	0	0
T59	569859	569757	0	0
T63	293856	293736	0	0
T90	87223	87172	0	0
T91	211718	211663	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	629400105	629277000	0	0
T1	60765	60707	0	0
T2	90758	90707	0	0
T3	145373	145315	0	0
T4	286885	286779	0	0
T5	101903	101843	0	0
T30	220460	220354	0	0
T59	569859	569757	0	0
T63	293856	293736	0	0
T90	87223	87172	0	0
T91	211718	211663	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	629400105	629277000	0	0
T1	60765	60707	0	0
T2	90758	90707	0	0
T3	145373	145315	0	0
T4	286885	286779	0	0
T5	101903	101843	0	0
T30	220460	220354	0	0
T59	569859	569757	0	0
T63	293856	293736	0	0
T90	87223	87172	0	0
T91	211718	211663	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2935	2935	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T30	1	1	0	0
T59	1	1	0	0
T63	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	629400105	52461	0	0
DepthKnown_A	629400105	629277000	0	0
RvalidKnown_A	629400105	629277000	0	0
WreadyKnown_A	629400105	629277000	0	0
gen_passthru_fifo.paramCheckPass	2935	2935	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	629400105	52461	0	0
T1	60765	12	0	0
T2	90758	18	0	0
T3	145373	23	0	0
T4	286885	94	0	0
T5	101903	98	0	0
T30	220460	28	0	0
T59	569859	77	0	0
T63	293856	95	0	0
T90	87223	12	0	0
T91	211718	52	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	629400105	629277000	0	0
T1	60765	60707	0	0
T2	90758	90707	0	0
T3	145373	145315	0	0
T4	286885	286779	0	0
T5	101903	101843	0	0
T30	220460	220354	0	0
T59	569859	569757	0	0
T63	293856	293736	0	0
T90	87223	87172	0	0
T91	211718	211663	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	629400105	629277000	0	0
T1	60765	60707	0	0
T2	90758	90707	0	0
T3	145373	145315	0	0
T4	286885	286779	0	0
T5	101903	101843	0	0
T30	220460	220354	0	0
T59	569859	569757	0	0
T63	293856	293736	0	0
T90	87223	87172	0	0
T91	211718	211663	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	629400105	629277000	0	0
T1	60765	60707	0	0
T2	90758	90707	0	0
T3	145373	145315	0	0
T4	286885	286779	0	0
T5	101903	101843	0	0
T30	220460	220354	0	0
T59	569859	569757	0	0
T63	293856	293736	0	0
T90	87223	87172	0	0
T91	211718	211663	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2935	2935	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T30	1	1	0	0
T59	1	1	0	0
T63	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	629400105	52461	0	0
DepthKnown_A	629400105	629277000	0	0
RvalidKnown_A	629400105	629277000	0	0
WreadyKnown_A	629400105	629277000	0	0
gen_passthru_fifo.paramCheckPass	2935	2935	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	629400105	52461	0	0
T1	60765	12	0	0
T2	90758	18	0	0
T3	145373	23	0	0
T4	286885	94	0	0
T5	101903	98	0	0
T30	220460	28	0	0
T59	569859	77	0	0
T63	293856	95	0	0
T90	87223	12	0	0
T91	211718	52	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	629400105	629277000	0	0
T1	60765	60707	0	0
T2	90758	90707	0	0
T3	145373	145315	0	0
T4	286885	286779	0	0
T5	101903	101843	0	0
T30	220460	220354	0	0
T59	569859	569757	0	0
T63	293856	293736	0	0
T90	87223	87172	0	0
T91	211718	211663	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	629400105	629277000	0	0
T1	60765	60707	0	0
T2	90758	90707	0	0
T3	145373	145315	0	0
T4	286885	286779	0	0
T5	101903	101843	0	0
T30	220460	220354	0	0
T59	569859	569757	0	0
T63	293856	293736	0	0
T90	87223	87172	0	0
T91	211718	211663	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	629400105	629277000	0	0
T1	60765	60707	0	0
T2	90758	90707	0	0
T3	145373	145315	0	0
T4	286885	286779	0	0
T5	101903	101843	0	0
T30	220460	220354	0	0
T59	569859	569757	0	0
T63	293856	293736	0	0
T90	87223	87172	0	0
T91	211718	211663	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2935	2935	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T30	1	1	0	0
T59	1	1	0	0
T63	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	629400105	47368	0	0
DepthKnown_A	629400105	629277000	0	0
RvalidKnown_A	629400105	629277000	0	0
WreadyKnown_A	629400105	629277000	0	0
gen_passthru_fifo.paramCheckPass	2935	2935	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	629400105	47368	0	0
T1	60765	1	0	0
T2	90758	1	0	0
T3	145373	3	0	0
T4	286885	8	0	0
T5	101903	0	0	0
T30	220460	2	0	0
T59	569859	10	0	0
T63	293856	56	0	0
T90	87223	1	0	0
T91	211718	1	0	0
T203	0	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	629400105	629277000	0	0
T1	60765	60707	0	0
T2	90758	90707	0	0
T3	145373	145315	0	0
T4	286885	286779	0	0
T5	101903	101843	0	0
T30	220460	220354	0	0
T59	569859	569757	0	0
T63	293856	293736	0	0
T90	87223	87172	0	0
T91	211718	211663	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	629400105	629277000	0	0
T1	60765	60707	0	0
T2	90758	90707	0	0
T3	145373	145315	0	0
T4	286885	286779	0	0
T5	101903	101843	0	0
T30	220460	220354	0	0
T59	569859	569757	0	0
T63	293856	293736	0	0
T90	87223	87172	0	0
T91	211718	211663	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	629400105	629277000	0	0
T1	60765	60707	0	0
T2	90758	90707	0	0
T3	145373	145315	0	0
T4	286885	286779	0	0
T5	101903	101843	0	0
T30	220460	220354	0	0
T59	569859	569757	0	0
T63	293856	293736	0	0
T90	87223	87172	0	0
T91	211718	211663	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2935	2935	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T30	1	1	0	0
T59	1	1	0	0
T63	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	629400105	50802	0	0
DepthKnown_A	629400105	629277000	0	0
RvalidKnown_A	629400105	629277000	0	0
WreadyKnown_A	629400105	629277000	0	0
gen_passthru_fifo.paramCheckPass	2935	2935	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	629400105	50802	0	0
T1	60765	1	0	0
T2	90758	1	0	0
T3	145373	3	0	0
T4	286885	8	0	0
T5	101903	0	0	0
T30	220460	2	0	0
T59	569859	10	0	0
T63	293856	56	0	0
T90	87223	1	0	0
T91	211718	1	0	0
T203	0	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	629400105	629277000	0	0
T1	60765	60707	0	0
T2	90758	90707	0	0
T3	145373	145315	0	0
T4	286885	286779	0	0
T5	101903	101843	0	0
T30	220460	220354	0	0
T59	569859	569757	0	0
T63	293856	293736	0	0
T90	87223	87172	0	0
T91	211718	211663	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	629400105	629277000	0	0
T1	60765	60707	0	0
T2	90758	90707	0	0
T3	145373	145315	0	0
T4	286885	286779	0	0
T5	101903	101843	0	0
T30	220460	220354	0	0
T59	569859	569757	0	0
T63	293856	293736	0	0
T90	87223	87172	0	0
T91	211718	211663	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	629400105	629277000	0	0
T1	60765	60707	0	0
T2	90758	90707	0	0
T3	145373	145315	0	0
T4	286885	286779	0	0
T5	101903	101843	0	0
T30	220460	220354	0	0
T59	569859	569757	0	0
T63	293856	293736	0	0
T90	87223	87172	0	0
T91	211718	211663	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2935	2935	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T30	1	1	0	0
T59	1	1	0	0
T63	1	1	0	0
T90	1	1	0	0
T91	1	1	0	0