Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T59,T30	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T91,T44,T95	Yes	T91,T44,T95	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T91,T44,T95	Yes	T91,T44,T95	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T7,*T78,*T79	Yes	T7,T78,T79	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T7,T80,T81	Yes	T7,T80,T81	INPUT
tl_i.a_valid	Yes	Yes	T91,T44,T95	Yes	T91,T44,T95	INPUT
tl_o.a_ready	Yes	Yes	T91,T44,T95	Yes	T91,T44,T95	OUTPUT
tl_o.d_error	Yes	Yes	T75,T76,T77	Yes	T76,T77,T82	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T91,T44,T95	Yes	T91,T44,T95	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T91,T44,T95	Yes	T91,T44,T95	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T91,T44,T95	Yes	T91,T44,T95	OUTPUT
tl_o.d_sink	Yes	Yes	T77,T82,T84	Yes	T77,T82,T84	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T78,*T265,*T77	Yes	T78,T265,T75	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T76,T77,T82	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T91,*T44,*T95	Yes	T91,T44,T95	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T91,T44,T95	Yes	T91,T44,T95	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T59,T85,T282	Yes	T59,T85,T282	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T59,T85,T164	Yes	T59,T85,T164	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T59,T85,T164	Yes	T59,T85,T164	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T59,T85,T282	Yes	T59,T85,T282	OUTPUT
cio_rx_i	Yes	Yes	T4,T91,T30	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T91,T44,T95	Yes	T91,T44,T95	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T91,T95,T307	Yes	T91,T95,T307	OUTPUT
intr_tx_empty_o	Yes	Yes	T91,T95,T307	Yes	T91,T95,T307	OUTPUT
intr_rx_watermark_o	Yes	Yes	T91,T95,T307	Yes	T91,T95,T307	OUTPUT
intr_tx_done_o	Yes	Yes	T91,T95,T307	Yes	T91,T95,T307	OUTPUT
intr_rx_overflow_o	Yes	Yes	T91,T95,T307	Yes	T91,T95,T307	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T328,T329,T330	Yes	T328,T329,T330	OUTPUT
intr_rx_break_err_o	Yes	Yes	T328,T329,T330	Yes	T328,T329,T330	OUTPUT
intr_rx_timeout_o	Yes	Yes	T328,T329,T330	Yes	T328,T329,T330	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T328,T329,T330	Yes	T328,T329,T330	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	40	40	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T59,T30	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T44,T95,T45	Yes	T44,T95,T45	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T44,T95,T45	Yes	T44,T95,T45	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T7,*T78,*T79	Yes	T7,T78,T79	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T7,T80,T81	Yes	T7,T80,T81	INPUT
tl_i.a_valid	Yes	Yes	T44,T95,T45	Yes	T44,T95,T45	INPUT
tl_o.a_ready	Yes	Yes	T44,T95,T45	Yes	T44,T95,T45	OUTPUT
tl_o.d_error	Yes	Yes	T75,T76,T77	Yes	T76,T77,T82	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T44,T95,T45	Yes	T44,T95,T45	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T44,T95,T45	Yes	T44,T95,T45	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T44,T95,T45	Yes	T44,T95,T45	OUTPUT
tl_o.d_sink	Yes	Yes	T77,T82,T84	Yes	T77,T82,T84	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T78,*T265,*T77	Yes	T78,T265,T77	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T76,T77,T82	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T44,*T95,*T45	Yes	T44,T95,T45	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T44,T95,T45	Yes	T44,T95,T45	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T59,T85,T164	Yes	T59,T85,T164	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T59,T85,T164	Yes	T59,T85,T164	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T59,T85,T164	Yes	T59,T85,T164	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T59,T85,T164	Yes	T59,T85,T164	OUTPUT
cio_rx_i	Yes	Yes	T4,T30,T5	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T44,T95,T45	Yes	T44,T95,T45	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T95,T307,T308	Yes	T95,T307,T308	OUTPUT
intr_tx_empty_o	Yes	Yes	T95,T307,T308	Yes	T95,T307,T308	OUTPUT
intr_rx_watermark_o	Yes	Yes	T95,T307,T308	Yes	T95,T307,T308	OUTPUT
intr_tx_done_o	Yes	Yes	T95,T307,T308	Yes	T95,T307,T308	OUTPUT
intr_rx_overflow_o	Yes	Yes	T95,T307,T308	Yes	T95,T307,T308	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T328,T329,T330	Yes	T328,T329,T330	OUTPUT
intr_rx_break_err_o	Yes	Yes	T328,T329,T330	Yes	T328,T329,T330	OUTPUT
intr_rx_timeout_o	Yes	Yes	T328,T329,T330	Yes	T328,T329,T330	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T328,T329,T330	Yes	T328,T329,T330	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T59,T30	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T91,T12,T13	Yes	T91,T12,T13	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T91,T12,T13	Yes	T91,T12,T13	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T7,*T78,*T79	Yes	T7,T78,T79	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T7,T80,T81	Yes	T7,T80,T81	INPUT
tl_i.a_valid	Yes	Yes	T91,T12,T13	Yes	T91,T12,T13	INPUT
tl_o.a_ready	Yes	Yes	T91,T12,T13	Yes	T91,T12,T13	OUTPUT
tl_o.d_error	Yes	Yes	T76,T77,T84	Yes	T76,T77,T84	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T91,T12,T13	Yes	T91,T12,T13	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T91,T12,T13	Yes	T91,T12,T13	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T91,T12,T13	Yes	T91,T12,T13	OUTPUT
tl_o.d_sink	Yes	Yes	T77,T82,T84	Yes	T77,T82,T84	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T77,*T82,*T83	Yes	T77,T82,T84	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T91,*T12,*T13	Yes	T91,T12,T13	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T91,T12,T13	Yes	T91,T12,T13	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T59,T85,T87	Yes	T59,T85,T87	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T59,T85,T87	Yes	T59,T85,T87	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T59,T85,T87	Yes	T59,T85,T87	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T59,T85,T87	Yes	T59,T85,T87	OUTPUT
cio_rx_i	Yes	Yes	T91,T220,T214	Yes	T91,T11,T8	INPUT
cio_tx_o	Yes	Yes	T91,T220,T214	Yes	T91,T220,T214	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T91,T220,T214	Yes	T91,T220,T214	OUTPUT
intr_tx_empty_o	Yes	Yes	T91,T220,T214	Yes	T91,T220,T214	OUTPUT
intr_rx_watermark_o	Yes	Yes	T91,T220,T214	Yes	T91,T220,T214	OUTPUT
intr_tx_done_o	Yes	Yes	T91,T220,T214	Yes	T91,T220,T214	OUTPUT
intr_rx_overflow_o	Yes	Yes	T91,T220,T214	Yes	T91,T220,T214	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T328,T329,T330	Yes	T328,T329,T330	OUTPUT
intr_rx_break_err_o	Yes	Yes	T328,T329,T330	Yes	T328,T329,T330	OUTPUT
intr_rx_timeout_o	Yes	Yes	T328,T329,T330	Yes	T328,T329,T330	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T328,T329,T330	Yes	T328,T329,T330	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	40	40	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T59,T30	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T12,T154,T13	Yes	T12,T154,T13	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T12,T154,T13	Yes	T12,T154,T13	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T7,*T78,*T79	Yes	T7,T78,T79	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T7,T80,T81	Yes	T7,T80,T81	INPUT
tl_i.a_valid	Yes	Yes	T12,T154,T13	Yes	T12,T154,T13	INPUT
tl_o.a_ready	Yes	Yes	T12,T154,T13	Yes	T12,T154,T13	OUTPUT
tl_o.d_error	Yes	Yes	T75,T76,T77	Yes	T76,T77,T84	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T12,T154,T13	Yes	T12,T154,T13	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T12,T154,T13	Yes	T12,T154,T13	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T12,T154,T13	Yes	T12,T154,T13	OUTPUT
tl_o.d_sink	Yes	Yes	T77,T84,T83	Yes	T77,T84,T83	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T77,*T83,*T452	Yes	T75,T77,T84	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T76,T77,T84	Yes	T76,T77,T84	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T12,*T154,*T13	Yes	T12,T154,T13	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T12,T154,T13	Yes	T12,T154,T13	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T59,T85,T267	Yes	T59,T85,T267	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T59,T85,T267	Yes	T59,T85,T267	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T59,T85,T267	Yes	T59,T85,T267	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T59,T85,T267	Yes	T59,T85,T267	OUTPUT
cio_rx_i	Yes	Yes	T154,T339,T342	Yes	T154,T339,T342	INPUT
cio_tx_o	Yes	Yes	T154,T339,T342	Yes	T154,T339,T342	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T154,T339,T328	Yes	T154,T339,T328	OUTPUT
intr_tx_empty_o	Yes	Yes	T154,T339,T328	Yes	T154,T339,T328	OUTPUT
intr_rx_watermark_o	Yes	Yes	T154,T339,T328	Yes	T154,T339,T328	OUTPUT
intr_tx_done_o	Yes	Yes	T154,T339,T328	Yes	T154,T339,T328	OUTPUT
intr_rx_overflow_o	Yes	Yes	T154,T339,T328	Yes	T154,T339,T328	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T328,T329,T330	Yes	T328,T329,T330	OUTPUT
intr_rx_break_err_o	Yes	Yes	T328,T329,T330	Yes	T328,T329,T330	OUTPUT
intr_rx_timeout_o	Yes	Yes	T328,T329,T330	Yes	T328,T329,T330	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T328,T329,T330	Yes	T328,T329,T330	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	40	40	100.00
Total Bits	308	308	100.00
Total Bits 0->1	154	154	100.00
Total Bits 1->0	154	154	100.00

Ports	40	40	100.00
Port Bits	308	308	100.00
Port Bits 0->1	154	154	100.00
Port Bits 1->0	154	154	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T59,T30	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T14,T12,T127	Yes	T14,T12,T127	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T14,T12,T127	Yes	T14,T12,T127	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T75,*T76,*T77	Yes	T75,T76,T77	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T7,*T78,*T79	Yes	T7,T78,T79	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T75,T76,T77	Yes	T75,T76,T77	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T7,T80,T81	Yes	T7,T80,T81	INPUT
tl_i.a_valid	Yes	Yes	T14,T12,T127	Yes	T14,T12,T127	INPUT
tl_o.a_ready	Yes	Yes	T14,T12,T127	Yes	T14,T12,T127	OUTPUT
tl_o.d_error	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T14,T12,T127	Yes	T14,T12,T127	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T14,T12,T127	Yes	T14,T12,T127	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T14,T12,T127	Yes	T14,T12,T127	OUTPUT
tl_o.d_sink	Yes	Yes	T77,T82,T84	Yes	T77,T82,T84	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T77,*T82,*T83	Yes	T77,T82,T84	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T76,T77,T82	Yes	T76,T77,T82	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T14,*T12,*T127	Yes	T14,T12,T127	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T14,T12,T127	Yes	T14,T12,T127	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T59,T85,T282	Yes	T59,T85,T282	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T59,T85,T87	Yes	T59,T85,T87	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T59,T85,T87	Yes	T59,T85,T87	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T59,T85,T282	Yes	T59,T85,T282	OUTPUT
cio_rx_i	Yes	Yes	T14,T127,T327	Yes	T14,T127,T327	INPUT
cio_tx_o	Yes	Yes	T14,T127,T327	Yes	T14,T127,T327	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T14,T127,T327	Yes	T14,T127,T327	OUTPUT
intr_tx_empty_o	Yes	Yes	T14,T127,T327	Yes	T14,T127,T327	OUTPUT
intr_rx_watermark_o	Yes	Yes	T14,T127,T327	Yes	T14,T127,T327	OUTPUT
intr_tx_done_o	Yes	Yes	T14,T127,T327	Yes	T14,T127,T327	OUTPUT
intr_rx_overflow_o	Yes	Yes	T14,T127,T327	Yes	T14,T127,T327	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T328,T329,T330	Yes	T328,T329,T330	OUTPUT
intr_rx_break_err_o	Yes	Yes	T328,T329,T330	Yes	T328,T329,T330	OUTPUT
intr_rx_timeout_o	Yes	Yes	T328,T329,T330	Yes	T328,T329,T330	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T328,T329,T330	Yes	T328,T329,T330	OUTPUT

*Tests covering at least one bit in the range